northbridge/amd/amdht/ht_wrapper.c
northbridge/amd/amdfam10/raminit_amdmct.c
cpu/amd/model_10xxx/fidvid.c
pc80/mc146818rtc_early.c
They are now included by the fam10 chipset code that requires them.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5548
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
13 files changed:
*/
#include <string.h>
#include <arch/stages.h>
*/
#include <string.h>
#include <arch/stages.h>
+#include <cpu/x86/mtrr.h>
#include "cpu/amd/car/disable_cache_as_ram.c"
#include "cpu/amd/car/disable_cache_as_ram.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
static inline void print_debug_pcar(const char *strval, uint32_t val)
{
static inline void print_debug_pcar(const char *strval, uint32_t val)
{
-#include "../../../northbridge/amd/amdht/AsPsDefs.h"
+#include <northbridge/amd/amdht/AsPsDefs.h>
#define SET_FIDVID_DEBUG 1
#define SET_FIDVID_DEBUG 1
#include <northbridge/amd/amdht/AsPsDefs.h>
#include <northbridge/amd/amdht/porting.h>
#include <northbridge/amd/amdht/AsPsDefs.h>
#include <northbridge/amd/amdht/porting.h>
+#include <cpu/x86/mtrr/earlymtrr.c>
+#include <northbridge/amd/amdfam10/raminit_amdmct.c>
+
//it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID
#ifndef SET_FIDVID
#define SET_FIDVID 1
//it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID
#ifndef SET_FIDVID
#define SET_FIDVID 1
*/
#include <console/console.h>
*/
#include <console/console.h>
+#include <pc80/mc146818rtc_early.c>
+#include <northbridge/amd/amdht/ht_wrapper.c>
#ifndef SET_NB_CFG_54
#define SET_NB_CFG_54 1
#ifndef SET_NB_CFG_54
#define SET_NB_CFG_54 1
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "option_table.h"
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
#include <console/console.h>
#include "lib/ramtest.c"
#include <cpu/amd/model_10xxx_rev.h>
#include <console/console.h>
#include "lib/ramtest.c"
#include <cpu/amd/model_10xxx_rev.h>
}
#include "northbridge/amd/amdfam10/amdfam10.h"
}
#include "northbridge/amd/amdfam10/amdfam10.h"
-#include "northbridge/amd/amdht/ht_wrapper.c"
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/raminit_amdmct.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
#include "resourcemap.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
#include "resourcemap.c"
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
-#include "cpu/amd/model_10xxx/fidvid.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "option_table.h"
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
#include <console/console.h>
#include "lib/ramtest.c"
#include <cpu/amd/model_10xxx_rev.h>
#include <console/console.h>
#include "lib/ramtest.c"
#include <cpu/amd/model_10xxx_rev.h>
}
#include "northbridge/amd/amdfam10/amdfam10.h"
}
#include "northbridge/amd/amdfam10/amdfam10.h"
-#include "northbridge/amd/amdht/ht_wrapper.c"
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/raminit_amdmct.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
#include "resourcemap.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
#include "resourcemap.c"
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
-#include "cpu/amd/model_10xxx/fidvid.c"
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "option_table.h"
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
#include <console/console.h>
#include "lib/ramtest.c"
#include <cpu/amd/model_10xxx_rev.h>
#include <console/console.h>
#include "lib/ramtest.c"
#include <cpu/amd/model_10xxx_rev.h>
}
#include "northbridge/amd/amdfam10/amdfam10.h"
}
#include "northbridge/amd/amdfam10/amdfam10.h"
-#include "northbridge/amd/amdht/ht_wrapper.c"
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/raminit_amdmct.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
#include "resourcemap.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
#include "resourcemap.c"
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
-#include "cpu/amd/model_10xxx/fidvid.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "option_table.h"
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
#include <console/console.h>
#if CONFIG_USBDEBUG_DIRECT
#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
#include <console/console.h>
#if CONFIG_USBDEBUG_DIRECT
#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
}
#include "northbridge/amd/amdfam10/amdfam10.h"
}
#include "northbridge/amd/amdfam10/amdfam10.h"
-#include "northbridge/amd/amdht/ht_wrapper.c"
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/raminit_amdmct.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
#include "resourcemap.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
#include "resourcemap.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
-#include "cpu/amd/model_10xxx/fidvid.c"
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "option_table.h"
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
#include <console/console.h>
#include "lib/ramtest.c"
#include <console/console.h>
#include "lib/ramtest.c"
}
#include "northbridge/amd/amdfam10/amdfam10.h"
}
#include "northbridge/amd/amdfam10/amdfam10.h"
-#include "northbridge/amd/amdht/ht_wrapper.c"
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/raminit_amdmct.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
#include "resourcemap.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
#include "resourcemap.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
-#include "cpu/amd/model_10xxx/fidvid.c"
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "option_table.h"
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
#include <console/console.h>
#include "lib/ramtest.c"
#include <console/console.h>
#include "lib/ramtest.c"
}
#include "northbridge/amd/amdfam10/amdfam10.h"
}
#include "northbridge/amd/amdfam10/amdfam10.h"
-#include "northbridge/amd/amdht/ht_wrapper.c"
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/raminit_amdmct.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
#include "resourcemap.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
#include "resourcemap.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
-#include "cpu/amd/model_10xxx/fidvid.c"
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "option_table.h"
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
#include <console/console.h>
#if CONFIG_USBDEBUG_DIRECT
#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
#include <console/console.h>
#if CONFIG_USBDEBUG_DIRECT
#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
}
#include "northbridge/amd/amdfam10/amdfam10.h"
}
#include "northbridge/amd/amdfam10/amdfam10.h"
-#include "northbridge/amd/amdht/ht_wrapper.c"
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/raminit_amdmct.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
#include "resourcemap.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
#include "resourcemap.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
-#include "cpu/amd/model_10xxx/fidvid.c"
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c"
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
static void set_htic_bit(u8 i, u32 val, u8 bit)
{
static void set_htic_bit(u8 i, u32 val, u8 bit)
{
#ifndef HTTOPO_H
#define HTTOPO_H
#ifndef HTTOPO_H
#define HTTOPO_H
/*----------------------------------------------------------------------------
* Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
*
/*----------------------------------------------------------------------------
* Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
*