Don't declare a handler for int 0x1c - the default handler is sufficient.

diff --git a/src/clock.c b/src/clock.c
index ccc05f45e99adc3c687000afa7edc1c6c1c4bfc4..b27417837c8a18651bc473769f0097522c940c22 100644 (file)
--- a/src/clock.c
+++ b/src/clock.c
@@ -399,13 +399,6 @@ handle_1a(struct bregs *regs)
     }
 }
 
     }
 }
 

-// User Timer Tick
-void VISIBLE16
-handle_1c()
-{
-    debug_isr(DEBUG_ISR_1c);
-}
-

 // INT 08h System Timer ISR Entry Point
 void VISIBLE16
 handle_08()
 // INT 08h System Timer ISR Entry Point
 void VISIBLE16
 handle_08()

diff --git a/src/config.h b/src/config.h
index 50dbd58f9ad2112fd7d9d6cc22846a034e463f19..cb9b1daef5d5cacbe322668eb283d3f897571873 100644 (file)
--- a/src/config.h
+++ b/src/config.h
@@ -140,7 +140,6 @@
 #define DEBUG_HDL_18 1
 #define DEBUG_HDL_19 1
 #define DEBUG_HDL_1a 9
 #define DEBUG_HDL_18 1
 #define DEBUG_HDL_19 1
 #define DEBUG_HDL_1a 9

-#define DEBUG_ISR_1c 20

 #define DEBUG_HDL_40 1
 #define DEBUG_ISR_70 9
 #define DEBUG_ISR_74 9
 #define DEBUG_HDL_40 1
 #define DEBUG_ISR_70 9
 #define DEBUG_ISR_74 9

diff --git a/src/post.c b/src/post.c
index 6b42e3441eaad3372e7f7db612951bda7540790e..8ae5fcc0f6c91de68cd5ed24809b1f9e92a09c84 100644 (file)
--- a/src/post.c
+++ b/src/post.c
@@ -57,7 +57,6 @@ init_ivt()
     set_irq(0x18, entry_18);
     set_irq(0x19, entry_19_official);
     set_irq(0x1a, entry_1a);
     set_irq(0x18, entry_18);
     set_irq(0x19, entry_19_official);
     set_irq(0x1a, entry_1a);

-    set_irq(0x1c, entry_1c);

     set_irq(0x40, entry_40);
 
     // set vector 0x79 to zero
     set_irq(0x40, entry_40);
 
     // set vector 0x79 to zero

diff --git a/src/romlayout.S b/src/romlayout.S
index efae759ac511b90e18be18a3c3bb28d5508402f2..4e3cdab4275d8943a95e1f036b50d18d62a0f354 100644 (file)
--- a/src/romlayout.S
+++ b/src/romlayout.S
@@ -465,7 +465,6 @@ permanent_halt:
         DECL_IRQ_ENTRY_ARG 12
         DECL_IRQ_ENTRY_ARG 11
         DECL_IRQ_ENTRY 76
         DECL_IRQ_ENTRY_ARG 12
         DECL_IRQ_ENTRY_ARG 11
         DECL_IRQ_ENTRY 76

-        DECL_IRQ_ENTRY 1c

         DECL_IRQ_ENTRY 70
         DECL_IRQ_ENTRY 74
         DECL_IRQ_ENTRY 75
         DECL_IRQ_ENTRY 70
         DECL_IRQ_ENTRY 74
         DECL_IRQ_ENTRY 75