+#if DIMM_SUPPORT==0x0204 /* DDR2 and SO-DIMM, S1G1 */
+ dword = 0x00111222;
+ dwordx = 0x002F2F00;
+
+ switch (meminfo->memclk_set) {
+ case DCH_MemClkFreq_200MHz: /* nothing to be set here */
+ break;
+ case DCH_MemClkFreq_266MHz:
+ if ((meminfo->single_rank_mask == 0)
+ && (meminfo->x4_mask == 0) && (meminfo->x16_mask))
+ dwordx = 0x002C2C00; /* Double rank x8 */
+ /* else SRx16, SRx8, DRx16 == 0x002F2F00 */
+ break;
+ case DCH_MemClkFreq_333MHz:
+ if ((meminfo->single_rank_mask == 1)
+ && (meminfo->x16_mask == 1)) /* SR x16 */
+ dwordx = 0x00272700;
+ else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0)
+ && (meminfo->single_rank_mask == 0)) { /* DR x8 */
+ SlowAccessMode = 1;
+ dwordx = 0x00002800;
+ } else { /* SR x8, DR x16 */
+ dwordx = 0x002A2A00;
+ }
+ break;
+ case DCH_MemClkFreq_400MHz:
+ if ((meminfo->single_rank_mask == 1)
+ && (meminfo->x16_mask == 1)) /* SR x16 */
+ dwordx = 0x00292900;
+ else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0)
+ && (meminfo->single_rank_mask == 0)) { /* DR x8 */
+ SlowAccessMode = 1;
+ dwordx = 0x00002A00;
+ } else { /* SR x8, DR x16 */
+ dwordx = 0x002A2A00;
+ }
+ break;
+ }
+#endif
+