Whitespace changes to make s2912_fam10/ms9652_fam10 more similar.

Also, fix another typo in the ms9652 board name.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5184 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig b/src/mainboard/msi/ms9652_fam10/Kconfig
index abc1aebb61dfd2f3c14deaf1db38b005253b8768..c595f63b3b888e7a4c860418667b277eac35d9f8 100644 (file)
--- a/src/mainboard/msi/ms9652_fam10/Kconfig
+++ b/src/mainboard/msi/ms9652_fam10/Kconfig
@@ -134,7 +134,7 @@ config LB_CKS_LOC
 
 config MAINBOARD_PART_NUMBER
        string
 
 config MAINBOARD_PART_NUMBER
        string

-       default "MS-9252"
+       default "MS-9652"

        depends on BOARD_MSI_MS9652_FAM10
 
 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
        depends on BOARD_MSI_MS9652_FAM10
 
 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID

diff --git a/src/mainboard/msi/ms9652_fam10/resourcemap.c b/src/mainboard/msi/ms9652_fam10/resourcemap.c
index 4fe4f4d7118fe5a4f83fde48e47df446f37a53b1..3bdb69abf5a039f1c42f2d984ed93e8f73b97d5e 100644 (file)
--- a/src/mainboard/msi/ms9652_fam10/resourcemap.c
+++ b/src/mainboard/msi/ms9652_fam10/resourcemap.c
@@ -161,7 +161,7 @@ static void setup_mb_resource_map(void)
                 *         1 = base/limit registers i are read-only
                 * [ 7: 4] Reserved
                 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
                 *         1 = base/limit registers i are read-only
                 * [ 7: 4] Reserved
                 * [31: 8] Memory-Mapped I/O Base Address i (39-16)

-                *         This field defines the upper address bits of a 40bit address 
+                *         This field defines the upper address bits of a 40bit address

                 *         that defines the start of memory-mapped I/O region i
                 */
                PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,
                 *         that defines the start of memory-mapped I/O region i
                 */
                PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,


@@ -218,7 +218,7 @@ static void setup_mb_resource_map(void)
                 * [ 3: 2] Reserved
                 * [ 4: 4] VGA Enable
                 *         0 = VGA matches Disabled
                 * [ 3: 2] Reserved
                 * [ 4: 4] VGA Enable
                 *         0 = VGA matches Disabled

-                *         1 = matches all address < 64K and where A[9:0] is in the 
+                *         1 = matches all address < 64K and where A[9:0] is in the

                 *             range 3B0-3BB or 3C0-3DF independen of the base & limit registers
                 * [ 5: 5] ISA Enable
                 *         0 = ISA matches Disabled
                 *             range 3B0-3BB or 3C0-3DF independen of the base & limit registers
                 * [ 5: 5] ISA Enable
                 *         0 = ISA matches Disabled


@@ -226,7 +226,7 @@ static void setup_mb_resource_map(void)
                 *             from matching agains this base/limit pair
                 * [11: 6] Reserved
                 * [24:12] PCI I/O Base i
                 *             from matching agains this base/limit pair
                 * [11: 6] Reserved
                 * [24:12] PCI I/O Base i

-                *         This field defines the start of PCI I/O region n 
+                *         This field defines the start of PCI I/O region n

                 * [31:25] Reserved
                 */
                /* Verified against board configuration registers after normal proprietary BIOS boot */
                 * [31:25] Reserved
                 */
                /* Verified against board configuration registers after normal proprietary BIOS boot */

diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index 96806609d9f25dbd5bee3d53c9b7126b2d81be56..f19147f11810c4aa785f789d2fd4373bd69b3b03 100644 (file)
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -50,9 +50,9 @@
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
 
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
 

- static void post_code(u8 value) {
-       outb(value, 0x80);
- }
+static void post_code(u8 value) {
+       outb(value, 0x80);
+}

 
 #if CONFIG_USE_FAILOVER_IMAGE==0
 #include "arch/i386/lib/console.c"
 
 #if CONFIG_USE_FAILOVER_IMAGE==0
 #include "arch/i386/lib/console.c"


@@ -153,20 +153,17 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 static void sio_setup(void)
 {
 
 static void sio_setup(void)
 {

+       unsigned value;
+       uint32_t dword;
+       uint8_t byte;

 
 

-        unsigned value;
-        uint32_t dword;
-        uint8_t byte;
-
-        byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
-        byte |= 0x20;
-        pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
-
-        dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
-        dword |= (1<<0);
-        pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
-
+       byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
+       byte |= 0x20;
+       pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);

 
 

+       dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
+       dword |= (1<<0);
+       pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);

 }
 
 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 }
 
 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)


@@ -281,10 +278,10 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #endif
 
        val = cpuid_eax(1);
 #endif
 
        val = cpuid_eax(1);

-       printk_debug("BSP Family_Model: %08x \n", val);
+       printk_debug("BSP Family_Model: %08x\n", val);

        printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
        printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");

-       printk_debug("bsp_apicid = %02x \n", bsp_apicid);
-       printk_debug("cpu_init_detectedx = %08x \n", cpu_init_detectedx);
+       printk_debug("bsp_apicid = %02x\n", bsp_apicid);
+       printk_debug("cpu_init_detectedx = %08x\n", cpu_init_detectedx);

 
        /* Setup sysinfo defaults */
        set_sysinfo_in_ram(0);
 
        /* Setup sysinfo defaults */
        set_sysinfo_in_ram(0);


@@ -300,12 +297,12 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        /* Setup nodes PCI space and start core 0 AP init. */
        finalize_node_setup(sysinfo);
 
        /* Setup nodes PCI space and start core 0 AP init. */
        finalize_node_setup(sysinfo);

-       printk_debug("finalize_node_setup done \n");
+       printk_debug("finalize_node_setup done\n");

 
        /* Setup any mainboard PCI settings etc. */
 
        /* Setup any mainboard PCI settings etc. */

-       printk_debug("setup_mb_resource_map begin \n");
+       printk_debug("setup_mb_resource_map begin\n");

        setup_mb_resource_map();
        setup_mb_resource_map();

-       printk_debug("setup_mb_resource_map end \n");
+       printk_debug("setup_mb_resource_map end\n");

        post_code(0x36);
 
        /* wait for all the APs core0 started by finalize_node_setup. */
        post_code(0x36);
 
        /* wait for all the APs core0 started by finalize_node_setup. */


@@ -329,7 +326,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 #if FAM10_SET_FIDVID == 1
        msr = rdmsr(0xc0010071);
 
 #if FAM10_SET_FIDVID == 1
        msr = rdmsr(0xc0010071);

-       printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+       printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);

 
        /* FIXME: The sb fid change may survive the warm reset and only
         * need to be done once.*/
 
        /* FIXME: The sb fid change may survive the warm reset and only
         * need to be done once.*/


@@ -347,7 +344,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        /* show final fid and vid */
        msr=rdmsr(0xc0010071);
 
        /* show final fid and vid */
        msr=rdmsr(0xc0010071);

-       printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+       printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);

 #endif
 
        wants_reset = mcp55_early_setup_x();
 #endif
 
        wants_reset = mcp55_early_setup_x();

diff --git a/src/mainboard/msi/ms9652_fam10/spd_addr.h b/src/mainboard/msi/ms9652_fam10/spd_addr.h
index 915ee8bd7ca1b95d00bbca7e0ad3c16ce52e25d7..a8abf331ee1f63d725406b9c10d64ac4cc07139e 100644 (file)
--- a/src/mainboard/msi/ms9652_fam10/spd_addr.h
+++ b/src/mainboard/msi/ms9652_fam10/spd_addr.h
@@ -19,7 +19,7 @@
 
 /**
  * This file defines the SPD addresses for the mainboard. Must be included in
 
 /**
  * This file defines the SPD addresses for the mainboard. Must be included in

- * cache_as_ram_auto.c
+ * romstage.c

  */
 
 #define RC00 0
  */
 
 #define RC00 0

diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig
index c71ffd8889f906b898a2a2a092d5509a4f4ed792..91f8f45457dcf2ad3d9f6a9eacade556b38fc6f1 100644 (file)
--- a/src/mainboard/tyan/s2912_fam10/Kconfig
+++ b/src/mainboard/tyan/s2912_fam10/Kconfig
@@ -27,7 +27,7 @@ config DCACHE_RAM_BASE
        hex
        default 0xc4000
        depends on BOARD_TYAN_S2912_FAM10
        hex
        default 0xc4000
        depends on BOARD_TYAN_S2912_FAM10

-       
+

 config DCACHE_RAM_SIZE
        hex
        default 0x0c000
 config DCACHE_RAM_SIZE
        hex
        default 0x0c000


@@ -39,7 +39,7 @@ config DCACHE_RAM_GLOBAL_VAR_SIZE
        depends on BOARD_TYAN_S2912_FAM10
 
 config APIC_ID_OFFSET
        depends on BOARD_TYAN_S2912_FAM10
 
 config APIC_ID_OFFSET

-       hex     
+       hex

        default 0
        depends on BOARD_TYAN_S2912_FAM10
 
        default 0
        depends on BOARD_TYAN_S2912_FAM10
 


@@ -65,7 +65,7 @@ config LB_CKS_RANGE_END
 
 config LB_CKS_LOC
        int
 
 config LB_CKS_LOC
        int

-        default 123
+       default 123

        depends on BOARD_TYAN_S2912_FAM10
 
 config MAINBOARD_PART_NUMBER
        depends on BOARD_TYAN_S2912_FAM10
 
 config MAINBOARD_PART_NUMBER


@@ -75,7 +75,7 @@ config MAINBOARD_PART_NUMBER
 
 config PCI_64BIT_PREF_MEM
        bool
 
 config PCI_64BIT_PREF_MEM
        bool

-        default n
+       default n

        depends on BOARD_TYAN_S2912_FAM10
 
 config HAVE_FALLBACK_BOOT
        depends on BOARD_TYAN_S2912_FAM10
 
 config HAVE_FALLBACK_BOOT


@@ -104,7 +104,7 @@ config MAX_PHYSICAL_CPUS
        depends on BOARD_TYAN_S2912_FAM10
 
 config HW_MEM_HOLE_SIZE_AUTO_INC
        depends on BOARD_TYAN_S2912_FAM10
 
 config HW_MEM_HOLE_SIZE_AUTO_INC

-       bool    
+       bool

        default n
        depends on BOARD_TYAN_S2912_FAM10
 
        default n
        depends on BOARD_TYAN_S2912_FAM10
 


@@ -114,7 +114,7 @@ config HT_CHAIN_UNITID_BASE
        depends on BOARD_TYAN_S2912_FAM10
 
 config HT_CHAIN_END_UNITID_BASE
        depends on BOARD_TYAN_S2912_FAM10
 
 config HT_CHAIN_END_UNITID_BASE

-       hex     
+       hex

        default 0x20
        depends on BOARD_TYAN_S2912_FAM10
 
        default 0x20
        depends on BOARD_TYAN_S2912_FAM10
 


@@ -124,12 +124,12 @@ config USE_INIT
        depends on BOARD_TYAN_S2912_FAM10
 
 config SERIAL_CPU_INIT
        depends on BOARD_TYAN_S2912_FAM10
 
 config SERIAL_CPU_INIT

-       bool    
+       bool

        default n
        depends on BOARD_TYAN_S2912_FAM10
 
 config WAIT_BEFORE_CPUS_INIT
        default n
        depends on BOARD_TYAN_S2912_FAM10
 
 config WAIT_BEFORE_CPUS_INIT

-       bool    
+       bool

        default n
        depends on BOARD_TYAN_S2912_FAM10
 
        default n
        depends on BOARD_TYAN_S2912_FAM10
 

diff --git a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c
index 79520bdcf31c829388a6ca073ab9cee678a1df46..7ee4944a9cb0d49f08f28b93adb05dc3778d5672 100644 (file)
--- a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c
+++ b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c
@@ -68,7 +68,6 @@ static unsigned get_bus_conf_done = 0;
 
 void get_bus_conf(void)
 {
 
 void get_bus_conf(void)
 {

-

        unsigned apicid_base;
        struct mb_sysconf_t *m;
 
        unsigned apicid_base;
        struct mb_sysconf_t *m;
 


@@ -134,5 +133,4 @@ void get_bus_conf(void)
        apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
 #endif
        m->apicid_mcp55 = apicid_base+0;
        apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
 #endif
        m->apicid_mcp55 = apicid_base+0;

-

 }
 }

diff --git a/src/mainboard/tyan/s2912_fam10/mptable.c b/src/mainboard/tyan/s2912_fam10/mptable.c
index 36767e96e62cc5017afdeae0aab9cf7a23560d27..b2fae1f4436a0a7ad150aa8229ceb90b9349a768 100644 (file)
--- a/src/mainboard/tyan/s2912_fam10/mptable.c
+++ b/src/mainboard/tyan/s2912_fam10/mptable.c
@@ -100,7 +100,7 @@ void *smp_write_config_table(void *v)
 
        }
 
 
        }
 

-                  /*I/O Ints:  Type    Polarity    Trigger                     Bus ID   IRQ    APIC ID PIN# */
+                       /*I/O Ints:     Type    Polarity    Trigger                     Bus ID   IRQ    APIC ID PIN# */

        smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x0);
        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x1, m->apicid_mcp55, 0x1);
        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x0, m->apicid_mcp55, 0x2);
        smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x0);
        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x1, m->apicid_mcp55, 0x1);
        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x0, m->apicid_mcp55, 0x2);

diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index 1216c298b998fdb6229ee4937f9cfefb3737fc7f..45d0d9401ae6448488f217d86894473af7869bf6 100644 (file)
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -150,10 +150,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 

-

 static void sio_setup(void)
 {
 static void sio_setup(void)
 {

-

        unsigned value;
        uint32_t dword;
        uint8_t byte;
        unsigned value;
        uint32_t dword;
        uint8_t byte;


@@ -278,10 +276,10 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #endif
 
        val = cpuid_eax(1);
 #endif
 
        val = cpuid_eax(1);

-       printk_debug("BSP Family_Model: %08x \n", val);
+       printk_debug("BSP Family_Model: %08x\n", val);

        printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
        printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");

-       printk_debug("bsp_apicid = %02x \n", bsp_apicid);
-       printk_debug("cpu_init_detectedx = %08x \n", cpu_init_detectedx);
+       printk_debug("bsp_apicid = %02x\n", bsp_apicid);
+       printk_debug("cpu_init_detectedx = %08x\n", cpu_init_detectedx);

 
        /* Setup sysinfo defaults */
        set_sysinfo_in_ram(0);
 
        /* Setup sysinfo defaults */
        set_sysinfo_in_ram(0);


@@ -322,7 +320,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 #if FAM10_SET_FIDVID == 1
        msr = rdmsr(0xc0010071);
 
 #if FAM10_SET_FIDVID == 1
        msr = rdmsr(0xc0010071);

-       printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+       printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);

 
        /* FIXME: The sb fid change may survive the warm reset and only
         * need to be done once.*/
 
        /* FIXME: The sb fid change may survive the warm reset and only
         * need to be done once.*/


@@ -340,7 +338,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        /* show final fid and vid */
        msr=rdmsr(0xc0010071);
 
        /* show final fid and vid */
        msr=rdmsr(0xc0010071);

-       printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+       printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);

 #endif
 
        wants_reset = mcp55_early_setup_x();
 #endif
 
        wants_reset = mcp55_early_setup_x();