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The enable_hpet() code in intel/i82801gx will not work with the
author
Uwe Hermann
<uwe@hermann-uwe.de>
Thu, 6 Nov 2008 22:23:05 +0000
(22:23 +0000)
committer
Uwe Hermann
<uwe@hermann-uwe.de>
Thu, 6 Nov 2008 22:23:05 +0000
(22:23 +0000)
ICH7 southbridge (but it might work with ICH4/ICH5 or so).
The ICH7 needs a different init code. Drop the non-working code for now.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3732
2b7e53f0
-3cfb-0310-b3e9-
8179ed1497e1
src/southbridge/intel/i82801gx/i82801gx_lpc.c
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diff --git
a/src/southbridge/intel/i82801gx/i82801gx_lpc.c
b/src/southbridge/intel/i82801gx/i82801gx_lpc.c
index 4d4c10e20136f21ba8016e335ce5f21bad20820f..13eb9e0ed12bd709e58caeef5b9e5c531ed37e6c 100644
(file)
--- a/
src/southbridge/intel/i82801gx/i82801gx_lpc.c
+++ b/
src/southbridge/intel/i82801gx/i82801gx_lpc.c
@@
-194,22
+194,7
@@
void i82801gx_rtc_init(struct device *dev)
static void enable_hpet(struct device *dev)
{
static void enable_hpet(struct device *dev)
{
- u32 reg32;
- u32 code = (0 & 0x3);
-
- reg32 = pci_read_config32(dev, GEN_CNTL);
- reg32 |= (1 << 17); /* Enable HPET. */
- /*
- * Bits [16:15] Memory Address Range
- * 00 FED0_0000h - FED0_03FFh
- * 01 FED0_1000h - FED0_13FFh
- * 10 FED0_2000h - FED0_23FFh
- * 11 FED0_3000h - FED0_33FFh
- */
- reg32 &= ~(3 << 15); /* Clear it */
- reg32 |= (code << 15);
- /* TODO: reg32 is never written to anywhere? */
- printk_debug("Enabling HPET @0x%x\n", HPET_ADDR | (code << 12));
+ /* TODO */
}
static void i82801gx_lock_smm(struct device *dev)
}
static void i82801gx_lock_smm(struct device *dev)