+
+#if MMCONF_SUPPORT
+uint8_t pci_mmio_read_config8(device_t dev, unsigned where)
+{
+ struct bus *pbus = get_pbus(dev);
+ return pci_ops_mmconf.read8(pbus, dev->bus->secondary, dev->path.pci.devfn, where);
+}
+
+uint16_t pci_mmio_read_config16(device_t dev, unsigned where)
+{
+ struct bus *pbus = get_pbus(dev);
+ return pci_ops_mmconf.read16(pbus, dev->bus->secondary, dev->path.pci.devfn, where);
+}
+
+uint32_t pci_mmio_read_config32(device_t dev, unsigned where)
+{
+ struct bus *pbus = get_pbus(dev);
+ return pci_ops_mmconf.read32(pbus, dev->bus->secondary, dev->path.pci.devfn, where);
+}
+
+void pci_mmio_write_config8(device_t dev, unsigned where, uint8_t val)
+{
+ struct bus *pbus = get_pbus(dev);
+ pci_ops_mmconf.write8(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val);
+}
+
+void pci_mmio_write_config16(device_t dev, unsigned where, uint16_t val)
+{
+ struct bus *pbus = get_pbus(dev);
+ pci_ops_mmconf.write16(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val);
+}
+
+void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t val)
+{
+ struct bus *pbus = get_pbus(dev);
+ pci_ops_mmconf.write32(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val);
+}
+#endif