likely break the build, since it is only a small part, but it needs to
go in at some point and doing it directory by directory makes things
easier.
Signed-off-by: Yinghai Lu <yinghai.lu at amd.com>
Signed-off-by: Ed Swierk <eswierk at arastra.com>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ward Vandewege <ward at gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2588
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
#undef __HAVE_LONG_LONG__
#undef __HAVE_LONG_LONG__
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+
#endif /* I386_STDINT_H */
#endif /* I386_STDINT_H */
-#if CONFIG_LOGICAL_CPUS == 1
static unsigned is_core0_started(unsigned nodeid)
{
static unsigned is_core0_started(unsigned nodeid)
{
#include <string.h>
#include <cpu/x86/msr.h>
#include <string.h>
#include <cpu/x86/msr.h>
-typedef unsigned int u32;
-
/* The maximum length of CPU names is 48 bytes, including the final NULL byte.
* If you change these names your BIOS will _NOT_ pass the AMD validation and
* your mainboard will not be posted on the AMD Recommended Motherboard Website
/* The maximum length of CPU names is 48 bytes, including the final NULL byte.
* If you change these names your BIOS will _NOT_ pass the AMD validation and
* your mainboard will not be posted on the AMD Recommended Motherboard Website
/* selgdt 0x08, flat code segment */
.word 0xffff, 0x0000
/* selgdt 0x08, flat code segment */
.word 0xffff, 0x0000
- .byte 0x00, 0x9b, 0xcf, 0x00
+ .byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */
/* selgdt 0x10,flat data segment */
.word 0xffff, 0x0000
/* selgdt 0x10,flat data segment */
.word 0xffff, 0x0000
- .byte 0x00, 0x93, 0xcf, 0x00
+ .byte 0x00, 0x93, 0xcf, 0x00
{
/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
{
/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
+ /* FIXME: It only support 4G less range */
msr_t basem, maskm;
basem.lo = base | type;
basem.hi = 0;
msr_t basem, maskm;
basem.lo = base | type;
basem.hi = 0;
+#ifndef CONFIG_VAR_MTRR_HOLE
+#define CONFIG_VAR_MTRR_HOLE 1
+#endif
+
struct var_mtrr_state {
unsigned long range_startk, range_sizek;
unsigned int reg;
struct var_mtrr_state {
unsigned long range_startk, range_sizek;
unsigned int reg;
+#if CONFIG_VAR_MTRR_HOLE
unsigned long hole_startk, hole_sizek;
unsigned long hole_startk, hole_sizek;
unsigned address_bits;
};
unsigned address_bits;
};
}
/* Write the range mtrrs */
if (state->range_sizek != 0) {
}
/* Write the range mtrrs */
if (state->range_sizek != 0) {
+#if CONFIG_VAR_MTRR_HOLE
if (state->hole_sizek == 0) {
/* We need to put that on to hole */
unsigned long endk = basek + sizek;
if (state->hole_sizek == 0) {
/* We need to put that on to hole */
unsigned long endk = basek + sizek;
state->range_sizek = endk - state->range_startk;
return;
}
state->range_sizek = endk - state->range_startk;
return;
}
state->reg = range_to_mtrr(state->reg, state->range_startk,
state->range_sizek, basek, MTRR_TYPE_WRBACK, state->address_bits);
state->reg = range_to_mtrr(state->reg, state->range_startk,
state->range_sizek, basek, MTRR_TYPE_WRBACK, state->address_bits);
+#if CONFIG_VAR_MTRR_HOLE
state->reg = range_to_mtrr(state->reg, state->hole_startk,
state->hole_sizek, basek, MTRR_TYPE_UNCACHEABLE, state->address_bits);
state->reg = range_to_mtrr(state->reg, state->hole_startk,
state->hole_sizek, basek, MTRR_TYPE_UNCACHEABLE, state->address_bits);
state->range_startk = 0;
state->range_sizek = 0;
state->range_startk = 0;
state->range_sizek = 0;
+#if CONFIG_VAR_MTRR_HOLE
state->hole_startk = 0;
state->hole_sizek = 0;
state->hole_startk = 0;
state->hole_sizek = 0;
- printk_spew(" Allocate an msr - basek = %d, sizek = %d,\n", basek, sizek);
+ printk_spew(" Allocate an msr - basek = %08x, sizek = %08x,\n", basek, sizek);
state->range_startk = basek;
state->range_sizek = sizek;
}
state->range_startk = basek;
state->range_sizek = sizek;
}
*/
var_state.range_startk = 0;
var_state.range_sizek = 0;
*/
var_state.range_startk = 0;
var_state.range_sizek = 0;
+#if CONFIG_VAR_MTRR_HOLE
var_state.hole_startk = 0;
var_state.hole_sizek = 0;
var_state.hole_startk = 0;
var_state.hole_sizek = 0;
var_state.reg = 0;
var_state.address_bits = address_bits;
search_global_resources(
var_state.reg = 0;
var_state.address_bits = address_bits;
search_global_resources(
/* Write the last range */
var_state.reg = range_to_mtrr(var_state.reg, var_state.range_startk,
var_state.range_sizek, 0, MTRR_TYPE_WRBACK, var_state.address_bits);
/* Write the last range */
var_state.reg = range_to_mtrr(var_state.reg, var_state.range_startk,
var_state.range_sizek, 0, MTRR_TYPE_WRBACK, var_state.address_bits);
+#if CONFIG_VAR_MTRR_HOLE
var_state.reg = range_to_mtrr(var_state.reg, var_state.hole_startk,
var_state.hole_sizek, 0, MTRR_TYPE_UNCACHEABLE, var_state.address_bits);
var_state.reg = range_to_mtrr(var_state.reg, var_state.hole_startk,
var_state.hole_sizek, 0, MTRR_TYPE_UNCACHEABLE, var_state.address_bits);
printk_debug("DONE variable MTRRs\n");
printk_debug("Clear out the extra MTRR's\n");
/* Clear out the extra MTRR's */
printk_debug("DONE variable MTRRs\n");
printk_debug("Clear out the extra MTRR's\n");
/* Clear out the extra MTRR's */