4KiB is not enough to work.
Additionally, modify the device tree so that the undocumented LDN 6
is ignored by the resource allocator, and while here, assign the
parallel port DRQ, hardware monitor IRQ and drop NIC MAC address
on SMBus EEPROM hint, the ms7135 doesn't have such hardware.
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5147
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
config DCACHE_RAM_BASE
hex
config DCACHE_RAM_BASE
hex
depends on BOARD_MSI_MS7135
config DCACHE_RAM_SIZE
hex
depends on BOARD_MSI_MS7135
config DCACHE_RAM_SIZE
hex
depends on BOARD_MSI_MS7135
depends on BOARD_MSI_MS7135
device pnp 4e.1 on # Parallel port
io 0x60 = 0x378
irq 0x70 = 7
device pnp 4e.1 on # Parallel port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 4e.2 on # Com1
io 0x60 = 0x3f8
end
device pnp 4e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 1
irq 0x72 = 12
end
irq 0x70 = 1
irq 0x72 = 12
end
+ device pnp 4e.6 off end # XXX keep allocator happy
device pnp 4e.7 off end # Game, MIDI, GPIO 1, GPIO 5
device pnp 4e.8 off end # GPIO 2
device pnp 4e.9 off end # GPIO 3, GPIO 4
device pnp 4e.a off end # ACPI
device pnp 4e.b on # Hardware monitor
io 0x60 = 0x290
device pnp 4e.7 off end # Game, MIDI, GPIO 1, GPIO 5
device pnp 4e.8 off end # GPIO 2
device pnp 4e.9 off end # GPIO 3, GPIO 4
device pnp 4e.a off end # ACPI
device pnp 4e.b on # Hardware monitor
io 0x60 = 0x290
register "ide1_enable" = "1"
register "sata0_enable" = "1"
register "sata1_enable" = "1"
register "ide1_enable" = "1"
register "sata0_enable" = "1"
register "sata1_enable" = "1"
- # register "mac_eeprom_smbus" = "3"
- # register "mac_eeprom_addr" = "0x51"
end
end
device pci 18.1 on end
end
end
device pci 18.1 on end