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(parent: e534daa) | patch
This patch adds support for the AMD LX cpu.
authorRon Minnich <Ron Minnich>
Fri, 28 Jul 2006 16:06:16 +0000 (16:06 +0000)
committerRonald G. Minnich <rminnich@gmail.com>
Fri, 28 Jul 2006 16:06:16 +0000 (16:06 +0000)
commit5e9dc231209c1a293b5a92a9ea78eb07ce0a3086
tree00c90e50087fba91bf5fb2cab050b3191b1daf46tree | snapshot
parente534daa05ae7057ad615e15fa3021b19f4850fd0commit | diff
This patch adds support for the AMD LX cpu.

There is one global change to pci_ids.h. The rest are changes for LX. I
ran abuild and it is ok.  Not all artec design changes are included as
some of them would adversely affect other mainboards. Indrek will need
to test.

Signed-off-by: Ron Minnich
Signed-off-by: Indrek Kruusa, indrek.kruusa@artecdesign.ee, artec
design.

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
29 files changed:
src/cpu/amd/model_lx/Config.lb [new file with mode: 0644] blob
src/cpu/amd/model_lx/cpubug.c [new file with mode: 0644] blob
src/cpu/amd/model_lx/cpureginit.c [new file with mode: 0644] blob
src/cpu/amd/model_lx/model_lx_init.c [new file with mode: 0644] blob
src/cpu/amd/model_lx/syspreinit.c [new file with mode: 0644] blob
src/cpu/amd/model_lx/vsmsetup.c [new file with mode: 0644] blob
src/include/cpu/amd/lxdef.h [new file with mode: 0644] blob
src/include/device/pci_ids.h diff | blob | history
src/mainboard/artecgroup/dbe61/Config.lb [new file with mode: 0644] blob
src/mainboard/artecgroup/dbe61/Options.lb [new file with mode: 0644] blob
src/mainboard/artecgroup/dbe61/auto.c [new file with mode: 0644] blob
src/mainboard/artecgroup/dbe61/chip.h [new file with mode: 0644] blob
src/mainboard/artecgroup/dbe61/cmos.layout [new file with mode: 0644] blob
src/mainboard/artecgroup/dbe61/debug.c [new file with mode: 0644] blob
src/mainboard/artecgroup/dbe61/failover.c [new file with mode: 0644] blob
src/mainboard/artecgroup/dbe61/irq_tables.c [new file with mode: 0644] blob
src/mainboard/artecgroup/dbe61/mainboard.c [new file with mode: 0644] blob
src/mainboard/artecgroup/dbe61/reset.c [new file with mode: 0644] blob
src/northbridge/amd/lx/Config.lb [new file with mode: 0644] blob
src/northbridge/amd/lx/chip.h [new file with mode: 0644] blob
src/northbridge/amd/lx/chipsetinit.c [new file with mode: 0644] blob
src/northbridge/amd/lx/grphinit.c [new file with mode: 0644] blob
src/northbridge/amd/lx/northbridge.c [new file with mode: 0644] blob
src/northbridge/amd/lx/northbridge.h [new file with mode: 0644] blob
src/northbridge/amd/lx/northbridgeinit.c [new file with mode: 0644] blob
src/northbridge/amd/lx/pll_reset.c [new file with mode: 0644] blob
src/northbridge/amd/lx/raminit.c [new file with mode: 0644] blob
src/northbridge/amd/lx/raminit.h [new file with mode: 0644] blob
targets/artecgroup/dbe61/Config.lb [new file with mode: 0644] blob
my coreboot WIP stuff (asus m5a99x-evo board)