projects / coreboot.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: c914053) | patch
AMD DDR2 and DDR3 MCT function InitPhyCompensation() compliant with AGESA code.
authorKerry She <Kerry.she@amd.com>
Sat, 4 Sep 2010 06:13:02 +0000 (06:13 +0000)
committerPatrick Georgi <patrick.georgi@coresystems.de>
Sat, 4 Sep 2010 06:13:02 +0000 (06:13 +0000)
commit08c92e03bf46e40559a25062fc77258c0eff2efb
tree29b6c6f31a97ad5368945bb192483b3994cc2a89tree | snapshot
parentc9140530261213bcd1c0a1eb8e44b4b06a3a5877commit | diff
AMD DDR2 and DDR3 MCT function InitPhyCompensation() compliant with AGESA code.

Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5776 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
src/northbridge/amd/amdmct/mct/mct_d.c diff | blob | history
src/northbridge/amd/amdmct/mct_ddr3/mct_d.c diff | blob | history
my coreboot WIP stuff (asus m5a99x-evo board)