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(parent: 4adc9eb) | patch
Now that the VIA code is run above 1Meg (like other boards), it should
authorKevin O'Connor <kevin@koconnor.net>
Wed, 19 Jan 2011 06:32:35 +0000 (06:32 +0000)
committerStefan Reinauer <stepan@openbios.org>
Wed, 19 Jan 2011 06:32:35 +0000 (06:32 +0000)
commit5bb9fd6e4dae32f86a07676228034d3828820037
tree9933b8327f3af0ce6814d5402ce798a3720d273etree | snapshot
parent4adc9eb60047e7dc3a7921793c489fff4fe3fc57commit | diff
Now that the VIA code is run above 1Meg (like other boards), it should
cache that range instead of the first 1Meg.  This reduces boot time by
about 1 second on epia-cn.

This patch also adds a MTRRphysMaskValid bit definition.

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
src/cpu/via/car/cache_as_ram.inc diff | blob | history
src/cpu/x86/mtrr/mtrr.c diff | blob | history
src/include/cpu/x86/mtrr.h diff | blob | history
my coreboot WIP stuff (asus m5a99x-evo board)