X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=vgasrc%2Fvgaio.c;h=bc4c9683756928067d7a2c872f392a4807e68cfc;hb=4040195d46ebdcc3503965a0f437a7d7f8b53aee;hp=6c1dbbd1ed5c92bd5a53e2b6bee42a6c73504f97;hpb=ca668640a91108ef3260c8402fc7ecb3cd5c6728;p=seabios.git

diff --git a/vgasrc/vgaio.c b/vgasrc/vgaio.c
index 6c1dbbd..bc4c968 100644
--- a/vgasrc/vgaio.c
+++ b/vgasrc/vgaio.c
@@ -8,7 +8,10 @@
 #include "ioport.h" // outb
 #include "farptr.h" // SET_FARVAR
 #include "biosvar.h" // GET_BDA
-#include "vgatables.h" // VGAREG_*
+#include "vgabios.h" // VGAREG_*
+
+// TODO
+//  * replace direct in/out calls with wrapper functions
 
 
 /****************************************************************
@@ -16,14 +19,14 @@
  ****************************************************************/
 
 void
-vgahw_screen_disable()
+vgahw_screen_disable(void)
 {
     inb(VGAREG_ACTL_RESET);
     outb(0x00, VGAREG_ACTL_ADDRESS);
 }
 
 void
-vgahw_screen_enable()
+vgahw_screen_enable(void)
 {
     inb(VGAREG_ACTL_RESET);
     outb(0x20, VGAREG_ACTL_ADDRESS);
@@ -62,7 +65,7 @@ vgahw_set_overscan_border_color(u8 color)
 }
 
 u8
-vgahw_get_overscan_border_color()
+vgahw_get_overscan_border_color(void)
 {
     inb(VGAREG_ACTL_RESET);
     outb(0x11, VGAREG_ACTL_ADDRESS);
@@ -237,7 +240,7 @@ vgahw_set_pel_mask(u8 val)
 }
 
 u8
-vgahw_get_pel_mask()
+vgahw_get_pel_mask(void)
 {
     return inb(VGAREG_PEL_MASK);
 }
@@ -266,6 +269,18 @@ vgahw_restore_dac_state(u16 seg, struct saveDACcolors *info)
  * Memory control
  ****************************************************************/
 
+void
+vgahw_sequ_write(u8 index, u8 value)
+{
+    outw((value<<8) | index, VGAREG_SEQU_ADDRESS);
+}
+
+void
+vgahw_grdc_write(u8 index, u8 value)
+{
+    outw((value<<8) | index, VGAREG_GRDC_ADDRESS);
+}
+
 void
 vgahw_set_text_block_specifier(u8 spec)
 {
@@ -273,7 +288,7 @@ vgahw_set_text_block_specifier(u8 spec)
 }
 
 void
-get_font_access()
+get_font_access(void)
 {
     outw(0x0100, VGAREG_SEQU_ADDRESS);
     outw(0x0402, VGAREG_SEQU_ADDRESS);
@@ -285,7 +300,7 @@ get_font_access()
 }
 
 void
-release_font_access()
+release_font_access(void)
 {
     outw(0x0100, VGAREG_SEQU_ADDRESS);
     outw(0x0302, VGAREG_SEQU_ADDRESS);
@@ -303,7 +318,7 @@ release_font_access()
  ****************************************************************/
 
 static u16
-get_crtc()
+get_crtc(void)
 {
     return GET_BDA(crtc_address);
 }
@@ -350,7 +365,7 @@ vgahw_set_scan_lines(u8 lines)
 
 // Get vertical display end
 u16
-vgahw_get_vde()
+vgahw_get_vde(void)
 {
     u16 crtc_addr = get_crtc();
     outb(0x12, crtc_addr);
@@ -363,31 +378,13 @@ vgahw_get_vde()
 
 
 /****************************************************************
- * Misc
+ * Save/Restore/Set state
  ****************************************************************/
 
-void
-vgahw_enable_video_addressing(u8 disable)
-{
-    u8 v = (disable & 1) ? 0x00 : 0x02;
-    u8 v2 = inb(VGAREG_READ_MISC_OUTPUT) & ~0x02;
-    outb(v | v2, VGAREG_WRITE_MISC_OUTPUT);
-}
-
-void
-vgahw_init()
-{
-    // switch to color mode and enable CPU access 480 lines
-    outb(0xc3, VGAREG_WRITE_MISC_OUTPUT);
-    // more than 64k 3C4/04
-    outb(0x04, VGAREG_SEQU_ADDRESS);
-    outb(0x02, VGAREG_SEQU_DATA);
-}
-
 void
 vgahw_save_state(u16 seg, struct saveVideoHardware *info)
 {
-    u16 crtc_addr = GET_BDA(crtc_address);
+    u16 crtc_addr = get_crtc();
     SET_FARVAR(seg, info->sequ_index, inb(VGAREG_SEQU_ADDRESS));
     SET_FARVAR(seg, info->crtc_index, inb(crtc_addr));
     SET_FARVAR(seg, info->grdc_index, inb(VGAREG_GRDC_ADDRESS));
@@ -482,3 +479,81 @@ vgahw_restore_state(u16 seg, struct saveVideoHardware *info)
     outb(GET_FARVAR(seg, info->grdc_index), VGAREG_GRDC_ADDRESS);
     outb(GET_FARVAR(seg, info->feature), crtc_addr - 0x4 + 0xa);
 }
+
+void
+vgahw_set_mode(struct vgamode_s *vmode_g)
+{
+    // Reset Attribute Ctl flip-flop
+    inb(VGAREG_ACTL_RESET);
+
+    // Set Attribute Ctl
+    u8 *regs = GET_GLOBAL(vmode_g->actl_regs);
+    u16 i;
+    for (i = 0; i <= 0x13; i++) {
+        outb(i, VGAREG_ACTL_ADDRESS);
+        outb(GET_GLOBAL(regs[i]), VGAREG_ACTL_WRITE_DATA);
+    }
+    outb(0x14, VGAREG_ACTL_ADDRESS);
+    outb(0x00, VGAREG_ACTL_WRITE_DATA);
+
+    // Set Sequencer Ctl
+    outb(0, VGAREG_SEQU_ADDRESS);
+    outb(0x03, VGAREG_SEQU_DATA);
+    regs = GET_GLOBAL(vmode_g->sequ_regs);
+    for (i = 1; i <= 4; i++) {
+        outb(i, VGAREG_SEQU_ADDRESS);
+        outb(GET_GLOBAL(regs[i - 1]), VGAREG_SEQU_DATA);
+    }
+
+    // Set Grafx Ctl
+    regs = GET_GLOBAL(vmode_g->grdc_regs);
+    for (i = 0; i <= 8; i++) {
+        outb(i, VGAREG_GRDC_ADDRESS);
+        outb(GET_GLOBAL(regs[i]), VGAREG_GRDC_DATA);
+    }
+
+    // Set CRTC address VGA or MDA
+    u8 miscreg = GET_GLOBAL(vmode_g->miscreg);
+    u16 crtc_addr = VGAREG_VGA_CRTC_ADDRESS;
+    if (!(miscreg & 1))
+        crtc_addr = VGAREG_MDA_CRTC_ADDRESS;
+
+    // Disable CRTC write protection
+    outw(0x0011, crtc_addr);
+    // Set CRTC regs
+    regs = GET_GLOBAL(vmode_g->crtc_regs);
+    for (i = 0; i <= 0x18; i++) {
+        outb(i, crtc_addr);
+        outb(GET_GLOBAL(regs[i]), crtc_addr + 1);
+    }
+
+    // Set the misc register
+    outb(miscreg, VGAREG_WRITE_MISC_OUTPUT);
+
+    // Enable video
+    outb(0x20, VGAREG_ACTL_ADDRESS);
+    inb(VGAREG_ACTL_RESET);
+}
+
+
+/****************************************************************
+ * Misc
+ ****************************************************************/
+
+void
+vgahw_enable_video_addressing(u8 disable)
+{
+    u8 v = (disable & 1) ? 0x00 : 0x02;
+    u8 v2 = inb(VGAREG_READ_MISC_OUTPUT) & ~0x02;
+    outb(v | v2, VGAREG_WRITE_MISC_OUTPUT);
+}
+
+void
+vgahw_init(void)
+{
+    // switch to color mode and enable CPU access 480 lines
+    outb(0xc3, VGAREG_WRITE_MISC_OUTPUT);
+    // more than 64k 3C4/04
+    outb(0x04, VGAREG_SEQU_ADDRESS);
+    outb(0x02, VGAREG_SEQU_DATA);
+}