X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=vgasrc%2Fstdvga.c;h=0345a813f03d38cb1f2ef9866461be0f5c981c2d;hb=3471fdbe63f9e982ae979094b6b3e7562dae1021;hp=f40c172b6dc9ca20d831fb2a041930300206f123;hpb=c990f27298104d23a0a63fc340385310e598fe00;p=seabios.git diff --git a/vgasrc/stdvga.c b/vgasrc/stdvga.c index f40c172..0345a81 100644 --- a/vgasrc/stdvga.c +++ b/vgasrc/stdvga.c @@ -1,4 +1,4 @@ -// VGA io port access +// Standard VGA driver code // // Copyright (C) 2009 Kevin O'Connor // Copyright (C) 2001-2008 the LGPL VGABios developers Team @@ -10,6 +10,7 @@ #include "farptr.h" // SET_FARVAR #include "biosvar.h" // GET_GLOBAL #include "util.h" // memcpy_far +#include "vbe.h" // VBE_RETURN_STATUS_FAILED // TODO // * replace direct in/out calls with wrapper functions @@ -19,14 +20,14 @@ * Attribute control ****************************************************************/ -void +static void stdvga_screen_disable(void) { inb(VGAREG_ACTL_RESET); outb(0x00, VGAREG_ACTL_ADDRESS); } -void +static void stdvga_screen_enable(void) { inb(VGAREG_ACTL_RESET); @@ -93,26 +94,6 @@ stdvga_set_palette(u8 palid) outb(0x20, VGAREG_ACTL_ADDRESS); } -void -stdvga_set_single_palette_reg(u8 reg, u8 val) -{ - inb(VGAREG_ACTL_RESET); - outb(reg, VGAREG_ACTL_ADDRESS); - outb(val, VGAREG_ACTL_WRITE_DATA); - outb(0x20, VGAREG_ACTL_ADDRESS); -} - -u8 -stdvga_get_single_palette_reg(u8 reg) -{ - inb(VGAREG_ACTL_RESET); - outb(reg, VGAREG_ACTL_ADDRESS); - u8 v = inb(VGAREG_ACTL_READ_DATA); - inb(VGAREG_ACTL_RESET); - outb(0x20, VGAREG_ACTL_ADDRESS); - return v; -} - void stdvga_set_all_palette_reg(u16 seg, u8 *data_far) { @@ -204,48 +185,6 @@ stdvga_read_video_dac_state(u8 *pmode, u8 *curpage) * DAC control ****************************************************************/ -void -stdvga_set_dac_regs(u16 seg, u8 *data_far, u8 start, int count) -{ - outb(start, VGAREG_DAC_WRITE_ADDRESS); - while (count) { - outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA); - data_far++; - outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA); - data_far++; - outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA); - data_far++; - count--; - } -} - -void -stdvga_get_dac_regs(u16 seg, u8 *data_far, u8 start, int count) -{ - outb(start, VGAREG_DAC_READ_ADDRESS); - while (count) { - SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA)); - data_far++; - SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA)); - data_far++; - SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA)); - data_far++; - count--; - } -} - -void -stdvga_set_pel_mask(u8 val) -{ - outb(val, VGAREG_PEL_MASK); -} - -u8 -stdvga_get_pel_mask(void) -{ - return inb(VGAREG_PEL_MASK); -} - void stdvga_save_dac_state(u16 seg, struct saveDACcolors *info) { @@ -253,7 +192,7 @@ stdvga_save_dac_state(u16 seg, struct saveDACcolors *info) SET_FARVAR(seg, info->rwmode, inb(VGAREG_DAC_STATE)); SET_FARVAR(seg, info->peladdr, inb(VGAREG_DAC_WRITE_ADDRESS)); SET_FARVAR(seg, info->pelmask, inb(VGAREG_PEL_MASK)); - stdvga_get_dac_regs(seg, info->dac, 0, 256); + stdvga_dac_read(seg, info->dac, 0, 256); SET_FARVAR(seg, info->color_select, 0); } @@ -261,27 +200,34 @@ void stdvga_restore_dac_state(u16 seg, struct saveDACcolors *info) { outb(GET_FARVAR(seg, info->pelmask), VGAREG_PEL_MASK); - stdvga_set_dac_regs(seg, info->dac, 0, 256); + stdvga_dac_write(seg, info->dac, 0, 256); outb(GET_FARVAR(seg, info->peladdr), VGAREG_DAC_WRITE_ADDRESS); } - -/**************************************************************** - * Memory control - ****************************************************************/ - void -stdvga_sequ_write(u8 index, u8 value) +stdvga_perform_gray_scale_summing(u16 start, u16 count) { - outw((value<<8) | index, VGAREG_SEQU_ADDRESS); -} + stdvga_screen_disable(); + int i; + for (i = start; i < start+count; i++) { + u8 rgb[3]; + stdvga_dac_read(GET_SEG(SS), rgb, i, 1); -void -stdvga_grdc_write(u8 index, u8 value) -{ - outw((value<<8) | index, VGAREG_GRDC_ADDRESS); + // intensity = ( 0.3 * Red ) + ( 0.59 * Green ) + ( 0.11 * Blue ) + u16 intensity = ((77 * rgb[0] + 151 * rgb[1] + 28 * rgb[2]) + 0x80) >> 8; + if (intensity > 0x3f) + intensity = 0x3f; + + stdvga_dac_write(GET_SEG(SS), rgb, i, 1); + } + stdvga_screen_enable(); } + +/**************************************************************** + * Memory control + ****************************************************************/ + void stdvga_set_text_block_specifier(u8 spec) { @@ -340,7 +286,7 @@ stdvga_load_font(u16 seg, void *src_far, u16 count u16 stdvga_get_crtc(void) { - if (inb(VGAREG_READ_MISC_OUTPUT) & 1) + if (stdvga_misc_read() & 1) return VGAREG_VGA_CRTC_ADDRESS; return VGAREG_MDA_CRTC_ADDRESS; } @@ -502,14 +448,59 @@ stdvga_restore_state(u16 seg, struct saveVideoHardware *info) outb(GET_FARVAR(seg, info->feature), crtc_addr - 0x4 + 0xa); } -void -stdvga_set_mode(struct vgamode_s *vmode_g) +static void +clear_screen(struct vgamode_s *vmode_g) +{ + switch (GET_GLOBAL(vmode_g->memmodel)) { + case MM_TEXT: + memset16_far(GET_GLOBAL(vmode_g->sstart), 0, 0x0720, 32*1024); + break; + case MM_CGA: + memset16_far(GET_GLOBAL(vmode_g->sstart), 0, 0x0000, 32*1024); + break; + default: + // XXX - old code gets/sets/restores sequ register 2 to 0xf - + // but it should always be 0xf anyway. + memset16_far(GET_GLOBAL(vmode_g->sstart), 0, 0x0000, 64*1024); + } +} + +int +stdvga_set_mode(int mode, int flags) { + // find the entry in the video modes + struct vgamode_s *vmode_g = stdvga_find_mode(mode); + dprintf(1, "mode search %02x found %p\n", mode, vmode_g); + if (!vmode_g) + return VBE_RETURN_STATUS_FAILED; + struct stdvga_mode_s *stdmode_g = container_of( + vmode_g, struct stdvga_mode_s, info); + + // if palette loading (bit 3 of modeset ctl = 0) + if (!(flags & MF_NOPALETTE)) { // Set the PEL mask + stdvga_pelmask_write(GET_GLOBAL(stdmode_g->pelmask)); + + // From which palette + u8 *palette_g = GET_GLOBAL(stdmode_g->dac); + u16 palsize = GET_GLOBAL(stdmode_g->dacsize) / 3; + + // Always 256*3 values + stdvga_dac_write(get_global_seg(), palette_g, 0, palsize); + u16 i; + for (i = palsize; i < 0x0100; i++) { + static u8 rgb[3] VAR16; + stdvga_dac_write(get_global_seg(), rgb, i, 1); + } + + if (flags & MF_GRAYSUM) + stdvga_perform_gray_scale_summing(0x00, 0x100); + } + // Reset Attribute Ctl flip-flop inb(VGAREG_ACTL_RESET); // Set Attribute Ctl - u8 *regs = GET_GLOBAL(vmode_g->actl_regs); + u8 *regs = GET_GLOBAL(stdmode_g->actl_regs); u16 i; for (i = 0; i <= 0x13; i++) { outb(i, VGAREG_ACTL_ADDRESS); @@ -521,21 +512,21 @@ stdvga_set_mode(struct vgamode_s *vmode_g) // Set Sequencer Ctl outb(0, VGAREG_SEQU_ADDRESS); outb(0x03, VGAREG_SEQU_DATA); - regs = GET_GLOBAL(vmode_g->sequ_regs); + regs = GET_GLOBAL(stdmode_g->sequ_regs); for (i = 1; i <= 4; i++) { outb(i, VGAREG_SEQU_ADDRESS); outb(GET_GLOBAL(regs[i - 1]), VGAREG_SEQU_DATA); } // Set Grafx Ctl - regs = GET_GLOBAL(vmode_g->grdc_regs); + regs = GET_GLOBAL(stdmode_g->grdc_regs); for (i = 0; i <= 8; i++) { outb(i, VGAREG_GRDC_ADDRESS); outb(GET_GLOBAL(regs[i]), VGAREG_GRDC_DATA); } // Set CRTC address VGA or MDA - u8 miscreg = GET_GLOBAL(vmode_g->miscreg); + u8 miscreg = GET_GLOBAL(stdmode_g->miscreg); u16 crtc_addr = VGAREG_VGA_CRTC_ADDRESS; if (!(miscreg & 1)) crtc_addr = VGAREG_MDA_CRTC_ADDRESS; @@ -543,7 +534,7 @@ stdvga_set_mode(struct vgamode_s *vmode_g) // Disable CRTC write protection outw(0x0011, crtc_addr); // Set CRTC regs - regs = GET_GLOBAL(vmode_g->crtc_regs); + regs = GET_GLOBAL(stdmode_g->crtc_regs); for (i = 0; i <= 0x18; i++) { outb(i, crtc_addr); outb(GET_GLOBAL(regs[i]), crtc_addr + 1); @@ -555,6 +546,20 @@ stdvga_set_mode(struct vgamode_s *vmode_g) // Enable video outb(0x20, VGAREG_ACTL_ADDRESS); inb(VGAREG_ACTL_RESET); + + // Clear screen + if (!(flags & MF_NOCLEARMEM)) + clear_screen(vmode_g); + + // Write the fonts in memory + u8 memmodel = GET_GLOBAL(vmode_g->memmodel); + if (memmodel == MM_TEXT) + stdvga_load_font(get_global_seg(), vgafont16, 0x100, 0, 0, 16); + + // Setup BDA variables + modeswitch_set_bda(mode, flags, vmode_g); + + return 0; } @@ -562,6 +567,12 @@ stdvga_set_mode(struct vgamode_s *vmode_g) * Misc ****************************************************************/ +void +stdvga_list_modes(u16 seg, u16 *dest, u16 *last) +{ + SET_FARVAR(seg, *dest, 0xffff); +} + void stdvga_enable_video_addressing(u8 disable) { @@ -570,7 +581,7 @@ stdvga_enable_video_addressing(u8 disable) outb(v | v2, VGAREG_WRITE_MISC_OUTPUT); } -void +int stdvga_init(void) { // switch to color mode and enable CPU access 480 lines @@ -578,4 +589,6 @@ stdvga_init(void) // more than 64k 3C4/04 outb(0x04, VGAREG_SEQU_ADDRESS); outb(0x02, VGAREG_SEQU_DATA); + + return 0; }