X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=vgasrc%2Fclext.c;h=ec0380f908bde4211e82fa3185ff1f0f20b5bac3;hb=2c8ba89aab21dcd400a923887843696dc00a9645;hp=b2c59fb7b3f50d6a32ffd994a6849cfd5146cbe9;hpb=8f4c019d75fb8f16dbd704b76f802dee3c9a066f;p=seabios.git

diff --git a/vgasrc/clext.c b/vgasrc/clext.c
index b2c59fb..ec0380f 100644
--- a/vgasrc/clext.c
+++ b/vgasrc/clext.c
@@ -5,11 +5,13 @@
 //
 // This file may be distributed under the terms of the GNU LGPLv3 license.
 
-#include "vgatables.h" // cirrus_init
+#include "clext.h" // clext_init
+#include "vgabios.h" // VBE_VENDOR_STRING
 #include "biosvar.h" // GET_GLOBAL
 #include "util.h" // dprintf
 #include "bregs.h" // struct bregs
 #include "vbe.h" // struct vbe_info
+#include "stdvga.h" // VGAREG_SEQU_ADDRESS
 
 
 /****************************************************************
@@ -19,6 +21,7 @@
 struct cirrus_mode_s {
     /* + 0 */
     u16 mode;
+    u8 memmodel;
     u16 width;
     u16 height;
     u16 depth;
@@ -29,7 +32,6 @@ struct cirrus_mode_s {
     u16 *crtc; /* 0x3d4 */
     /* +16 */
     u8 bitsperpixel;
-    u8 vesacolortype;
     u8 vesaredmask;
     u8 vesaredpos;
     u8 vesagreenmask;
@@ -238,64 +240,65 @@ static u16 ccrtc_1600x1200x8[] VAR16 = {
 };
 
 static struct cirrus_mode_s cirrus_modes[] VAR16 = {
-    {0x5f,640,480,8,0x00,
+    {0x5f,MM_PACKED,640,480,8,0x00,
      cseq_640x480x8,cgraph_svgacolor,ccrtc_640x480x8,8,
-     4,0,0,0,0,0,0,0,0},
-    {0x64,640,480,16,0xe1,
+     0,0,0,0,0,0,0,0},
+    {0x64,MM_DIRECT,640,480,16,0xe1,
      cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16,16,
-     6,5,11,6,5,5,0,0,0},
-    {0x66,640,480,15,0xf0,
+     5,11,6,5,5,0,0,0},
+    {0x66,MM_DIRECT,640,480,15,0xf0,
      cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16,16,
-     6,5,10,5,5,5,0,1,15},
-    {0x71,640,480,24,0xe5,
+     5,10,5,5,5,0,1,15},
+    {0x71,MM_DIRECT,640,480,24,0xe5,
      cseq_640x480x24,cgraph_svgacolor,ccrtc_640x480x24,24,
-     6,8,16,8,8,8,0,0,0},
+     8,16,8,8,8,0,0,0},
 
-    {0x5c,800,600,8,0x00,
+    {0x5c,MM_PACKED,800,600,8,0x00,
      cseq_800x600x8,cgraph_svgacolor,ccrtc_800x600x8,8,
-     4,0,0,0,0,0,0,0,0},
-    {0x65,800,600,16,0xe1,
+     0,0,0,0,0,0,0,0},
+    {0x65,MM_DIRECT,800,600,16,0xe1,
      cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16,16,
-     6,5,11,6,5,5,0,0,0},
-    {0x67,800,600,15,0xf0,
+     5,11,6,5,5,0,0,0},
+    {0x67,MM_DIRECT,800,600,15,0xf0,
      cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16,16,
-     6,5,10,5,5,5,0,1,15},
+     5,10,5,5,5,0,1,15},
 
-    {0x60,1024,768,8,0x00,
+    {0x60,MM_PACKED,1024,768,8,0x00,
      cseq_1024x768x8,cgraph_svgacolor,ccrtc_1024x768x8,8,
-     4,0,0,0,0,0,0,0,0},
-    {0x74,1024,768,16,0xe1,
+     0,0,0,0,0,0,0,0},
+    {0x74,MM_DIRECT,1024,768,16,0xe1,
      cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16,16,
-     6,5,11,6,5,5,0,0,0},
-    {0x68,1024,768,15,0xf0,
+     5,11,6,5,5,0,0,0},
+    {0x68,MM_DIRECT,1024,768,15,0xf0,
      cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16,16,
-     6,5,10,5,5,5,0,1,15},
+     5,10,5,5,5,0,1,15},
 
-    {0x78,800,600,24,0xe5,
+    {0x78,MM_DIRECT,800,600,24,0xe5,
      cseq_800x600x24,cgraph_svgacolor,ccrtc_800x600x24,24,
-     6,8,16,8,8,8,0,0,0},
-    {0x79,1024,768,24,0xe5,
+     8,16,8,8,8,0,0,0},
+    {0x79,MM_DIRECT,1024,768,24,0xe5,
      cseq_1024x768x24,cgraph_svgacolor,ccrtc_1024x768x24,24,
-     6,8,16,8,8,8,0,0,0},
+     8,16,8,8,8,0,0,0},
 
-    {0x6d,1280,1024,8,0x00,
+    {0x6d,MM_PACKED,1280,1024,8,0x00,
      cseq_1280x1024x8,cgraph_svgacolor,ccrtc_1280x1024x8,8,
-     4,0,0,0,0,0,0,0,0},
-    {0x69,1280,1024,15,0xf0,
+     0,0,0,0,0,0,0,0},
+    {0x69,MM_DIRECT,1280,1024,15,0xf0,
      cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16,16,
-     6,5,10,5,5,5,0,1,15},
-    {0x75,1280,1024,16,0xe1,
+     5,10,5,5,5,0,1,15},
+    {0x75,MM_DIRECT,1280,1024,16,0xe1,
      cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16,16,
-     6,5,11,6,5,5,0,0,0},
+     5,11,6,5,5,0,0,0},
 
-    {0x7b,1600,1200,8,0x00,
+    {0x7b,MM_PACKED,1600,1200,8,0x00,
      cseq_1600x1200x8,cgraph_svgacolor,ccrtc_1600x1200x8,8,
-     4,0,0,0,0,0,0,0,0},
-
-    {0xfe,0,0,0,0,cseq_vga,cgraph_vga,ccrtc_vga,0,
-     0xff,0,0,0,0,0,0,0,0},
+     0,0,0,0,0,0,0,0},
 };
 
+static struct cirrus_mode_s mode_switchback VAR16 =
+    {0xfe,0xff,0,0,0,0,cseq_vga,cgraph_vga,ccrtc_vga,0,
+     0,0,0,0,0,0,0,0};
+
 
 /****************************************************************
  * helper functions
@@ -326,14 +329,6 @@ cirrus_switch_mode_setregs(u16 *data, u16 port)
     }
 }
 
-static u16
-cirrus_get_crtc(void)
-{
-    if (inb(VGAREG_READ_MISC_OUTPUT) & 1)
-        return VGAREG_VGA_CRTC_ADDRESS;
-    return VGAREG_MDA_CRTC_ADDRESS;
-}
-
 static void
 cirrus_switch_mode(struct cirrus_mode_s *table)
 {
@@ -341,7 +336,7 @@ cirrus_switch_mode(struct cirrus_mode_s *table)
     outw(0x1206, VGAREG_SEQU_ADDRESS);
     cirrus_switch_mode_setregs(GET_GLOBAL(table->seq), VGAREG_SEQU_ADDRESS);
     cirrus_switch_mode_setregs(GET_GLOBAL(table->graph), VGAREG_GRDC_ADDRESS);
-    cirrus_switch_mode_setregs(GET_GLOBAL(table->crtc), cirrus_get_crtc());
+    cirrus_switch_mode_setregs(GET_GLOBAL(table->crtc), stdvga_get_crtc());
 
     outb(0x00, VGAREG_PEL_MASK);
     inb(VGAREG_PEL_MASK);
@@ -351,13 +346,13 @@ cirrus_switch_mode(struct cirrus_mode_s *table)
     outb(GET_GLOBAL(table->hidden_dac), VGAREG_PEL_MASK);
     outb(0xff, VGAREG_PEL_MASK);
 
-    u8 vesacolortype = GET_GLOBAL(table->vesacolortype);
-    u8 v = vgahw_get_single_palette_reg(0x10) & 0xfe;
-    if (vesacolortype == 3)
+    u8 memmodel = GET_GLOBAL(table->memmodel);
+    u8 v = stdvga_get_single_palette_reg(0x10) & 0xfe;
+    if (memmodel == MM_PLANAR)
         v |= 0x41;
-    else if (vesacolortype)
+    else if (memmodel != MM_TEXT)
         v |= 0x01;
-    vgahw_set_single_palette_reg(0x10, v);
+    stdvga_set_single_palette_reg(0x10, v);
 }
 
 static u8
@@ -399,22 +394,21 @@ cirrus_clear_vram(u16 param)
 }
 
 int
-cirrus_set_video_mode(u8 mode, u8 noclearmem)
+clext_set_mode(int mode, int flags)
 {
     dprintf(1, "cirrus mode %d\n", mode);
     SET_BDA(vbe_mode, 0);
     struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode);
     if (table_g) {
         cirrus_switch_mode(table_g);
-        if (!noclearmem)
+        if (!(flags & MF_NOCLEARMEM))
             cirrus_clear_vram(0xffff);
         SET_BDA(video_mode, mode);
-        return 1;
+        return 0;
     }
-    table_g = cirrus_get_modeentry(0xfe);
-    cirrus_switch_mode(table_g);
+    cirrus_switch_mode(&mode_switchback);
     dprintf(1, "cirrus mode switch regular\n");
-    return 0;
+    return stdvga_set_mode(mode, flags);
 }
 
 static int
@@ -432,7 +426,7 @@ cirrus_check(void)
 static void
 cirrus_extbios_80h(struct bregs *regs)
 {
-    u16 crtc_addr = cirrus_get_crtc();
+    u16 crtc_addr = stdvga_get_crtc();
     outb(0x27, crtc_addr);
     u8 v = inb(crtc_addr + 1);
     if (v == 0xa0)
@@ -457,7 +451,7 @@ cirrus_extbios_81h(struct bregs *regs)
 static void
 cirrus_extbios_82h(struct bregs *regs)
 {
-    u16 crtc_addr = cirrus_get_crtc();
+    u16 crtc_addr = stdvga_get_crtc();
     outb(0x27, crtc_addr);
     regs->al = inb(crtc_addr + 1) & 0x03;
     regs->ah = 0xAF;
@@ -595,7 +589,7 @@ cirrus_get_bpp_bytes(void)
 static void
 cirrus_set_line_offset(u16 new_line_offset)
 {
-    u16 crtc_addr = cirrus_get_crtc();
+    u16 crtc_addr = stdvga_get_crtc();
     outb(0x13, crtc_addr);
     outb(new_line_offset / 8, crtc_addr + 1);
 
@@ -607,7 +601,7 @@ cirrus_set_line_offset(u16 new_line_offset)
 static u16
 cirrus_get_line_offset(void)
 {
-    u16 crtc_addr = cirrus_get_crtc();
+    u16 crtc_addr = stdvga_get_crtc();
     outb(0x13, crtc_addr);
     u8 reg13 = inb(crtc_addr + 1);
     outb(0x1b, crtc_addr);
@@ -647,7 +641,7 @@ cirrus_get_line_offset_entry(struct cirrus_mode_s *table_g)
 static void
 cirrus_set_start_addr(u32 addr)
 {
-    u16 crtc_addr = cirrus_get_crtc();
+    u16 crtc_addr = stdvga_get_crtc();
     outb(0x0d, crtc_addr);
     outb(addr, crtc_addr + 1);
 
@@ -667,7 +661,7 @@ cirrus_set_start_addr(u32 addr)
 static u32
 cirrus_get_start_addr(void)
 {
-    u16 crtc_addr = cirrus_get_crtc();
+    u16 crtc_addr = stdvga_get_crtc();
     outb(0x0c, crtc_addr);
     u8 b2 = inb(crtc_addr + 1);
 
@@ -758,7 +752,7 @@ cirrus_vesa_01h(struct bregs *regs)
     SET_FARVAR(seg, info->planes, 1);
     SET_FARVAR(seg, info->bits_per_pixel, GET_GLOBAL(table_g->depth));
     SET_FARVAR(seg, info->banks, 1);
-    SET_FARVAR(seg, info->mem_model, GET_GLOBAL(table_g->vesacolortype));
+    SET_FARVAR(seg, info->mem_model, GET_GLOBAL(table_g->memmodel));
     SET_FARVAR(seg, info->bank_size, 0);
 
     int pages = (cirrus_get_memsize() * 64 * 1024) / (height * linesize);
@@ -938,12 +932,16 @@ cirrus_vesa(struct bregs *regs)
  * init
  ****************************************************************/
 
-void
-cirrus_init(void)
+int
+clext_init(void)
 {
+    int ret = stdvga_init();
+    if (ret)
+        return ret;
+
     dprintf(1, "cirrus init\n");
     if (! cirrus_check())
-        return;
+        return -1;
     dprintf(1, "cirrus init 2\n");
 
     // memory setup
@@ -955,4 +953,6 @@ cirrus_init(void)
     // reset bitblt
     outw(0x0431, VGAREG_GRDC_ADDRESS);
     outw(0x0031, VGAREG_GRDC_ADDRESS);
+
+    return 0;
 }