X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=vgasrc%2Fclext.c;h=413add53586fffe3d2b321423923e9a6f22a2bfc;hb=97cc354a0223ad4241e657f69dc13ffed2694ee8;hp=835d80962a40315d57157407eb41e1f50eaeb693;hpb=e19a68f5acf441eb0c00cbd38f74e46ad4a288f3;p=seabios.git

diff --git a/vgasrc/clext.c b/vgasrc/clext.c
index 835d809..413add5 100644
--- a/vgasrc/clext.c
+++ b/vgasrc/clext.c
@@ -12,6 +12,8 @@
 #include "bregs.h" // struct bregs
 #include "vbe.h" // struct vbe_info
 #include "stdvga.h" // VGAREG_SEQU_ADDRESS
+#include "pci.h" // pci_config_readl
+#include "pci_regs.h" // PCI_BASE_ADDRESS_0
 
 
 /****************************************************************
@@ -421,7 +423,7 @@ cirrus_clear_vram(u16 param)
 int
 clext_set_mode(int mode, int flags)
 {
-    dprintf(1, "cirrus mode %d\n", mode);
+    dprintf(1, "cirrus mode %x\n", mode);
     SET_BDA(vbe_mode, 0);
     struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode);
     if (table_g) {
@@ -452,7 +454,7 @@ cirrus_check(void)
  ****************************************************************/
 
 static void
-cirrus_extbios_80h(struct bregs *regs)
+clext_101280(struct bregs *regs)
 {
     u16 crtc_addr = stdvga_get_crtc();
     outb(0x27, crtc_addr);
@@ -470,14 +472,14 @@ cirrus_extbios_80h(struct bregs *regs)
 }
 
 static void
-cirrus_extbios_81h(struct bregs *regs)
+clext_101281(struct bregs *regs)
 {
     // XXX
     regs->ax = 0x0100;
 }
 
 static void
-cirrus_extbios_82h(struct bregs *regs)
+clext_101282(struct bregs *regs)
 {
     u16 crtc_addr = stdvga_get_crtc();
     outb(0x27, crtc_addr);
@@ -486,13 +488,13 @@ cirrus_extbios_82h(struct bregs *regs)
 }
 
 static void
-cirrus_extbios_85h(struct bregs *regs)
+clext_101285(struct bregs *regs)
 {
     regs->al = cirrus_get_memsize();
 }
 
 static void
-cirrus_extbios_9Ah(struct bregs *regs)
+clext_10129a(struct bregs *regs)
 {
     regs->ax = 0x4060;
     regs->cx = 0x1132;
@@ -507,7 +509,7 @@ ASM16(
     "retf");
 
 static void
-cirrus_extbios_A0h(struct bregs *regs)
+clext_1012a0(struct bregs *regs)
 {
     struct cirrus_mode_s *table_g = cirrus_get_modeentry(regs->al & 0x7f);
     regs->ah = (table_g ? 1 : 0);
@@ -516,38 +518,43 @@ cirrus_extbios_A0h(struct bregs *regs)
 }
 
 static void
-cirrus_extbios_A1h(struct bregs *regs)
+clext_1012a1(struct bregs *regs)
 {
     regs->bx = 0x0e00; // IBM 8512/8513, color
 }
 
 static void
-cirrus_extbios_A2h(struct bregs *regs)
+clext_1012a2(struct bregs *regs)
 {
     regs->al = 0x07; // HSync 31.5 - 64.0 kHz
 }
 
 static void
-cirrus_extbios_AEh(struct bregs *regs)
+clext_1012ae(struct bregs *regs)
 {
     regs->al = 0x01; // High Refresh 75Hz
 }
 
+static void
+clext_1012XX(struct bregs *regs)
+{
+    debug_stub(regs);
+}
+
 void
-cirrus_extbios(struct bregs *regs)
+clext_1012(struct bregs *regs)
 {
-    // XXX - regs->bl < 0x80 or > 0xaf call regular handlers.
     switch (regs->bl) {
-    case 0x80: cirrus_extbios_80h(regs); break;
-    case 0x81: cirrus_extbios_81h(regs); break;
-    case 0x82: cirrus_extbios_82h(regs); break;
-    case 0x85: cirrus_extbios_85h(regs); break;
-    case 0x9a: cirrus_extbios_9Ah(regs); break;
-    case 0xa0: cirrus_extbios_A0h(regs); break;
-    case 0xa1: cirrus_extbios_A1h(regs); break;
-    case 0xa2: cirrus_extbios_A2h(regs); break;
-    case 0xae: cirrus_extbios_AEh(regs); break;
-    default: break;
+    case 0x80: clext_101280(regs); break;
+    case 0x81: clext_101281(regs); break;
+    case 0x82: clext_101282(regs); break;
+    case 0x85: clext_101285(regs); break;
+    case 0x9a: clext_10129a(regs); break;
+    case 0xa0: clext_1012a0(regs); break;
+    case 0xa1: clext_1012a1(regs); break;
+    case 0xa2: clext_1012a2(regs); break;
+    case 0xae: clext_1012ae(regs); break;
+    default:   clext_1012XX(regs); break;
     }
 }
 
@@ -766,6 +773,12 @@ clext_init(void)
         return -1;
     dprintf(1, "cirrus init 2\n");
 
+    SET_VGA(VBE_enabled, 1);
+    u32 lfb_addr = 0;
+    if (CONFIG_VGA_PCI)
+        lfb_addr = (pci_config_readl(GET_GLOBAL(VgaBDF), PCI_BASE_ADDRESS_0)
+                    & PCI_BASE_ADDRESS_MEM_MASK);
+    SET_VGA(VBE_framebuffer, lfb_addr);
     u16 totalmem = cirrus_get_memsize();
     SET_VGA(VBE_total_memory, totalmem * 64 * 1024);
     SET_VGA(VBE_win_granularity, 16);