X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=util%2Fsuperiotool%2Fsuperiotool.h;h=5583ec56697540a6d8f00c86f9bbbee40800f380;hb=3d1d6bb4ecb15a12f48f871c623882bee9c0c576;hp=479dba0d7a202cb750d569820bc08b19ac3668db;hpb=760498f8ea96096314900861d492f2125121a112;p=coreboot.git

diff --git a/util/superiotool/superiotool.h b/util/superiotool/superiotool.h
index 479dba0d7..5583ec566 100644
--- a/util/superiotool/superiotool.h
+++ b/util/superiotool/superiotool.h
@@ -33,8 +33,8 @@
 #include <sys/io.h>
 #endif
 #if (defined(__MACH__) && defined(__APPLE__))
-/* DirectIO is available here: http://www.coresystems.de/en/directio */
-#include <DirectIO/darwinio.h>
+/* DirectHW is available here: http://www.coreboot.org/DirectHW */
+#include <DirectHW/DirectHW.h>
 #endif
 
 #ifdef PCI_SUPPORT
@@ -182,11 +182,23 @@ void print_vendor_chips(const char *vendor,
 void probe_idregs_ali(uint16_t port);
 void print_ali_chips(void);
 
+/* amd.c */
+void probe_idregs_amd(uint16_t port);
+void print_amd_chips(void);
+
+/* serverengines.c */
+void probe_idregs_serverengines(uint16_t port);
+void print_serverengines_chips(void);
+
 /* fintek.c */
 void probe_idregs_fintek(uint16_t port);
 void probe_idregs_fintek_alternative(uint16_t port);
 void print_fintek_chips(void);
 
+/* infineon.c */
+void probe_idregs_infineon(uint16_t port);
+void print_infineon_chips(void);
+
 /* ite.c */
 void probe_idregs_ite(uint16_t port);
 void print_ite_chips(void);
@@ -223,15 +235,19 @@ static const struct {
 	{probe_idregs_fintek_alternative,	{0x2e, 0x4e, EOT}},
 	/* Only use 0x370 for ITE, but 0x3f0 or 0x3bd would also be valid. */
 	{probe_idregs_ite,	{0x25e, 0x2e, 0x4e, 0x370, EOT}},
-	{probe_idregs_nsc,	{0x2e, 0x4e, 0x15c, EOT}},
+	{probe_idregs_nsc,	{0x2e, 0x4e, 0x15c, 0x164e, EOT}},
 	/* I/O pairs on Nuvoton EC chips can be configured by firmware in
 	 * addition to the following hardware strapping options. */
-	{probe_idregs_nuvoton, {0x164e, 0x2e, EOT}},
+	{probe_idregs_nuvoton, {0x164e, 0x2e, 0x4e, EOT}},
 	{probe_idregs_smsc,	{0x2e, 0x4e, 0x162e, 0x164e, 0x3f0, 0x370, EOT}},
 	{probe_idregs_winbond,	{0x2e, 0x4e, 0x3f0, 0x370, 0x250, EOT}},
 #ifdef PCI_SUPPORT
 	{probe_idregs_via,	{0x3f0, EOT}},
+	/* in fact read the BASE from HW */
+	{probe_idregs_amd,	{0xaa, EOT}},
 #endif
+	{probe_idregs_serverengines,	{0x2e, EOT}},
+	{probe_idregs_infineon,	{0x2e, 0x4e}},
 };
 
 /** Table of functions to print out supported Super I/O chips. */
@@ -247,7 +263,10 @@ static const struct {
 	{print_winbond_chips},
 #ifdef PCI_SUPPORT
 	{print_via_chips},
+	{print_amd_chips},
 #endif
+	{print_serverengines_chips},
+	{print_infineon_chips},
 };
 
 #endif