X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=util%2Finteltool%2Finteltool.c;h=93169d398c85bad2db7e8e03c08f8d1c47603fae;hb=bb41f502444b2d0295809cc882b829d768962990;hp=e2520930fb5e3c1af074f5da1e8ef055ca60c5cd;hpb=eb02f45e6ff2a6870353816712ff6271250dc7ee;p=coreboot.git diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index e2520930f..93169d398 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -1,9 +1,10 @@ /* * inteltool - dump all registers on an Intel CPU + chipset based system. * - * Copyright (C) 2008 by coresystems GmbH - * written by Stefan Reinauer - * + * Copyright (C) 2008-2010 by coresystems GmbH + * written by Stefan Reinauer + * Copyright (C) 2009 Carl-Daniel Hailfinger + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -18,766 +19,94 @@ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ -#include -#include -#include #include -#include #include -#include #include +#include #include -#include -#include - -#define INTELTOOL_VERSION "1.0" - -/* Tested chipsets: */ -#define PCI_VENDOR_ID_INTEL 0x8086 -#define PCI_DEVICE_ID_INTEL_ICH 0x2410 -#define PCI_DEVICE_ID_INTEL_ICH0 0x2420 -#define PCI_DEVICE_ID_INTEL_ICH2 0x2440 -#define PCI_DEVICE_ID_INTEL_ICH4 0x24c0 -#define PCI_DEVICE_ID_INTEL_ICH4M 0x24cc -#define PCI_DEVICE_ID_INTEL_ICH7DH 0x27b0 -#define PCI_DEVICE_ID_INTEL_ICH7 0x27b8 -#define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9 -#define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd - -#define PCI_DEVICE_ID_INTEL_82845 0x1a30 -#define PCI_DEVICE_ID_INTEL_82945GM 0x27a0 +#include "inteltool.h" +#if defined(__FreeBSD__) +#include +#endif static const struct { uint16_t vendor_id, device_id; char *name; } supported_chips_list[] = { + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX, "82443LX" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX, "82443BX" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_NO_AGP, "82443BX without AGP" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810, "i810" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810DC, "i810-DC100" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_MC, "i810E DC-133" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82830M, "i830M" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865, "i865" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915, "82915G/P/GV/GL/PL/910GL" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "i945P" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GSE, "i945GSE" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PM965, "PM965" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q965, "Q963/965" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "i975X" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q35, "Q35" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G33, "P35/G33/G31/P31" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q33, "Q33" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58, "X58" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GS45, "GS45ME" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_DXXX, "Atom D400/500 Series" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_NXXX, "Atom N400 Series" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO, "SCH Poulsbo" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC, "SCH Poulsbo" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10R, "ICH10R" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DH, "ICH9DH" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DO, "ICH9DO" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9R, "ICH9R" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9, "ICH9" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9M, "ICH9M" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9ME, "ICH9M-E" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8M, "ICH8-M" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8, "ICH8" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10, "NM10" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7MDH, "ICH7-M DH" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7M, "ICH7-M" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7, "ICH7" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7DH, "ICH7DH" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6, "ICH6" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH5, "ICH5" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4M, "ICH4-M" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4, "ICH4" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH2, "ICH2" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH0, "ICH0" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" } -}; - -#define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0]))) - -int fd_mem; -int fd_msr; - -typedef struct { uint32_t hi, lo; } msr_t; -typedef struct { uint16_t addr; int size; char *name; } io_register_t; - -static const io_register_t ich0_gpio_registers[] = { - { 0x00, 4, "GPIO_USE_SEL" }, - { 0x04, 4, "GP_IO_SEL" }, - { 0x08, 4, "RESERVED" }, - { 0x0c, 4, "GP_LVL" }, - { 0x10, 4, "RESERVED" }, - { 0x14, 4, "GPO_TTL" }, - { 0x18, 4, "GPO_BLINK" }, - { 0x1c, 4, "RESERVED" }, - { 0x20, 4, "RESERVED" }, - { 0x24, 4, "RESERVED" }, - { 0x28, 4, "RESERVED" }, - { 0x2c, 4, "GPI_INV" }, - { 0x30, 4, "RESERVED" }, - { 0x34, 4, "RESERVED" }, - { 0x38, 4, "RESERVED" }, - { 0x3C, 4, "RESERVED" } -}; - -static const io_register_t ich4_gpio_registers[] = { - { 0x00, 4, "GPIO_USE_SEL" }, - { 0x04, 4, "GP_IO_SEL" }, - { 0x08, 4, "RESERVED" }, - { 0x0c, 4, "GP_LVL" }, - { 0x10, 4, "RESERVED" }, - { 0x14, 4, "GPO_TTL" }, - { 0x18, 4, "GPO_BLINK" }, - { 0x1c, 4, "RESERVED" }, - { 0x20, 4, "RESERVED" }, - { 0x24, 4, "RESERVED" }, - { 0x28, 4, "RESERVED" }, - { 0x2c, 4, "GPI_INV" }, - { 0x30, 4, "GPIO_USE_SEL2" }, - { 0x34, 4, "GP_IO_SEL2" }, - { 0x38, 4, "GP_LVL2" }, - { 0x3C, 4, "RESERVED" } + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "82371AB/EB/MB" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X44, "82X38/X48" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_32X0, "3200/3210" }, }; -static const io_register_t ich7_gpio_registers[] = { - { 0x00, 4, "GPIO_USE_SEL" }, - { 0x04, 4, "GP_IO_SEL" }, - { 0x08, 4, "RESERVED" }, - { 0x0c, 4, "GP_LVL" }, - { 0x10, 4, "RESERVED" }, - { 0x14, 4, "RESERVED" }, - { 0x18, 4, "GPO_BLINK" }, - { 0x1c, 4, "RESERVED" }, - { 0x20, 4, "RESERVED" }, - { 0x24, 4, "RESERVED" }, - { 0x28, 4, "RESERVED" }, - { 0x2c, 4, "GPI_INV" }, - { 0x30, 4, "GPIO_USE_SEL2" }, - { 0x34, 4, "GP_IO_SEL2" }, - { 0x38, 4, "GP_LVL2" }, - { 0x3C, 4, "RESERVED" } -}; +#ifndef __DARWIN__ +static int fd_mem; -int print_gpios(struct pci_dev *sb) +void *map_physical(uint64_t phys_addr, size_t len) { - int i, size; - uint16_t gpiobase; - const io_register_t *gpio_registers; - - printf("\n============= GPIOS =============\n\n"); - - switch (sb->device_id) { - case PCI_DEVICE_ID_INTEL_ICH7: - case PCI_DEVICE_ID_INTEL_ICH7M: - case PCI_DEVICE_ID_INTEL_ICH7DH: - case PCI_DEVICE_ID_INTEL_ICH7MDH: - gpiobase = pci_read_word(sb, 0x48) & 0xfffc; - gpio_registers = ich7_gpio_registers; - size = ARRAY_SIZE(ich7_gpio_registers); - break; - case PCI_DEVICE_ID_INTEL_ICH4: - case PCI_DEVICE_ID_INTEL_ICH4M: - gpiobase = pci_read_word(sb, 0x58) & 0xfffc; - gpio_registers = ich4_gpio_registers; - size = ARRAY_SIZE(ich4_gpio_registers); - break; - case PCI_DEVICE_ID_INTEL_ICH: - case PCI_DEVICE_ID_INTEL_ICH0: - gpiobase = pci_read_word(sb, 0x58) & 0xfffc; - gpio_registers = ich0_gpio_registers; - size = ARRAY_SIZE(ich0_gpio_registers); - break; - case 0x1234: // Dummy for non-existent functionality - printf("This southbridge does not have GPIOBASE.\n"); - return 1; - default: - printf("Error: Dumping GPIOs on this southbridge is not (yet) supported.\n"); - return 1; - } + void *virt_addr; - printf("GPIOBASE = 0x%04x (IO)\n\n", gpiobase); + virt_addr = mmap(0, len, PROT_WRITE | PROT_READ, MAP_SHARED, + fd_mem, (off_t) phys_addr); - for (i = 0; i < size; i++) { - switch (gpio_registers[i].size) { - case 4: - printf("gpiobase+0x%04x: 0x%08x (%s)\n", - gpio_registers[i].addr, - inl(gpiobase+gpio_registers[i].addr), - gpio_registers[i].name); - break; - case 2: - printf("gpiobase+0x%04x: 0x%04x (%s)\n", - gpio_registers[i].addr, - inw(gpiobase+gpio_registers[i].addr), - gpio_registers[i].name); - break; - case 1: - printf("gpiobase+0x%04x: 0x%02x (%s)\n", - gpio_registers[i].addr, - inb(gpiobase+gpio_registers[i].addr), - gpio_registers[i].name); - break; - } + if (virt_addr == MAP_FAILED) { + printf("Error mapping physical memory 0x%08lx[0x%x]\n", phys_addr, len); + return NULL; } - return 0; + return virt_addr; } -int print_rcba(struct pci_dev *sb) +void unmap_physical(void *virt_addr, size_t len) { - int i, size = 0x4000; - volatile uint8_t *rcba; - uint32_t rcba_phys; - - printf("\n============= RCBA ==============\n\n"); - - switch (sb->device_id) { - case PCI_DEVICE_ID_INTEL_ICH7: - case PCI_DEVICE_ID_INTEL_ICH7M: - case PCI_DEVICE_ID_INTEL_ICH7DH: - case PCI_DEVICE_ID_INTEL_ICH7MDH: - rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe; - break; - case PCI_DEVICE_ID_INTEL_ICH: - case PCI_DEVICE_ID_INTEL_ICH0: - case PCI_DEVICE_ID_INTEL_ICH4: - case PCI_DEVICE_ID_INTEL_ICH4M: - printf("This southbridge does not have RCBA.\n"); - return 1; - default: - printf("Error: Dumping RCBA on this southbridge is not (yet) supported.\n"); - return 1; - } - - rcba = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED, - fd_mem, (off_t) rcba_phys); - - if (rcba == MAP_FAILED) { - perror("Error mapping RCBA"); - exit(1); - } - - printf("RCBA = 0x%08x (MEM)\n\n", rcba_phys); - - for (i = 0; i < size; i += 4) { - if (*(uint32_t *)(rcba + i)) - printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(rcba + i)); - } - - munmap((void *)rcba, size); - return 0; + munmap(virt_addr, len); } - -int print_pmbase(struct pci_dev *sb) -{ - int i, size = 0x80; - uint16_t pmbase; - - printf("\n============= PMBASE ============\n\n"); - - switch (sb->device_id) { - case PCI_DEVICE_ID_INTEL_ICH7: - case PCI_DEVICE_ID_INTEL_ICH7M: - case PCI_DEVICE_ID_INTEL_ICH7DH: - case PCI_DEVICE_ID_INTEL_ICH7MDH: - pmbase = pci_read_word(sb, 0x40) & 0xfffc; - break; - case 0x1234: // Dummy for non-existent functionality - printf("This southbridge does not have PMBASE.\n"); - return 1; - default: - printf("Error: Dumping PMBASE on this southbridge is not (yet) supported.\n"); - return 1; - } - - printf("PMBASE = 0x%04x (IO)\n\n", pmbase); - - for (i = 0; i < size; i += 4) { - printf("pmbase+0x%04x: 0x%08x\n", i, inl(pmbase + i)); - } - - return 0; -} - -/* - * (G)MCH MMIO Config Space - */ -int print_mchbar(struct pci_dev *nb) -{ - int i, size = (16 * 1024); - volatile uint8_t *mchbar; - uint32_t mchbar_phys; - - printf("\n============= MCHBAR ============\n\n"); - - switch (nb->device_id) { - case PCI_DEVICE_ID_INTEL_82945GM: - mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe; - break; - case 0x1234: // Dummy for non-existent functionality - printf("This northbrigde does not have MCHBAR.\n"); - return 1; - default: - printf("Error: Dumping MCHBAR on this northbridge is not (yet) supported.\n"); - return 1; - } - - mchbar = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED, - fd_mem, (off_t) mchbar_phys); - - if (mchbar == MAP_FAILED) { - perror("Error mapping MCHBAR"); - exit(1); - } - - printf("MCHBAR = 0x%08x (MEM)\n\n", mchbar_phys); - - for (i = 0; i < size; i += 4) { - if (*(uint32_t *)(mchbar + i)) - printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(mchbar+i)); - } - - munmap((void *)mchbar, size); - return 0; -} - -/* - * Egress Port Root Complex MMIO configuration space - */ -int print_epbar(struct pci_dev *nb) -{ - int i, size = (4 * 1024); - volatile uint8_t *epbar; - uint32_t epbar_phys; - - printf("\n============= EPBAR =============\n\n"); - - switch (nb->device_id) { - case PCI_DEVICE_ID_INTEL_82945GM: - epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; - break; - case 0x1234: // Dummy for non-existent functionality - printf("This northbrigde does not have EPBAR.\n"); - return 1; - default: - printf("Error: Dumping EPBAR on this northbridge is not (yet) supported.\n"); - return 1; - } - - epbar = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED, - fd_mem, (off_t) epbar_phys); - - if (epbar == MAP_FAILED) { - perror("Error mapping EPBAR"); - exit(1); - } - - printf("EPBAR = 0x%08x (MEM)\n\n", epbar_phys); - for (i = 0; i < size; i += 4) { - if (*(uint32_t *)(epbar + i)) - printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(epbar+i)); - } - - munmap((void *)epbar, size); - return 0; -} - -/* - * MCH-ICH Serial Interconnect Ingress Root Complex MMIO configuration space - */ -int print_dmibar(struct pci_dev *nb) -{ - int i, size = (4 * 1024); - volatile uint8_t *dmibar; - uint32_t dmibar_phys; - - printf("\n============= DMIBAR ============\n\n"); - - switch (nb->device_id) { - case PCI_DEVICE_ID_INTEL_82945GM: - dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe; - break; - case 0x1234: // Dummy for non-existent functionality - printf("This northbrigde does not have DMIBAR.\n"); - return 1; - default: - printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n"); - return 1; - } - - dmibar = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED, - fd_mem, (off_t) dmibar_phys); - - if (dmibar == MAP_FAILED) { - perror("Error mapping DMIBAR"); - exit(1); - } - - printf("DMIBAR = 0x%08x (MEM)\n\n", dmibar_phys); - for (i = 0; i < size; i += 4) { - if (*(uint32_t *)(dmibar + i)) - printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(dmibar+i)); - } - - munmap((void *)dmibar, size); - return 0; -} - -/* - * PCIe MMIO configuration space - */ -int print_pciexbar(struct pci_dev *nb) -{ - uint32_t pciexbar_reg; - uint32_t pciexbar_phys; - volatile uint8_t *pciexbar; - int max_busses, devbase, i; - int bus, dev, fn; - - printf("========= PCIEXBAR ========\n\n"); - - switch (nb->device_id) { - case PCI_DEVICE_ID_INTEL_82945GM: - pciexbar_reg = pci_read_long(nb, 0x48); - break; - case 0x1234: // Dummy for non-existent functionality - printf("Error: This northbrigde does not have PCIEXBAR.\n"); - return 1; - default: - printf("Error: Dumping PCIEXBAR on this northbridge is not (yet) supported.\n"); - return 1; - } - - if (!(pciexbar_reg & (1 << 0))) { - printf("PCIEXBAR register is disabled.\n"); - return 0; - } - - switch ((pciexbar_reg >> 1) & 3) { - case 0: // 256MB - pciexbar_phys = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); - max_busses = 256; - break; - case 1: // 128M - pciexbar_phys = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); - max_busses = 128; - break; - case 2: // 64M - pciexbar_phys = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); - max_busses = 64; - break; - default: // RSVD - printf("Undefined address base. Bailing out.\n"); - return 1; - } - - printf("PCIEXBAR: 0x%08x\n", pciexbar_phys); - - pciexbar = mmap(0, (max_busses * 1024 * 1024), PROT_WRITE | PROT_READ, - MAP_SHARED, fd_mem, (off_t) pciexbar_phys); - - if (pciexbar == MAP_FAILED) { - perror("Error mapping PCIEXBAR"); - exit(1); - } - - for (bus = 0; bus < max_busses; bus++) { - for (dev = 0; dev < 32; dev++) { - for (fn = 0; fn < 8; fn++) { - devbase = (bus * 1024 * 1024) + (dev * 32 * 1024) + (fn * 4 * 1024); - - if (*(uint16_t *)(pciexbar + devbase) == 0xffff) - continue; - - /* This is a heuristics. Anyone got a better check? */ - if( (*(uint32_t *)(pciexbar + devbase + 256) == 0xffffffff) && - (*(uint32_t *)(pciexbar + devbase + 512) == 0xffffffff) ) { -#if DEBUG - printf("Skipped non-PCIe device %02x:%02x.%01x\n", bus, dev, fn); #endif - continue; - } - - printf("\nPCIe %02x:%02x.%01x extended config space:", bus, dev, fn); - for (i = 0; i < 4096; i++) { - if((i % 0x10) == 0) - printf("\n%04x:", i); - printf(" %02x", *(pciexbar+devbase+i)); - } - printf("\n"); - } - } - } - - munmap((void *)pciexbar, (max_busses * 1024 * 1024)); - - return 0; -} - -static unsigned int cpuid(unsigned int op) -{ - unsigned int ret; - unsigned int dummy2, dummy3, dummy4; - asm volatile ( - "cpuid" - : "=a" (ret), "=b" (dummy2), "=c" (dummy3), "=d" (dummy4) - : "a" (op) - ); - return ret; -} - -int msr_readerror = 0; - -msr_t rdmsr(int addr) -{ - uint8_t buf[8]; - msr_t msr = { 0xffffffff, 0xffffffff }; - - if (lseek(fd_msr, (off_t) addr, SEEK_SET) == -1) { - perror("Could not lseek() to MSR"); - close(fd_msr); - exit(1); - } - - if (read(fd_msr, buf, 8) == 8) { - msr.lo = *(uint32_t *)buf; - msr.hi = *(uint32_t *)(buf + 4); - - return msr; - } - - if (errno == 5) { - printf(" (*)"); // Not all bits of the MSR could be read - msr_readerror = 1; - } else { - // A severe error. - perror("Could not read() MSR"); - close(fd_msr); - exit(1); - } - - return msr; -} - -int print_intel_core_msrs(void) -{ - unsigned int i, core, id; - msr_t msr; - -#define IA32_PLATFORM_ID 0x0017 -#define EBL_CR_POWERON 0x002a -#define FSB_CLK_STS 0x00cd -#define IA32_TIME_STAMP_COUNTER 0x0010 -#define IA32_APIC_BASE 0x001b - - typedef struct { - int number; - char *name; - } msr_entry_t; - - static const msr_entry_t model6ex_global_msrs[] = { - { 0x0017, "IA32_PLATFORM_ID" }, - { 0x002a, "EBL_CR_POWERON" }, - { 0x00cd, "FSB_CLOCK_STS" }, - { 0x00ce, "FSB_CLOCK_VCC" }, - { 0x00e2, "CLOCK_CST_CONFIG_CONTROL" }, - { 0x00e3, "PMG_IO_BASE_ADDR" }, - { 0x00e4, "PMG_IO_CAPTURE_ADDR" }, - { 0x00ee, "EXT_CONFIG" }, - { 0x011e, "BBL_CR_CTL3" }, - { 0x0194, "CLOCK_FLEX_MAX" }, - { 0x0198, "IA32_PERF_STATUS" }, - { 0x01a0, "IA32_MISC_ENABLES" }, - { 0x01aa, "PIC_SENS_CFG" }, - { 0x0400, "IA32_MC0_CTL" }, - { 0x0401, "IA32_MC0_STATUS" }, - { 0x0402, "IA32_MC0_ADDR" }, - //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO - { 0x040c, "IA32_MC4_CTL" }, - { 0x040d, "IA32_MC4_STATUS" }, - { 0x040e, "IA32_MC4_ADDR" }, - //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO - }; - - static const msr_entry_t model6ex_per_core_msrs[] = { - { 0x0010, "IA32_TIME_STAMP_COUNTER" }, - { 0x001b, "IA32_APIC_BASE" }, - { 0x003a, "IA32_FEATURE_CONTROL" }, - { 0x003f, "IA32_TEMPERATURE_OFFSET" }, - //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO - { 0x008b, "IA32_BIOS_SIGN_ID" }, - { 0x00e7, "IA32_MPERF" }, - { 0x00e8, "IA32_APERF" }, - { 0x00fe, "IA32_MTRRCAP" }, - { 0x015f, "DTS_CAL_CTRL" }, - { 0x0179, "IA32_MCG_CAP" }, - { 0x017a, "IA32_MCG_STATUS" }, - { 0x0199, "IA32_PERF_CONTROL" }, - { 0x019a, "IA32_CLOCK_MODULATION" }, - { 0x019b, "IA32_THERM_INTERRUPT" }, - { 0x019c, "IA32_THERM_STATUS" }, - { 0x019d, "GV_THERM" }, - { 0x01d9, "IA32_DEBUGCTL" }, - { 0x0200, "IA32_MTRR_PHYSBASE0" }, - { 0x0201, "IA32_MTRR_PHYSMASK0" }, - { 0x0202, "IA32_MTRR_PHYSBASE1" }, - { 0x0203, "IA32_MTRR_PHYSMASK1" }, - { 0x0204, "IA32_MTRR_PHYSBASE2" }, - { 0x0205, "IA32_MTRR_PHYSMASK2" }, - { 0x0206, "IA32_MTRR_PHYSBASE3" }, - { 0x0207, "IA32_MTRR_PHYSMASK3" }, - { 0x0208, "IA32_MTRR_PHYSBASE4" }, - { 0x0209, "IA32_MTRR_PHYSMASK4" }, - { 0x020a, "IA32_MTRR_PHYSBASE5" }, - { 0x020b, "IA32_MTRR_PHYSMASK5" }, - { 0x020c, "IA32_MTRR_PHYSBASE6" }, - { 0x020d, "IA32_MTRR_PHYSMASK6" }, - { 0x020e, "IA32_MTRR_PHYSBASE7" }, - { 0x020f, "IA32_MTRR_PHYSMASK7" }, - { 0x0250, "IA32_MTRR_FIX64K_00000" }, - { 0x0258, "IA32_MTRR_FIX16K_80000" }, - { 0x0259, "IA32_MTRR_FIX16K_A0000" }, - { 0x0268, "IA32_MTRR_FIX4K_C0000" }, - { 0x0269, "IA32_MTRR_FIX4K_C8000" }, - { 0x026a, "IA32_MTRR_FIX4K_D0000" }, - { 0x026b, "IA32_MTRR_FIX4K_D8000" }, - { 0x026c, "IA32_MTRR_FIX4K_E0000" }, - { 0x026d, "IA32_MTRR_FIX4K_E8000" }, - { 0x026e, "IA32_MTRR_FIX4K_F0000" }, - { 0x026f, "IA32_MTRR_FIX4K_F8000" }, - { 0x02ff, "IA32_MTRR_DEF_TYPE" }, - //{ 0x00c000080, "IA32_CR_EFER" }, // Seems to be RO - }; - - static const msr_entry_t model6fx_global_msrs[] = { - { 0x0017, "IA32_PLATFORM_ID" }, - { 0x002a, "EBL_CR_POWERON" }, - { 0x003f, "IA32_TEMPERATURE_OFFSET" }, - { 0x00a8, "EMTTM_CR_TABLE0" }, - { 0x00a9, "EMTTM_CR_TABLE1" }, - { 0x00aa, "EMTTM_CR_TABLE2" }, - { 0x00ab, "EMTTM_CR_TABLE3" }, - { 0x00ac, "EMTTM_CR_TABLE4" }, - { 0x00ad, "EMTTM_CR_TABLE5" }, - { 0x00cd, "FSB_CLOCK_STS" }, - { 0x00e2, "PMG_CST_CONFIG_CONTROL" }, - { 0x00e3, "PMG_IO_BASE_ADDR" }, - { 0x00e4, "PMG_IO_CAPTURE_ADDR" }, - { 0x00ee, "EXT_CONFIG" }, - { 0x011e, "BBL_CR_CTL3" }, - { 0x0194, "CLOCK_FLEX_MAX" }, - { 0x0198, "IA32_PERF_STATUS" }, - { 0x01a0, "IA32_MISC_ENABLES" }, - { 0x01aa, "PIC_SENS_CFG" }, - { 0x0400, "IA32_MC0_CTL" }, - { 0x0401, "IA32_MC0_STATUS" }, - { 0x0402, "IA32_MC0_ADDR" }, - //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO - { 0x040c, "IA32_MC4_CTL" }, - { 0x040d, "IA32_MC4_STATUS" }, - { 0x040e, "IA32_MC4_ADDR" }, - //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO - }; - - static const msr_entry_t model6fx_per_core_msrs[] = { - { 0x0010, "IA32_TIME_STAMP_COUNTER" }, - { 0x001b, "IA32_APIC_BASE" }, - { 0x003a, "IA32_FEATURE_CONTROL" }, - //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO - { 0x008b, "IA32_BIOS_SIGN_ID" }, - { 0x00e1, "SMM_CST_MISC_INFO" }, - { 0x00e7, "IA32_MPERF" }, - { 0x00e8, "IA32_APERF" }, - { 0x00fe, "IA32_MTRRCAP" }, - { 0x0179, "IA32_MCG_CAP" }, - { 0x017a, "IA32_MCG_STATUS" }, - { 0x0199, "IA32_PERF_CONTROL" }, - { 0x019a, "IA32_THERM_CTL" }, - { 0x019b, "IA32_THERM_INTERRUPT" }, - { 0x019c, "IA32_THERM_STATUS" }, - { 0x019d, "MSR_THERM2_CTL" }, - { 0x01d9, "IA32_DEBUGCTL" }, - { 0x0200, "IA32_MTRR_PHYSBASE0" }, - { 0x0201, "IA32_MTRR_PHYSMASK0" }, - { 0x0202, "IA32_MTRR_PHYSBASE1" }, - { 0x0203, "IA32_MTRR_PHYSMASK1" }, - { 0x0204, "IA32_MTRR_PHYSBASE2" }, - { 0x0205, "IA32_MTRR_PHYSMASK2" }, - { 0x0206, "IA32_MTRR_PHYSBASE3" }, - { 0x0207, "IA32_MTRR_PHYSMASK3" }, - { 0x0208, "IA32_MTRR_PHYSBASE4" }, - { 0x0209, "IA32_MTRR_PHYSMASK4" }, - { 0x020a, "IA32_MTRR_PHYSBASE5" }, - { 0x020b, "IA32_MTRR_PHYSMASK5" }, - { 0x020c, "IA32_MTRR_PHYSBASE6" }, - { 0x020d, "IA32_MTRR_PHYSMASK6" }, - { 0x020e, "IA32_MTRR_PHYSBASE7" }, - { 0x020f, "IA32_MTRR_PHYSMASK7" }, - { 0x0250, "IA32_MTRR_FIX64K_00000" }, - { 0x0258, "IA32_MTRR_FIX16K_80000" }, - { 0x0259, "IA32_MTRR_FIX16K_A0000" }, - { 0x0268, "IA32_MTRR_FIX4K_C0000" }, - { 0x0269, "IA32_MTRR_FIX4K_C8000" }, - { 0x026a, "IA32_MTRR_FIX4K_D0000" }, - { 0x026b, "IA32_MTRR_FIX4K_D8000" }, - { 0x026c, "IA32_MTRR_FIX4K_E0000" }, - { 0x026d, "IA32_MTRR_FIX4K_E8000" }, - { 0x026e, "IA32_MTRR_FIX4K_F0000" }, - { 0x026f, "IA32_MTRR_FIX4K_F8000" }, - { 0x02ff, "IA32_MTRR_DEF_TYPE" }, - //{ 0x00c000080, "IA32_CR_EFER" }, // Seems to be RO - }; - - typedef struct { - unsigned int model; - const msr_entry_t *global_msrs; - unsigned int num_global_msrs; - const msr_entry_t *per_core_msrs; - unsigned int num_per_core_msrs; - } cpu_t; - - cpu_t cpulist[] = { - { 0x006e0, model6ex_global_msrs, ARRAY_SIZE(model6ex_global_msrs), model6ex_per_core_msrs, ARRAY_SIZE(model6ex_per_core_msrs) }, - { 0x006f0, model6fx_global_msrs, ARRAY_SIZE(model6fx_global_msrs), model6fx_per_core_msrs, ARRAY_SIZE(model6fx_per_core_msrs) }, - }; - - cpu_t *cpu = NULL; - - /* Get CPU family and model, not the stepping - * (TODO: extended family/model) - */ - id = cpuid(1) & 0xff0; - for (i = 0; i < ARRAY_SIZE(cpulist); i++) { - if(cpulist[i].model == id) { - cpu = &cpulist[i]; - break; - } - } - - if (!cpu) { - printf("Error: Dumping MSRs on this CPU (0x%06x) is not (yet) supported.\n", id); - return -1; - } - - fd_msr = open("/dev/cpu/0/msr", O_RDWR); - if (fd_msr < 0) { - perror("Error while opening /dev/cpu/0/msr"); - printf("Did you run 'modprobe msr'?\n"); - return -1; - } - - printf("\n===================== SHARED MSRs (All Cores) =====================\n"); - - for (i = 0; i < cpu->num_global_msrs; i++) { - msr = rdmsr(cpu->global_msrs[i].number); - printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n", - cpu->global_msrs[i].number, msr.hi, msr.lo, - cpu->global_msrs[i].name); - } - - close(fd_msr); - - for (core = 0; core < 8; core++) { - char msrfilename[64]; - memset(msrfilename, 0, 64); - sprintf(msrfilename, "/dev/cpu/%d/msr", core); - - fd_msr = open(msrfilename, O_RDWR); - - /* If the file is not there, we're probably through. No error, - * since we successfully opened /dev/cpu/0/msr before. - */ - if (fd_msr < 0) - break; - - printf("\n====================== UNIQUE MSRs (core %d) ======================\n", core); - - for (i = 0; i < cpu->num_per_core_msrs; i++) { - msr = rdmsr(cpu->per_core_msrs[i].number); - printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n", - cpu->per_core_msrs[i].number, msr.hi, msr.lo, - cpu->per_core_msrs[i].name); - } - - close(fd_msr); - } - - if (msr_readerror) - printf("\n(*) Some MSRs could not be read. The marked values are unreliable.\n"); - - return 0; -} void print_version(void) { @@ -817,7 +146,7 @@ void print_usage(const char *name) int main(int argc, char *argv[]) { struct pci_access *pacc; - struct pci_dev *sb, *nb; + struct pci_dev *sb = NULL, *nb, *dev; int i, opt, option_index = 0; unsigned int id; @@ -892,23 +221,47 @@ int main(int argc, char *argv[]) } } +#if defined(__FreeBSD__) + int io_fd; +#endif + +#if defined(__FreeBSD__) + if ((io_fd = open("/dev/io", O_RDWR)) < 0) { + perror("/dev/io"); +#else if (iopl(3)) { + perror("iopl"); +#endif printf("You need to be root.\n"); exit(1); } +#ifndef __DARWIN__ if ((fd_mem = open("/dev/mem", O_RDWR)) < 0) { perror("Can not open /dev/mem"); exit(1); } +#endif pacc = pci_alloc(); pci_init(pacc); pci_scan_bus(pacc); /* Find the required devices */ + for (dev = pacc->devices; dev; dev = dev->next) { + pci_fill_info(dev, PCI_FILL_CLASS); + /* The ISA/LPC bridge can be 0x1f, 0x07, or 0x04 so we probe. */ + if (dev->device_class == 0x0601) { /* ISA/LPC bridge */ + if (sb == NULL) + sb = dev; + else + fprintf(stderr, "Multiple devices with class ID" + " 0x0601, using %02x%02x:%02x.%02x\n", + dev->domain, dev->bus, dev->dev, + dev->func); + } + } - sb = pci_get_dev(pacc, 0, 0, 0x1f, 0); if (!sb) { printf("No southbridge found.\n"); exit(1); @@ -935,8 +288,16 @@ int main(int argc, char *argv[]) } id = cpuid(1); - printf("Intel CPU: Family %x, Model %x\n", - (id >> 8) & 0xf, (id >> 4) & 0xf); + + /* Intel has suggested applications to display the family of a CPU as + * the sum of the "Family" and the "Extended Family" fields shown + * above, and the model as the sum of the "Model" and the 4-bit + * left-shifted "Extended Model" fields. + * http://download.intel.com/design/processor/applnots/24161832.pdf + */ + printf("Intel CPU: Processor Type: %x, Family %x, Model %x, Stepping %x\n", + (id >> 12) & 0x3, ((id >> 8) & 0xf) + ((id >> 20) & 0xff), + ((id >> 12) & 0xf0) + ((id >> 4) & 0xf), (id & 0xf)); /* Determine names */ for (i = 0; i < ARRAY_SIZE(supported_chips_list); i++) @@ -946,10 +307,10 @@ int main(int argc, char *argv[]) if (sb->device_id == supported_chips_list[i].device_id) sbname = supported_chips_list[i].name; - printf("Intel Northbridge: %04x:%04x (%s)\n", + printf("Intel Northbridge: %04x:%04x (%s)\n", nb->vendor_id, nb->device_id, nbname); - printf("Intel Southbridge: %04x:%04x (%s)\n", + printf("Intel Southbridge: %04x:%04x (%s)\n", sb->vendor_id, sb->device_id, sbname); /* Now do the deed */ @@ -965,12 +326,12 @@ int main(int argc, char *argv[]) } if (dump_pmbase) { - print_pmbase(sb); + print_pmbase(sb, pacc); printf("\n\n"); } if (dump_mchbar) { - print_mchbar(nb); + print_mchbar(nb, pacc); printf("\n\n"); } @@ -996,7 +357,7 @@ int main(int argc, char *argv[]) /* Clean up */ pci_free_dev(nb); - pci_free_dev(sb); + // pci_free_dev(sb); // TODO: glibc detected "double free or corruption" pci_cleanup(pacc); return 0;