X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=util%2Finteltool%2Finteltool.c;h=93169d398c85bad2db7e8e03c08f8d1c47603fae;hb=bb41f502444b2d0295809cc882b829d768962990;hp=04b0a9d87f0a9601dac4545f06fda501ec7c19ff;hpb=b2aedb1a3f2409b549c4094654281893b82c7435;p=coreboot.git diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 04b0a9d87..93169d398 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -1,9 +1,10 @@ /* * inteltool - dump all registers on an Intel CPU + chipset based system. * - * Copyright (C) 2008 by coresystems GmbH - * written by Stefan Reinauer - * + * Copyright (C) 2008-2010 by coresystems GmbH + * written by Stefan Reinauer + * Copyright (C) 2009 Carl-Daniel Hailfinger + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -24,42 +25,75 @@ #include #include #include "inteltool.h" +#if defined(__FreeBSD__) +#include +#endif static const struct { uint16_t vendor_id, device_id; char *name; } supported_chips_list[] = { + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX, "82443LX" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX, "82443BX" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_NO_AGP, "82443BX without AGP" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810, "i810" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810DC, "i810-DC100" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_MC, "i810E DC-133" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82830M, "i830M" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865, "i865" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915, "82915G/P/GV/GL/PL/910GL" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "i945P" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GSE, "i945GSE" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PM965, "PM965" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q965, "Q963/965" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "i975X" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q35, "Q35" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G33, "P35/G33/G31/P31" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q33, "Q33" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58, "X58" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GS45, "GS45ME" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_DXXX, "Atom D400/500 Series" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_NXXX, "Atom N400 Series" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO, "SCH Poulsbo" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC, "SCH Poulsbo" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10R, "ICH10R" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DH, "ICH9DH" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DO, "ICH9DO" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9R, "ICH9R" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9, "ICH9" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9M, "ICH9M" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9ME, "ICH9M-E" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8M, "ICH8-M" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8, "ICH8" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10, "NM10" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7MDH, "ICH7-M DH" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7M, "ICH7-M" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7, "ICH7" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7DH, "ICH7DH" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6, "ICH6" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH5, "ICH5" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4M, "ICH4-M" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4, "ICH4" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH2, "ICH2" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH0, "ICH0" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" } + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "82371AB/EB/MB" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X44, "82X38/X48" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_32X0, "3200/3210" }, }; -#ifndef DARWIN +#ifndef __DARWIN__ static int fd_mem; -void *map_physical(unsigned long phys_addr, int len) +void *map_physical(uint64_t phys_addr, size_t len) { void *virt_addr; virt_addr = mmap(0, len, PROT_WRITE | PROT_READ, MAP_SHARED, fd_mem, (off_t) phys_addr); - + if (virt_addr == MAP_FAILED) { printf("Error mapping physical memory 0x%08lx[0x%x]\n", phys_addr, len); return NULL; @@ -68,7 +102,7 @@ void *map_physical(unsigned long phys_addr, int len) return virt_addr; } -void unmap_physical(void *virt_addr, int len) +void unmap_physical(void *virt_addr, size_t len) { munmap(virt_addr, len); } @@ -112,7 +146,7 @@ void print_usage(const char *name) int main(int argc, char *argv[]) { struct pci_access *pacc; - struct pci_dev *sb, *nb; + struct pci_dev *sb = NULL, *nb, *dev; int i, opt, option_index = 0; unsigned int id; @@ -187,12 +221,22 @@ int main(int argc, char *argv[]) } } +#if defined(__FreeBSD__) + int io_fd; +#endif + +#if defined(__FreeBSD__) + if ((io_fd = open("/dev/io", O_RDWR)) < 0) { + perror("/dev/io"); +#else if (iopl(3)) { + perror("iopl"); +#endif printf("You need to be root.\n"); exit(1); } -#ifndef DARWIN +#ifndef __DARWIN__ if ((fd_mem = open("/dev/mem", O_RDWR)) < 0) { perror("Can not open /dev/mem"); exit(1); @@ -204,8 +248,20 @@ int main(int argc, char *argv[]) pci_scan_bus(pacc); /* Find the required devices */ + for (dev = pacc->devices; dev; dev = dev->next) { + pci_fill_info(dev, PCI_FILL_CLASS); + /* The ISA/LPC bridge can be 0x1f, 0x07, or 0x04 so we probe. */ + if (dev->device_class == 0x0601) { /* ISA/LPC bridge */ + if (sb == NULL) + sb = dev; + else + fprintf(stderr, "Multiple devices with class ID" + " 0x0601, using %02x%02x:%02x.%02x\n", + dev->domain, dev->bus, dev->dev, + dev->func); + } + } - sb = pci_get_dev(pacc, 0, 0, 0x1f, 0); if (!sb) { printf("No southbridge found.\n"); exit(1); @@ -232,8 +288,16 @@ int main(int argc, char *argv[]) } id = cpuid(1); - printf("Intel CPU: Family %x, Model %x\n", - (id >> 8) & 0xf, (id >> 4) & 0xf); + + /* Intel has suggested applications to display the family of a CPU as + * the sum of the "Family" and the "Extended Family" fields shown + * above, and the model as the sum of the "Model" and the 4-bit + * left-shifted "Extended Model" fields. + * http://download.intel.com/design/processor/applnots/24161832.pdf + */ + printf("Intel CPU: Processor Type: %x, Family %x, Model %x, Stepping %x\n", + (id >> 12) & 0x3, ((id >> 8) & 0xf) + ((id >> 20) & 0xff), + ((id >> 12) & 0xf0) + ((id >> 4) & 0xf), (id & 0xf)); /* Determine names */ for (i = 0; i < ARRAY_SIZE(supported_chips_list); i++) @@ -243,10 +307,10 @@ int main(int argc, char *argv[]) if (sb->device_id == supported_chips_list[i].device_id) sbname = supported_chips_list[i].name; - printf("Intel Northbridge: %04x:%04x (%s)\n", + printf("Intel Northbridge: %04x:%04x (%s)\n", nb->vendor_id, nb->device_id, nbname); - printf("Intel Southbridge: %04x:%04x (%s)\n", + printf("Intel Southbridge: %04x:%04x (%s)\n", sb->vendor_id, sb->device_id, sbname); /* Now do the deed */ @@ -262,12 +326,12 @@ int main(int argc, char *argv[]) } if (dump_pmbase) { - print_pmbase(sb); + print_pmbase(sb, pacc); printf("\n\n"); } if (dump_mchbar) { - print_mchbar(nb); + print_mchbar(nb, pacc); printf("\n\n"); } @@ -293,7 +357,7 @@ int main(int argc, char *argv[]) /* Clean up */ pci_free_dev(nb); - pci_free_dev(sb); + // pci_free_dev(sb); // TODO: glibc detected "double free or corruption" pci_cleanup(pacc); return 0;