X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=util%2Finteltool%2Fgpio.c;h=1d48a6800e51155ffc233227abc19335af3acc2c;hb=cbb648c001167f7762e0f1aa2af906d3a8e34715;hp=105e77696ab14912ebaf4fd6228b6e51c5e165a2;hpb=2319027d7e3a9b44110794a553b10a554fed1102;p=coreboot.git

diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c
index 105e77696..1d48a6800 100644
--- a/util/inteltool/gpio.c
+++ b/util/inteltool/gpio.c
@@ -1,8 +1,8 @@
 /*
  * inteltool - dump all registers on an Intel CPU + chipset based system.
  *
- * Copyright (C) 2008 by coresystems GmbH 
- * 
+ * Copyright (C) 2008 by coresystems GmbH
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.
@@ -18,7 +18,6 @@
  */
 
 #include <stdio.h>
-#include <sys/io.h>
 #include "inteltool.h"
 
 static const io_register_t ich0_gpio_registers[] = {
@@ -40,6 +39,25 @@ static const io_register_t ich0_gpio_registers[] = {
 	{ 0x3C, 4, "RESERVED" }
 };
 
+static const io_register_t ich2_gpio_registers[] = {
+	{ 0x00, 4, "GPIO_USE_SEL" },
+	{ 0x04, 4, "GP_IO_SEL" },
+	{ 0x08, 4, "RESERVED" },
+	{ 0x0c, 4, "GP_LVL" },
+	{ 0x10, 4, "RESERVED" },
+	{ 0x14, 4, "GPO_TTL" },
+	{ 0x18, 4, "GPO_BLINK" },
+	{ 0x1c, 4, "RESERVED" },
+	{ 0x20, 4, "RESERVED" },
+	{ 0x24, 4, "RESERVED" },
+	{ 0x28, 4, "RESERVED" },
+	{ 0x2c, 4, "GPI_INV" },
+	{ 0x30, 4, "RESERVED" },
+	{ 0x34, 4, "RESERVED" },
+	{ 0x38, 4, "RESERVED" },
+	{ 0x3C, 4, "RESERVED" }
+};
+
 static const io_register_t ich4_gpio_registers[] = {
 	{ 0x00, 4, "GPIO_USE_SEL" },
 	{ 0x04, 4, "GP_IO_SEL" },
@@ -59,6 +77,40 @@ static const io_register_t ich4_gpio_registers[] = {
 	{ 0x3C, 4, "RESERVED" }
 };
 
+static const io_register_t ich5_gpio_registers[] = {
+	{ 0x00, 4, "GPIO_USE_SEL" },
+	{ 0x04, 4, "GP_IO_SEL" },
+	{ 0x08, 4, "RESERVED" },
+	{ 0x0c, 4, "GP_LVL" },
+	{ 0x10, 4, "RESERVED" },
+	{ 0x14, 4, "GPO_TTL"},
+	{ 0x18, 4, "GPO_BLINK"},
+	{ 0x1c, 4, "RESERVED" },
+	{ 0x20, 4, "RESERVED" },
+	{ 0x2c, 4, "GPI_INV" },
+	{ 0x30, 4, "GPIO_USE_SEL2" },
+	{ 0x34, 4, "GP_IO_SEL2" },
+	{ 0x38, 4, "GP_LVL2" },
+};
+
+static const io_register_t ich6_gpio_registers[] = {
+	{ 0x00, 4, "GPIO_USE_SEL" },
+	{ 0x08, 4, "RESERVED" },
+	{ 0x0c, 4, "GP_LVL" },
+	{ 0x10, 4, "RESERVED" },
+	{ 0x14, 4, "RESERVED" },
+	{ 0x18, 4, "GPO_BLINK" },
+	{ 0x1c, 4, "RESERVED" },
+	{ 0x20, 4, "RESERVED" },
+	{ 0x24, 4, "RESERVED" },
+	{ 0x28, 4, "RESERVED" },
+	{ 0x2c, 4, "GPI_INV" },
+	{ 0x30, 4, "GPIO_USE_SEL2" },
+	{ 0x34, 4, "GP_IO_SEL2" },
+	{ 0x38, 4, "GP_LVL2" },
+	{ 0x04, 4, "GP_IO_SEL" },
+};
+
 static const io_register_t ich7_gpio_registers[] = {
 	{ 0x00, 4, "GPIO_USE_SEL" },
 	{ 0x04, 4, "GP_IO_SEL" },
@@ -78,6 +130,97 @@ static const io_register_t ich7_gpio_registers[] = {
 	{ 0x3C, 4, "RESERVED" }
 };
 
+static const io_register_t ich8_gpio_registers[] = {
+	{ 0x00, 4, "GPIO_USE_SEL" },
+	{ 0x04, 4, "GP_IO_SEL" },
+	{ 0x08, 4, "RESERVED" },
+	{ 0x0c, 4, "GP_LVL" },
+	{ 0x10, 4, "GPIO_USE_SEL Override (LOW)" },
+	{ 0x14, 4, "RESERVED" },
+	{ 0x18, 4, "GPO_BLINK" },
+	{ 0x1c, 4, "GP_SER_BLINK" },
+	{ 0x20, 4, "GP_SB_CMDSTS" },
+	{ 0x24, 4, "GP_SB_DATA" },
+	{ 0x28, 4, "RESERVED" },
+	{ 0x2c, 4, "GPI_INV" },
+	{ 0x30, 4, "GPIO_USE_SEL2" },
+	{ 0x34, 4, "GP_IO_SEL2" },
+	{ 0x38, 4, "GP_LVL2" },
+	{ 0x3C, 4, "GPIO_USE_SEL Override (HIGH)" }
+};
+
+static const io_register_t ich9_gpio_registers[] = {
+	{ 0x00, 4, "GPIO_USE_SEL" },
+	{ 0x04, 4, "GP_IO_SEL" },
+	{ 0x08, 4, "RESERVED" },
+	{ 0x0c, 4, "GP_LVL" },
+	{ 0x10, 4, "RESERVED" },
+	{ 0x14, 4, "RESERVED" },
+	{ 0x18, 4, "GPO_BLINK" },
+	{ 0x1c, 4, "GP_SER_BLINK" },
+	{ 0x20, 4, "GP_SB_CMDSTS" },
+	{ 0x24, 4, "GP_SB_DATA" },
+	{ 0x28, 4, "RESERVED" },
+	{ 0x2c, 4, "GPI_INV" },
+	{ 0x30, 4, "GPIO_USE_SEL2" },
+	{ 0x34, 4, "GP_IO_SEL2" },
+	{ 0x38, 4, "GP_LVL2" },
+	{ 0x3C, 4, "RESERVED" }
+};
+
+static const io_register_t ich10_gpio_registers[] = {
+	{ 0x00, 4, "GPIO_USE_SEL" },
+	{ 0x04, 4, "GP_IO_SEL" },
+	{ 0x08, 4, "RESERVED" },
+	{ 0x0c, 4, "GP_LVL" },
+	{ 0x10, 4, "RESERVED" },
+	{ 0x14, 4, "RESERVED" },
+	{ 0x18, 4, "GPO_BLINK" },
+	{ 0x1c, 4, "GP_SER_BLINK" },
+	{ 0x20, 4, "GP_SB_CMDSTS" },
+	{ 0x24, 4, "GP_SB_DATA" },
+	{ 0x28, 4, "RESERVED" },
+	{ 0x2c, 4, "GPI_INV" },
+	{ 0x30, 4, "GPIO_USE_SEL2" },
+	{ 0x34, 4, "GP_IO_SEL2" },
+	{ 0x38, 4, "GP_LVL2" },
+	{ 0x3C, 4, "RESERVED" },
+	{ 0x40, 4, "GPIO_USE_SEL3" },
+	{ 0x44, 4, "GPIO_SEL3" },
+	{ 0x48, 4, "GPIO_LVL3" },
+	{ 0x4c, 4, "RESERVED" },
+	{ 0x50, 4, "RESERVED" },
+	{ 0x54, 4, "RESERVED" },
+	{ 0x58, 4, "RESERVED" },
+	{ 0x5c, 4, "RESERVED" },
+	{ 0x60, 4, "GP_RST_SEL" },
+	{ 0x64, 4, "RESERVED" },
+	{ 0x68, 4, "RESERVED" },
+	{ 0x6c, 4, "RESERVED" },
+	{ 0x70, 4, "RESERVED" },
+	{ 0x74, 4, "RESERVED" },
+	{ 0x78, 4, "RESERVED" },
+	{ 0x7c, 4, "RESERVED" },
+};
+
+static const io_register_t i631x_gpio_registers[] = {
+	{ 0x00, 4, "GPIO_USE_SEL" },
+	{ 0x04, 4, "GP_IO_SEL" },
+	{ 0x08, 4, "RESERVED" },
+	{ 0x0c, 4, "GP_LVL" },
+	{ 0x10, 4, "RESERVED" },
+	{ 0x14, 4, "RESERVED" },
+	{ 0x18, 4, "GPO_BLINK" },
+	{ 0x1c, 4, "RESERVED" },
+	{ 0x20, 4, "RESERVED" },
+	{ 0x24, 4, "RESERVED" },
+	{ 0x28, 4, "RESERVED" },
+	{ 0x2c, 4, "GPI_INV" },
+	{ 0x30, 4, "GPIO_USE_SEL2" },
+	{ 0x34, 4, "GP_IO_SEL2" },
+	{ 0x38, 4, "GP_LVL2" },
+};
+
 int print_gpios(struct pci_dev *sb)
 {
 	int i, size;
@@ -87,26 +230,73 @@ int print_gpios(struct pci_dev *sb)
 	printf("\n============= GPIOS =============\n\n");
 
 	switch (sb->device_id) {
+	case PCI_DEVICE_ID_INTEL_ICH10R:
+		gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
+		gpio_registers = ich10_gpio_registers;
+		size = ARRAY_SIZE(ich10_gpio_registers);
+		break;
+	case PCI_DEVICE_ID_INTEL_ICH9DH:
+	case PCI_DEVICE_ID_INTEL_ICH9DO:
+	case PCI_DEVICE_ID_INTEL_ICH9R:
+	case PCI_DEVICE_ID_INTEL_ICH9:
+	case PCI_DEVICE_ID_INTEL_ICH9M:
+	case PCI_DEVICE_ID_INTEL_ICH9ME:
+		gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
+		gpio_registers = ich9_gpio_registers;
+		size = ARRAY_SIZE(ich9_gpio_registers);
+		break;
+	case PCI_DEVICE_ID_INTEL_ICH8:
+	case PCI_DEVICE_ID_INTEL_ICH8M:
+		gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
+		gpio_registers = ich8_gpio_registers;
+		size = ARRAY_SIZE(ich8_gpio_registers);
+		break;
 	case PCI_DEVICE_ID_INTEL_ICH7:
 	case PCI_DEVICE_ID_INTEL_ICH7M:
 	case PCI_DEVICE_ID_INTEL_ICH7DH:
 	case PCI_DEVICE_ID_INTEL_ICH7MDH:
+	case PCI_DEVICE_ID_INTEL_NM10:
 		gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
 		gpio_registers = ich7_gpio_registers;
 		size = ARRAY_SIZE(ich7_gpio_registers);
 		break;
+	case PCI_DEVICE_ID_INTEL_ICH6:
+		gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
+		gpio_registers = ich6_gpio_registers;
+		size = ARRAY_SIZE(ich6_gpio_registers);
+		break;
+	case PCI_DEVICE_ID_INTEL_ICH5:
+		gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
+		gpio_registers = ich5_gpio_registers;
+		size = ARRAY_SIZE(ich5_gpio_registers);
+		break;
 	case PCI_DEVICE_ID_INTEL_ICH4:
 	case PCI_DEVICE_ID_INTEL_ICH4M:
 		gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
 		gpio_registers = ich4_gpio_registers;
 		size = ARRAY_SIZE(ich4_gpio_registers);
 		break;
+	case PCI_DEVICE_ID_INTEL_ICH2:
+		gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
+		gpio_registers = ich2_gpio_registers;
+		size = ARRAY_SIZE(ich2_gpio_registers);
+		break;
 	case PCI_DEVICE_ID_INTEL_ICH:
 	case PCI_DEVICE_ID_INTEL_ICH0:
 		gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
 		gpio_registers = ich0_gpio_registers;
 		size = ARRAY_SIZE(ich0_gpio_registers);
 		break;
+
+	case PCI_DEVICE_ID_INTEL_I63XX:
+		gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
+		gpio_registers = i631x_gpio_registers;
+		size = ARRAY_SIZE(i631x_gpio_registers);
+		break;
+
+	case PCI_DEVICE_ID_INTEL_82371XX:
+		printf("This southbridge has GPIOs in the PM unit.\n");
+		return 1;
 	case 0x1234: // Dummy for non-existent functionality
 		printf("This southbridge does not have GPIOBASE.\n");
 		return 1;
@@ -142,4 +332,3 @@ int print_gpios(struct pci_dev *sb)
 
 	return 0;
 }
-