X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=usb%2Fhost%2Fohci.h;h=51be9bf31b1100845be2cd70ad47d486beb41b06;hb=316456cf22ec6843102b39cb4a33b4bb3e484d45;hp=224872fcac599ba0d72c3c44e2c0c36bae17e94c;hpb=7bff2456c919b94efa534efd15dec289314a682e;p=ppcskel.git

diff --git a/usb/host/ohci.h b/usb/host/ohci.h
index 224872f..51be9bf 100644
--- a/usb/host/ohci.h
+++ b/usb/host/ohci.h
@@ -62,23 +62,6 @@ Copyright (C) 2009     Sebastian Falbesoner <sebastian.falbesoner@gmail.com>
 #define OHCI_INTR_OC   (1 << 30)       /* ownership change */
 #define OHCI_INTR_MIE  (1 << 31)       /* master interrupt enable */
 
-/*
- * masks used with interrupt registers:
- * HcInterruptStatus (intrstatus)
- * HcInterruptEnable (intrenable)
- * HcInterruptDisable (intrdisable)
- */
-#define OHCI_INTR_SO   (1 << 0)        /* scheduling overrun */
-#define OHCI_INTR_WDH  (1 << 1)        /* writeback of done_head */
-#define OHCI_INTR_SF   (1 << 2)        /* start frame */
-#define OHCI_INTR_RD   (1 << 3)        /* resume detect */
-#define OHCI_INTR_UE   (1 << 4)        /* unrecoverable error */
-#define OHCI_INTR_FNO  (1 << 5)        /* frame number overflow */
-#define OHCI_INTR_RHSC (1 << 6)        /* root hub status change */
-#define OHCI_INTR_OC   (1 << 30)       /* ownership change */
-#define OHCI_INTR_MIE  (1 << 31)       /* master interrupt enable */
-
-
 /* For initializing controller (mask in an HCFS mode too) */
 #define OHCI_CONTROL_INIT      (3 << 0)
 #define        OHCI_INTR_INIT \
@@ -124,17 +107,98 @@ Copyright (C) 2009     Sebastian Falbesoner <sebastian.falbesoner@gmail.com>
 
 struct ohci_hcca {
 #define NUM_INITS 32
-       u32 int_table[NUM_INITS]; /* periodic schedule */
-       /*
-        * OHCI defines u16 frame_no, followed by u16 zero pad.
-        * Since some processors can't do 16 bit bus accesses,
-        * portable access must be a 32 bits wide.
-        */
-       u32     frame_no;               /* current frame number */
-       u32     done_head;              /* info returned for an interrupt */
-       u8 reserved_for_hc [116];
-       u8 what [4];            /* spec only identifies 252 bytes :) */
+	u32 int_table[NUM_INITS]; /* periodic schedule */
+	/*
+	 * OHCI defines u16 frame_no, followed by u16 zero pad.
+	 * Since some processors can't do 16 bit bus accesses,
+	 * portable access must be a 32 bits wide.
+	 */
+	u32 frame_no;			/* current frame number */
+	u32 done_head;		/* info returned for an interrupt */
+	u8 reserved_for_hc [116];
+	u8 what [4];		   /* spec only identifies 252 bytes :) */
 } ALIGNED(256);
 
+struct endpoint_descriptor {
+	/* required by HC */
+	u32 flags;
+	u32 tailp;
+	u32 headp;
+	u32 nexted;
+
+	/* required by software */
+	u32 tdcount;
+} ALIGNED(16);
+
+#define	OHCI_ENDPOINT_ADDRESS_MASK				0x0000007f
+#define	OHCI_ENDPOINT_GET_DEVICE_ADDRESS(s)		((s) & 0x7f)
+#define	OHCI_ENDPOINT_SET_DEVICE_ADDRESS(s)		(s)
+#define	OHCI_ENDPOINT_GET_ENDPOINT_NUMBER(s)	(((s) >> 7) & 0xf)
+#define	OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(s)	((s) << 7)
+#define	OHCI_ENDPOINT_DIRECTION_MASK			0x00001800
+#define	OHCI_ENDPOINT_DIRECTION_DESCRIPTOR		0x00000000
+#define	OHCI_ENDPOINT_DIRECTION_OUT				0x00000800
+#define	OHCI_ENDPOINT_DIRECTION_IN				0x00001000
+#define	OHCI_ENDPOINT_LOW_SPEED					0x00002000
+#define	OHCI_ENDPOINT_FULL_SPEED				0x00000000
+#define	OHCI_ENDPOINT_SKIP						0x00004000
+#define	OHCI_ENDPOINT_GENERAL_FORMAT			0x00000000
+#define	OHCI_ENDPOINT_ISOCHRONOUS_FORMAT		0x00008000
+#define	OHCI_ENDPOINT_MAX_PACKET_SIZE_MASK		(0x7ff << 16)
+#define	OHCI_ENDPOINT_GET_MAX_PACKET_SIZE(s)	(((s) >> 16) & 0x07ff)
+#define	OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(s)	((s) << 16)
+#define	OHCI_ENDPOINT_HALTED					0x00000001
+#define	OHCI_ENDPOINT_TOGGLE_CARRY				0x00000002
+#define	OHCI_ENDPOINT_HEAD_MASK					0xfffffffc
+
+
+struct general_td {
+	/* required by HC */
+	u32 flags;
+	u32 cbp;
+	u32 nexttd;
+	u32 be;
+
+	/* required by software */
+	u32 bufaddr;
+	u32 buflen;
+	u32 pad1;
+	u32 pad2;
+} ALIGNED(16);
+
+#define	OHCI_TD_BUFFER_ROUNDING			0x00040000
+#define	OHCI_TD_DIRECTION_PID_MASK		0x00180000
+#define	OHCI_TD_DIRECTION_PID_SETUP		0x00000000
+#define	OHCI_TD_DIRECTION_PID_OUT		0x00080000
+#define	OHCI_TD_DIRECTION_PID_IN		0x00100000
+#define	OHCI_TD_GET_DELAY_INTERRUPT(x)	(((x) >> 21) & 7)
+#define	OHCI_TD_SET_DELAY_INTERRUPT(x)	((x) << 21)
+#define	OHCI_TD_INTERRUPT_MASK			0x00e00000
+#define	OHCI_TD_TOGGLE_CARRY			0x00000000
+#define	OHCI_TD_TOGGLE_0				0x02000000
+#define	OHCI_TD_TOGGLE_1				0x03000000
+#define	OHCI_TD_TOGGLE_MASK				0x03000000
+#define	OHCI_TD_GET_ERROR_COUNT(x)		(((x) >> 26) & 3)
+#define	OHCI_TD_GET_CONDITION_CODE(x)	((x) >> 28)
+#define	OHCI_TD_SET_CONDITION_CODE(x)	((x) << 28)
+#define	OHCI_TD_CONDITION_CODE_MASK		0xf0000000
+
+#define OHCI_TD_INTERRUPT_IMMEDIATE			0x00
+#define OHCI_TD_INTERRUPT_NONE				0x07
+
+#define OHCI_TD_CONDITION_NO_ERROR			0x00
+#define OHCI_TD_CONDITION_CRC_ERROR			0x01
+#define OHCI_TD_CONDITION_BIT_STUFFING		0x02
+#define OHCI_TD_CONDITION_TOGGLE_MISMATCH	0x03
+#define OHCI_TD_CONDITION_STALL				0x04
+#define OHCI_TD_CONDITION_NO_RESPONSE		0x05
+#define OHCI_TD_CONDITION_PID_CHECK_FAILURE	0x06
+#define OHCI_TD_CONDITION_UNEXPECTED_PID	0x07
+#define OHCI_TD_CONDITION_DATA_OVERRUN		0x08
+#define OHCI_TD_CONDITION_DATA_UNDERRUN		0x09
+#define OHCI_TD_CONDITION_BUFFER_OVERRUN	0x0c
+#define OHCI_TD_CONDITION_BUFFER_UNDERRUN	0x0d
+#define OHCI_TD_CONDITION_NOT_ACCESSED		0x0f
+
 #endif