X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=usb%2Fhost%2Fohci.c;h=bb0a3c0acfb5957195bc1ad6e6494251156e8c99;hb=8c443e089d9f0202d06e0b5d656fd713b14fc9bc;hp=79283ae2931bca0d20c80427312ad072faa055b9;hpb=fcf79bc1bc34cfc6709870e24efc35766587febd;p=ppcskel.git diff --git a/usb/host/ohci.c b/usb/host/ohci.c index 79283ae..bb0a3c0 100644 --- a/usb/host/ohci.c +++ b/usb/host/ohci.c @@ -18,6 +18,9 @@ Copyright (C) 2009 Sebastian Falbesoner #include "host.h" #include "../usbspec/usb11spec.h" +/* activate control_quirk */ +#define _USE_C_Q + /* macro for accessing u32 variables that need to be in little endian byte order; * * whenever you read or write from an u32 field that the ohci host controller @@ -28,26 +31,15 @@ Copyright (C) 2009 Sebastian Falbesoner (((dword) & 0x0000FF00) << 8) | \ (((dword) & 0x000000FF) << 24) ) -static struct endpoint_descriptor *allocate_endpoint(); static struct general_td *allocate_general_td(); -static void control_quirk(); -static void dbg_op_state(); -//static void dbg_td_flag(u32 flag); -static void configure_ports(u8 from_init); -static void setup_port(u32 reg, u8 from_init); +static void dbg_op_state(u32 reg); +static void configure_ports(u8 from_init, u32 reg); +static void setup_port(u32 ohci, u32 reg, u8 from_init); +static void set_target_hcca(u32 reg); static struct ohci_hcca hcca_oh0; - - -static struct endpoint_descriptor *allocate_endpoint() -{ - struct endpoint_descriptor *ep; - ep = (struct endpoint_descriptor *)memalign(16, sizeof(struct endpoint_descriptor)); - memset(ep, 0, sizeof(struct endpoint_descriptor)); - ep->flags = LE(OHCI_ENDPOINT_GENERAL_FORMAT); - ep->headp = ep->tailp = ep->nexted = LE(0); - return ep; -} +static struct ohci_hcca hcca_oh1; +struct ohci_hcca *hcca; static struct general_td *allocate_general_td() { @@ -60,84 +52,10 @@ static struct general_td *allocate_general_td() return td; } -static void control_quirk() -{ - static struct endpoint_descriptor *ed = 0; /* empty ED */ - static struct general_td *td = 0; /* dummy TD */ - u32 head; - u32 current; - u32 status; - - /* - * One time only. - * Allocate and keep a special empty ED with just a dummy TD. - */ - if (!ed) { - ed = allocate_endpoint(); - if (!ed) - return; - - td = allocate_general_td(0); - if (!td) { - free(ed); - ed = NULL; - return; - } - - ed->tailp = ed->headp = LE(virt_to_phys((void*) ((u32)td & OHCI_ENDPOINT_HEAD_MASK))); - ed->flags |= LE(OHCI_ENDPOINT_DIRECTION_OUT); - } - - /* - * The OHCI USB host controllers on the Nintendo Wii - * video game console stop working when new TDs are - * added to a scheduled control ED after a transfer has - * has taken place on it. - * - * Before scheduling any new control TD, we make the - * controller happy by always loading a special control ED - * with a single dummy TD and letting the controller attempt - * the transfer. - * The controller won't do anything with it, as the special - * ED has no TDs, but it will keep the controller from failing - * on the next transfer. - */ - head = read32(OHCI0_HC_CTRL_HEAD_ED); - if (head) { - printf("head: 0x%08X\n", head); - /* - * Load the special empty ED and tell the controller to - * process the control list. - */ - sync_after_write(ed, 16); - sync_after_write(td, 16); - write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(ed)); - - status = read32(OHCI0_HC_CONTROL); - set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE); - write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF); - - /* spin until the controller is done with the control list */ - current = read32(OHCI0_HC_CTRL_CURRENT_ED); - while(!current) { - udelay(10); - current = read32(OHCI0_HC_CTRL_CURRENT_ED); - } - - printf("current: 0x%08X\n", current); - - /* restore the old control head and control settings */ - write32(OHCI0_HC_CONTROL, status); - write32(OHCI0_HC_CTRL_HEAD_ED, head); - } else { - printf("nohead!\n"); - } -} - -static void dbg_op_state() +static void dbg_op_state(u32 reg) { - switch (read32(OHCI0_HC_CONTROL) & OHCI_CTRL_HCFS) { + switch (read32(reg+OHCI_HC_CONTROL) & OHCI_CTRL_HCFS) { case OHCI_USB_SUSPEND: printf("ohci-- OHCI_USB_SUSPEND\n"); break; @@ -153,6 +71,7 @@ static void dbg_op_state() } } +#ifdef _DU_OHCI_F_HALT static void dbg_td_flag(u32 flag) { printf("**************** dbg_td_flag: 0x%08X ***************\n", flag); @@ -164,8 +83,9 @@ static void dbg_td_flag(u32 flag) printf(" R: %X\n", (flag>>18)&1); printf("********************************************************\n"); } +#endif -static void general_td_fill(struct general_td *dest, const usb_transfer_descriptor *src) +static void general_td_fill(struct general_td *dest, const struct usb_transfer_descriptor *src) { if(src->actlen) { dest->cbp = LE(virt_to_phys(src->buffer)); @@ -183,100 +103,156 @@ static void general_td_fill(struct general_td *dest, const usb_transfer_descript dest->flags &= LE(~OHCI_TD_DIRECTION_PID_MASK); switch(src->pid) { case USB_PID_SETUP: +#ifdef _DU_OHCI_Q printf("pid_setup\n"); +#endif dest->flags |= LE(OHCI_TD_DIRECTION_PID_SETUP); dest->flags |= LE(OHCI_TD_TOGGLE_0); dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING); break; case USB_PID_OUT: +#ifdef _DU_OHCI_Q printf("pid_out\n"); +#endif dest->flags |= LE(OHCI_TD_DIRECTION_PID_OUT); dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING); - /* - * TODO: just temporary solution! (consider it with len?) - * there can be also regular PID_OUT pakets - */ - dest->flags |= LE(OHCI_TD_TOGGLE_1); + dest->flags |= src->togl ? LE(OHCI_TD_TOGGLE_1) : LE(OHCI_TD_TOGGLE_0); break; case USB_PID_IN: +#ifdef _DU_OHCI_Q printf("pid_in\n"); +#endif dest->flags |= LE(OHCI_TD_DIRECTION_PID_IN); - dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING); - /* - * let the endpoint do the togglestuff! - * TODO: just temporary solution! - * there can be also inregular PID_IN pakets (@Status Stage) - */ - dest->flags |= LE(OHCI_TD_TOGGLE_CARRY); -#if 0 - /* should be done by HC! - * first pid_in start with DATA0 */ - */ - dummyconfig.headp = LE( src->togl ? - LE(dummyconfig.headp) | OHCI_ENDPOINT_TOGGLE_CARRY : - LE(dummyconfig.headp) & ~OHCI_ENDPOINT_TOGGLE_CARRY); + if(src->maxp > src->actlen) { + dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING); +#ifdef _DU_OHCI_Q + printf("round buffer!\n"); #endif + } + dest->flags |= src->togl ? LE(OHCI_TD_TOGGLE_1) : LE(OHCI_TD_TOGGLE_0); break; } dest->flags |= LE(OHCI_TD_SET_DELAY_INTERRUPT(7)); } +#ifdef _DU_OHCI_F_HALT static void dump_address(void *addr, u32 size, const char* str) { printf("%s hexdump (%d) @ 0x%08X:\n", str, size, addr); hexdump(addr, size); } +#endif static struct endpoint_descriptor _edhead; struct endpoint_descriptor *edhead = 0; -void hcdi_fire() +void hcdi_fire(u32 reg) { +#ifdef _DU_OHCI_F printf("<^> <^> <^> hcdi_fire(start)\n"); +#endif if(edhead == 0) return; - control_quirk(); //required? YES! :O ... erm... or no? :/ ... in fact I have no idea - write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(edhead)); +#ifdef _USE_C_Q + /* quirk... 11ms seems to be a minimum :O */ + udelay(11000); +#endif + + write32(reg+OHCI_HC_CTRL_HEAD_ED, virt_to_phys(edhead)); /* sync it all */ sync_after_write(edhead, sizeof(struct endpoint_descriptor)); +#ifdef _DU_OHCI_F dump_address(edhead, sizeof(struct endpoint_descriptor), "edhead(before)"); +#endif struct general_td *x = phys_to_virt(LE(edhead->headp) & OHCI_ENDPOINT_HEAD_MASK); - printf("STRUCT LEN: %d\n", sizeof(struct general_td)); while(virt_to_phys(x)) { sync_after_write(x, sizeof(struct general_td)); +#ifdef _DU_OHCI_F dump_address(x, sizeof(struct general_td), "x(before)"); +#endif if(x->buflen > 0) { sync_after_write((void*) phys_to_virt(LE(x->cbp)), x->buflen); +#ifdef _DU_OHCI_F dump_address((void*) phys_to_virt(LE(x->cbp)), x->buflen, "x->cbp(before)"); +#endif } x = phys_to_virt(LE(x->nexttd)); } /* trigger control list */ - set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE); - write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF); + set32(reg+OHCI_HC_CONTROL, OHCI_CTRL_CLE); + write32(reg+OHCI_HC_COMMAND_STATUS, OHCI_CLF); + struct general_td *n=0, *prev = 0, *next = 0; /* poll until edhead->headp is null */ do { sync_before_read(edhead, sizeof(struct endpoint_descriptor)); +#ifdef _DU_OHCI_F printf("edhead->headp: 0x%08X\n", LE(edhead->headp)); +#endif + + /* if halted, debug output plz. will break the transfer */ + if((LE(edhead->headp) & OHCI_ENDPOINT_HALTED)) { + n = phys_to_virt(LE(edhead->headp)&~0xf); + prev = phys_to_virt((u32)prev); +#ifdef _DU_OHCI_F_HALT + printf("halted!\n"); +#endif + + sync_before_read((void*) n, sizeof(struct general_td)); +#ifdef _DU_OHCI_F_HALT + printf("n: 0x%08X\n", n); + dump_address(n, sizeof(struct general_td), "n(after)"); +#endif + if(n->buflen > 0) { + sync_before_read((void*) n->bufaddr, n->buflen); +#ifdef _DU_OHCI_F_HALT + dump_address((void*) n->bufaddr, n->buflen, "n->bufaddr(after)"); +#endif + } +#ifdef _DU_OHCI_F_HALT + dbg_td_flag(LE(n->flags)); +#endif + + sync_before_read((void*) prev, sizeof(struct general_td)); +#ifdef _DU_OHCI_F_HALT + printf("prev: 0x%08X\n", prev); + dump_address(prev, sizeof(struct general_td), "prev(after)"); +#endif + if(prev->buflen >0) { + sync_before_read((void*) prev->bufaddr, prev->buflen); +#ifdef _DU_OHCI_F_HALT + dump_address((void*) prev->bufaddr, prev->buflen, "prev->bufaddr(after)"); +#endif + } +#ifdef _DU_OHCI_F_HALT + dbg_td_flag(LE(prev->flags)); + printf("halted end!\n"); +#endif + goto out; + } + prev = (struct general_td*) (LE(edhead->headp)&~0xf); } while(LE(edhead->headp)&~0xf); - struct general_td *n = phys_to_virt(read32(OHCI0_HC_DONE_HEAD) & ~1); - printf("hc_done_head: 0x%08X\n", read32(OHCI0_HC_DONE_HEAD)); + n = phys_to_virt(read32(reg+OHCI_HC_DONE_HEAD) & ~1); +#ifdef _DU_OHCI_F + printf("hc_done_head: 0x%08X\n", read32(reg+OHCI_HC_DONE_HEAD)); +#endif - struct general_td *prev = 0, *next = 0; + prev = 0; next = 0; /* reverse done queue */ while(virt_to_phys(n) && edhead->tdcount) { sync_before_read((void*) n, sizeof(struct general_td)); +#ifdef _DU_OHCI_F printf("n: 0x%08X\n", n); printf("next: 0x%08X\n", next); printf("prev: 0x%08X\n", prev); +#endif next = n; n = (struct general_td*) phys_to_virt(LE(n->nexttd)); @@ -289,40 +265,55 @@ void hcdi_fire() n = next; prev = 0; while(virt_to_phys(n)) { +#ifdef _DU_OHCI_F dump_address(n, sizeof(struct general_td), "n(after)"); - +#endif if(n->buflen > 0) { sync_before_read((void*) n->bufaddr, n->buflen); +#ifdef _DU_OHCI_F dump_address((void*) n->bufaddr, n->buflen, "n->bufaddr(after)"); +#endif } +#ifdef _DU_OHCI_F dbg_td_flag(LE(n->flags)); +#endif prev = n; n = (struct general_td*) n->nexttd; free(prev); } - hcca_oh0.done_head = 0; - sync_after_write(&hcca_oh0, sizeof(hcca_oh0)); + set_target_hcca(reg); + hcca->done_head = 0; + sync_after_write(hcca, sizeof(*hcca)); - write32(OHCI0_HC_CONTROL, read32(OHCI0_HC_CONTROL)&~OHCI_CTRL_CLE); +out: + write32(reg+OHCI_HC_CONTROL, read32(reg+OHCI_HC_CONTROL)&~OHCI_CTRL_CLE); edhead = 0; +#ifdef _DU_OHCI_F printf("<^> <^> <^> hcdi_fire(end)\n"); +#endif } /** * Enqueue a transfer descriptor. */ -u8 hcdi_enqueue(const usb_transfer_descriptor *td) { +u8 hcdi_enqueue(const struct usb_transfer_descriptor *td, u32 reg) { +#ifdef _DU_OHCI_Q printf("*()*()*()*()*()*()*() hcdi_enqueue(start)\n"); +#endif if(!edhead) { edhead = &_edhead; memset(edhead, 0, sizeof(struct endpoint_descriptor)); edhead->flags = LE(OHCI_ENDPOINT_GENERAL_FORMAT); edhead->headp = edhead->tailp = edhead->nexted = LE(0); - edhead->flags |= LE(OHCI_ENDPOINT_LOW_SPEED | - OHCI_ENDPOINT_SET_DEVICE_ADDRESS(td->devaddress) | + if(td->fullspeed) { + edhead->flags |= LE(OHCI_ENDPOINT_FULL_SPEED); + } else { + edhead->flags |= LE(OHCI_ENDPOINT_LOW_SPEED); + } + edhead->flags |= LE(OHCI_ENDPOINT_SET_DEVICE_ADDRESS(td->devaddress) | OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(td->endpoint) | OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(td->maxp)); edhead->tdcount = 0; @@ -345,11 +336,15 @@ u8 hcdi_enqueue(const usb_transfer_descriptor *td) { n = phys_to_virt(LE(n->nexttd)); } n->nexttd = LE(virt_to_phys((void*) ((u32)tdhw & OHCI_ENDPOINT_HEAD_MASK))); +#ifdef _DU_OHCI_Q printf("n: 0x%08X\n", n); printf("n->nexttd: 0x%08X\n", phys_to_virt(LE(n->nexttd))); +#endif } +#ifdef _DU_OHCI_Q printf("*()*()*()*()*()*()*() hcdi_enqueue(end)\n"); +#endif return 0; } @@ -357,22 +352,22 @@ u8 hcdi_enqueue(const usb_transfer_descriptor *td) { /** * Remove an transfer descriptor from transfer queue. */ -u8 hcdi_dequeue(usb_transfer_descriptor *td) { +u8 hcdi_dequeue(struct usb_transfer_descriptor *td, u32 reg) { return 0; } -void hcdi_init() +void hcdi_init(u32 reg) { printf("ohci-- init\n"); - dbg_op_state(); + dbg_op_state(reg); /* disable hc interrupts */ - set32(OHCI0_HC_INT_DISABLE, OHCI_INTR_MIE); + set32(reg+OHCI_HC_INT_DISABLE, OHCI_INTR_MIE); /* save fmInterval and calculate FSMPS */ #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7)) #define FI 0x2edf /* 12000 bits per frame (-1) */ - u32 fmint = read32(OHCI0_HC_FM_INTERVAL) & 0x3fff; + u32 fmint = read32(reg+OHCI_HC_FM_INTERVAL) & 0x3fff; if(fmint != FI) printf("ohci-- fminterval delta: %d\n", fmint - FI); fmint |= FSMP (fmint) << 16; @@ -381,11 +376,11 @@ void hcdi_init() set32(EHCI_CTL, EHCI_CTL_OH0INTE | EHCI_CTL_OH1INTE | 0xe0000); /* reset HC */ - write32(OHCI0_HC_COMMAND_STATUS, OHCI_HCR); + write32(reg+OHCI_HC_COMMAND_STATUS, OHCI_HCR); /* wait max. 30us */ u32 ts = 30; - while ((read32(OHCI0_HC_COMMAND_STATUS) & OHCI_HCR) != 0) { + while ((read32(reg+OHCI_HC_COMMAND_STATUS) & OHCI_HCR) != 0) { if(--ts == 0) { printf("ohci-- FAILED"); return; @@ -401,59 +396,65 @@ void hcdi_init() /* Tell the controller where the control and bulk lists are * The lists are empty now. */ - write32(OHCI0_HC_CTRL_HEAD_ED, 0); - write32(OHCI0_HC_BULK_HEAD_ED, 0); + write32(reg+OHCI_HC_CTRL_HEAD_ED, 0); + write32(reg+OHCI_HC_BULK_HEAD_ED, 0); /* set hcca adress */ - sync_after_write(&hcca_oh0, 256); - write32(OHCI0_HC_HCCA, virt_to_phys(&hcca_oh0)); + set_target_hcca(reg); + sync_after_write(hcca, 256); + write32(reg+OHCI_HC_HCCA, virt_to_phys(hcca)); /* set periodicstart */ #define FIT (1<<31) - u32 fmInterval = read32(OHCI0_HC_FM_INTERVAL) &0x3fff; - u32 fit = read32(OHCI0_HC_FM_INTERVAL) & FIT; + u32 fmInterval = read32(reg+OHCI_HC_FM_INTERVAL) &0x3fff; + u32 fit = read32(reg+OHCI_HC_FM_INTERVAL) & FIT; - write32(OHCI0_HC_FM_INTERVAL, fmint | (fit ^ FIT)); - write32(OHCI0_HC_PERIODIC_START, ((9*fmInterval)/10)&0x3fff); + write32(reg+OHCI_HC_FM_INTERVAL, fmint | (fit ^ FIT)); + write32(reg+OHCI_HC_PERIODIC_START, ((9*fmInterval)/10)&0x3fff); /* testing bla */ - if ((read32(OHCI0_HC_FM_INTERVAL) & 0x3fff0000) == 0 || !read32(OHCI0_HC_PERIODIC_START)) { + if ((read32(reg+OHCI_HC_FM_INTERVAL) & 0x3fff0000) == 0 || !read32(reg+OHCI_HC_PERIODIC_START)) { printf("ohci-- w00t, fail!! see ohci-hcd.c:669\n"); } /* start HC operations */ - write32(OHCI0_HC_CONTROL, OHCI_CONTROL_INIT | OHCI_USB_OPER); + write32(reg+OHCI_HC_CONTROL, OHCI_CONTROL_INIT | OHCI_USB_OPER); /* wake on ConnectStatusChange, matching external hubs */ - write32(OHCI0_HC_RH_STATUS, /*RH_HS_DRWE |*/ RH_HS_LPSC); + write32(reg+OHCI_HC_RH_STATUS, /*RH_HS_DRWE |*/ RH_HS_LPSC); /* Choose the interrupts we care about now, others later on demand */ - write32(OHCI0_HC_INT_STATUS, ~0); - write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_INIT); + write32(reg+OHCI_HC_INT_STATUS, ~0); + write32(reg+OHCI_HC_INT_ENABLE, OHCI_INTR_INIT); //wtf? - wait_ms ((read32(OHCI0_HC_RH_DESCRIPTOR_A) >> 23) & 0x1fe); + wait_ms ((read32(reg+OHCI_HC_RH_DESCRIPTOR_A) >> 23) & 0x1fe); - configure_ports((u8)1); + configure_ports((u8)1, reg); irq_restore(cookie); - dbg_op_state(); + dbg_op_state(reg); } -static void configure_ports(u8 from_init) +static void configure_ports(u8 from_init, u32 reg) { - printf("OHCI0_HC_RH_DESCRIPTOR_A:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_A)); - printf("OHCI0_HC_RH_DESCRIPTOR_B:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_B)); - printf("OHCI0_HC_RH_STATUS:\t\t0x%08X\n", read32(OHCI0_HC_RH_STATUS)); - printf("OHCI0_HC_RH_PORT_STATUS_1:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_1)); - printf("OHCI0_HC_RH_PORT_STATUS_2:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_2)); - - setup_port(OHCI0_HC_RH_PORT_STATUS_1, from_init); - setup_port(OHCI0_HC_RH_PORT_STATUS_2, from_init); +#ifdef _DU_OHCI_RH + printf("=== Roothub @ %s ===\n", reg == OHCI0_REG_BASE ? "OHCI0" : "OHCI1"); + printf("OHCI_HC_RH_DESCRIPTOR_A:\t0x%08X\n", read32(reg+OHCI_HC_RH_DESCRIPTOR_A)); + printf("OHCI_HC_RH_DESCRIPTOR_B:\t0x%08X\n", read32(reg+OHCI_HC_RH_DESCRIPTOR_B)); + printf("OHCI_HC_RH_STATUS:\t\t0x%08X\n", read32(reg+OHCI_HC_RH_STATUS)); + printf("OHCI_HC_RH_PORT_STATUS_1:\t0x%08X\n", read32(reg+OHCI_HC_RH_PORT_STATUS_1)); + printf("OHCI_HC_RH_PORT_STATUS_2:\t0x%08X\n", read32(reg+OHCI_HC_RH_PORT_STATUS_2)); +#endif + + setup_port(reg, reg+OHCI_HC_RH_PORT_STATUS_1, from_init); + setup_port(reg, reg+OHCI_HC_RH_PORT_STATUS_2, from_init); +#ifdef _DU_OHCI_RH printf("configure_ports done\n"); +#endif } -static void setup_port(u32 reg, u8 from_init) +static void setup_port(u32 ohci, u32 reg, u8 from_init) { u32 port = read32(reg); if((port & RH_PS_CCS) && ((port & RH_PS_CSC) || from_init)) { @@ -464,7 +465,9 @@ static void setup_port(u32 reg, u8 from_init) /* clear CSC flag, set PES and start port reset (PRS) */ write32(reg, RH_PS_PES); while(!(read32(reg) & RH_PS_PES)) { +#ifdef _DU_OHCI_RH printf("fu\n"); +#endif return; } @@ -472,16 +475,19 @@ static void setup_port(u32 reg, u8 from_init) /* spin until port reset is complete */ while(!(read32(reg) & RH_PS_PRSC)); // hint: it may stuck here +#ifdef _DU_OHCI_RH printf("loop done\n"); +#endif - (void) usb_add_device(); + /* returns usb_device struct */ + (void) usb_add_device((read32(reg) & RH_PS_LSDA) >> 8, ohci); } } -void hcdi_irq() +void hcdi_irq(u32 reg) { /* read interrupt status */ - u32 flags = read32(OHCI0_HC_INT_STATUS); + u32 flags = read32(reg+OHCI_HC_INT_STATUS); /* when all bits are set to 1 some problem occured */ if (flags == 0xffffffff) { @@ -490,7 +496,7 @@ void hcdi_irq() } /* only care about interrupts that are enabled */ - flags &= read32(OHCI0_HC_INT_ENABLE); + flags &= read32(reg+OHCI_HC_INT_ENABLE); /* nothing to do? */ if (flags == 0) { @@ -510,13 +516,13 @@ void hcdi_irq() if (flags & OHCI_INTR_RHSC) { printf("RootHubStatusChange\n"); /* TODO: set some next_statechange variable... */ - configure_ports(0); - write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD | OHCI_INTR_RHSC); + configure_ports(0, reg); + write32(reg+OHCI_HC_INT_STATUS, OHCI_INTR_RD | OHCI_INTR_RHSC); } /* ResumeDetected */ else if (flags & OHCI_INTR_RD) { printf("ResumeDetected\n"); - write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD); + write32(reg+OHCI_HC_INT_STATUS, OHCI_INTR_RD); /* TODO: figure out what the linux kernel does here... */ } @@ -540,13 +546,23 @@ void hcdi_irq() #define HC_IS_RUNNING() 1 /* dirty, i know... just a temporary solution */ if (HC_IS_RUNNING()) { - write32(OHCI0_HC_INT_STATUS, flags); - write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_MIE); + write32(reg+OHCI_HC_INT_STATUS, flags); + write32(reg+OHCI_HC_INT_ENABLE, OHCI_INTR_MIE); + } +} + +/* Before you access the HCCA structure in any way, call this to set the pointer correctly! */ +static void set_target_hcca(u32 reg) +{ + switch(reg) { + case OHCI0_REG_BASE: hcca = &hcca_oh0; break; + case OHCI1_REG_BASE: hcca = &hcca_oh1; break; } } -void show_frame_no() +void show_frame_no(u32 reg) { - sync_before_read(&hcca_oh0, 256); - printf("***** frame_no: %d *****\n", LE(hcca_oh0.frame_no)); + set_target_hcca(reg); + sync_before_read(hcca, 256); + printf("***** frame_no: %d *****\n", LE(hcca->frame_no)); }