X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=usb%2Fhost%2Fohci.c;h=74430ea1c4359d90c1a418decc47ab6a2d0ffa6e;hb=0a6c9cd0c045cc9481147531a8e3cc08aef20a98;hp=0dea4b1773791dfb5828ec7a516fda79e3582a4c;hpb=e3850e3c60ac379edf9d6fad436eeeca5718aa3a;p=ppcskel.git diff --git a/usb/host/ohci.c b/usb/host/ohci.c index 0dea4b1..74430ea 100644 --- a/usb/host/ohci.c +++ b/usb/host/ohci.c @@ -16,34 +16,124 @@ Copyright (C) 2009 Sebastian Falbesoner #include "../../malloc.h" #include "ohci.h" #include "host.h" +#include "../usbspec/usb11spec.h" + +/* macro for accessing u32 variables that need to be in little endian byte order; + * + * whenever you read or write from an u32 field that the ohci host controller + * will read or write from too, use this macro for access! + */ +#define LE(dword) (u32)( (((dword) & 0xFF000000) >> 24) | \ + (((dword) & 0x00FF0000) >> 8) | \ + (((dword) & 0x0000FF00) << 8) | \ + (((dword) & 0x000000FF) << 24) ) + +static struct endpoint_descriptor *allocate_endpoint(); +static struct general_td *allocate_general_td(); +static void control_quirk(); +static void dbg_op_state(); +//static void dbg_td_flag(u32 flag); +static void configure_ports(u8 from_init); +static void setup_port(u32 reg, u8 from_init); static struct ohci_hcca hcca_oh0; -static struct endpoint_descriptor *dummyconfig; + static struct endpoint_descriptor *allocate_endpoint() { struct endpoint_descriptor *ep; - ep = (struct endpoint_descriptor *)calloc(sizeof(struct endpoint_descriptor), 16); - ep->flags = OHCI_ENDPOINT_GENERAL_FORMAT; - ep->headp = ep->tailp = ep->nexted = 0; + ep = (struct endpoint_descriptor *)memalign(16, sizeof(struct endpoint_descriptor)); + ep->flags = LE(OHCI_ENDPOINT_GENERAL_FORMAT); + ep->headp = ep->tailp = ep->nexted = LE(0); return ep; } -static struct general_td *allocate_general_td(size_t bsize) +static struct general_td *allocate_general_td() { struct general_td *td; - td = (struct general_td *)calloc(sizeof(struct general_td), 16); - td->flags = 0; - td->nexttd = 0; - if(bsize == 0) { - td->cbp = td->be = 0; + td = (struct general_td *)memalign(16, sizeof(struct general_td)); + td->flags = LE(0); + td->nexttd = LE(0); + td->cbp = td->be = LE(0); + return td; +} + +static void control_quirk() +{ + static struct endpoint_descriptor *ed = 0; /* empty ED */ + static struct general_td *td = 0; /* dummy TD */ + u32 head; + u32 current; + u32 status; + + /* + * One time only. + * Allocate and keep a special empty ED with just a dummy TD. + */ + if (!ed) { + ed = allocate_endpoint(); + if (!ed) + return; + + td = allocate_general_td(0); + if (!td) { + free(ed); + ed = NULL; + return; + } + +#define ED_MASK ((u32)~0x0f) + ed->tailp = ed->headp = LE(virt_to_phys((void*) ((u32)td & ED_MASK))); + ed->flags |= LE(OHCI_ENDPOINT_DIRECTION_OUT); + } + + /* + * The OHCI USB host controllers on the Nintendo Wii + * video game console stop working when new TDs are + * added to a scheduled control ED after a transfer has + * has taken place on it. + * + * Before scheduling any new control TD, we make the + * controller happy by always loading a special control ED + * with a single dummy TD and letting the controller attempt + * the transfer. + * The controller won't do anything with it, as the special + * ED has no TDs, but it will keep the controller from failing + * on the next transfer. + */ + head = read32(OHCI0_HC_CTRL_HEAD_ED); + if (head) { + printf("head: 0x%08X\n", head); + /* + * Load the special empty ED and tell the controller to + * process the control list. + */ + sync_after_write(ed, 16); + sync_after_write(td, 16); + write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(ed)); + + status = read32(OHCI0_HC_CONTROL); + set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE); + write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF); + + /* spin until the controller is done with the control list */ + current = read32(OHCI0_HC_CTRL_CURRENT_ED); + while(!current) { + udelay(10); + current = read32(OHCI0_HC_CTRL_CURRENT_ED); + } + + printf("current: 0x%08X\n", current); + + /* restore the old control head and control settings */ + write32(OHCI0_HC_CONTROL, status); + write32(OHCI0_HC_CTRL_HEAD_ED, head); } else { - td->cbp = (u32)malloc(bsize); - td->be = td->cbp + bsize - 1; + printf("nohead!\n"); } - return td; } + static void dbg_op_state() { switch (read32(OHCI0_HC_CONTROL) & OHCI_CTRL_HCFS) { @@ -62,53 +152,185 @@ static void dbg_op_state() } } +#if 0 +static void dbg_td_flag(u32 flag) +{ + printf("**************** dbg_td_flag: 0x%08X ***************\n", flag); + printf("CC: %X\tshould be 0, see page 32 (ohci spec)\n", (flag>>28)&0xf); + printf("EC: %X\tsee page 20 (ohci spec)\n", (flag>>26)&3); + printf(" T: %X\n", (flag>>24)&3); + printf("DI: %X\n", (flag>>21)&7); + printf("DP: %X\n", (flag>>19)&3); + printf(" R: %X\n", (flag>>18)&1); + printf("********************************************************\n"); +} +#endif + +static void general_td_fill(struct general_td *dest, const usb_transfer_descriptor *src) +{ + dest->bufaddr = dest->cbp = LE(virt_to_phys(src->buffer)); + dest->be = src->actlen ? LE(LE(dest->cbp) + src->actlen - 1) : LE(0); + dest->flags &= LE(~OHCI_TD_DIRECTION_PID_MASK); + dest->buflen = src->actlen; + + switch(src->pid) { + case USB_PID_SETUP: + printf("pid_setup\n"); + dest->flags |= LE(OHCI_TD_DIRECTION_PID_SETUP); + dest->flags |= LE(OHCI_TD_TOGGLE_0); + dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING); + break; + case USB_PID_OUT: + printf("pid_out\n"); + dest->flags |= LE(OHCI_TD_DIRECTION_PID_OUT); + dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING); + + /* + * TODO: just temporary solution! (consider it with len?) + * there can be also regular PID_OUT pakets + */ + dest->flags |= LE(OHCI_TD_TOGGLE_1); + break; + case USB_PID_IN: + printf("pid_in\n"); + dest->flags |= LE(OHCI_TD_DIRECTION_PID_IN); + dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING); + /* + * let the endpoint do the togglestuff! + * TODO: just temporary solution! + * there can be also inregular PID_IN pakets (@Status Stage) + */ + dest->flags |= LE(OHCI_TD_TOGGLE_CARRY); +#if 0 + /* should be done by HC! + * first pid_in start with DATA0 */ + */ + dummyconfig.headp = LE( src->togl ? + LE(dummyconfig.headp) | OHCI_ENDPOINT_TOGGLE_CARRY : + LE(dummyconfig.headp) & ~OHCI_ENDPOINT_TOGGLE_CARRY); +#endif + break; + } + dest->flags |= LE(OHCI_TD_SET_DELAY_INTERRUPT(7)); +#if 1 + // not necessary here anymore? + sync_after_write(dest, sizeof(struct general_td)); + sync_after_write((void*) phys_to_virt(LE(dest->cbp)), src->actlen); +#endif +} + +static void dump_address(void *addr, u32 size, const char* str) +{ + sync_before_read(addr, size); + printf("%s hexdump @ 0x%08X:\n", str, addr); + hexdump(addr, size); +} + +struct endpoint_descriptor *edhead = 0; +void hcdi_fire() +{ + printf("<^> <^> <^> hcdi_fire(start)\n"); + + control_quirk(); //required? YES! :O ... erm... or no? :/ ... in fact I have no idea + + /* sync it all */ + sync_after_write(edhead, sizeof(struct endpoint_descriptor)); + dump_address(edhead, sizeof(struct endpoint_descriptor), "edhead(before)"); + + struct general_td *x = phys_to_virt(LE(edhead->headp)); + while(virt_to_phys(x)) { + sync_after_write(x, sizeof(struct general_td)); + dump_address(x, sizeof(struct general_td), "x(before)"); + + if(x->buflen > 0) { + sync_after_write((void*) x->cbp, x->buflen); + dump_address((void*) phys_to_virt(LE(x->cbp)), x->buflen, "x->cbp(before)"); + } + x = phys_to_virt(LE(x->nexttd)); + } + + /* trigger control list */ + u32 wait=0; + set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE); + write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF); + + //don't use this quirk stuff here!? +#if 1 + while(!read32(OHCI0_HC_CTRL_CURRENT_ED)) { + } +#endif + printf("+++++++++++++++++++++++++++++\n"); + printf("wait: %d\n", wait); + udelay(100000); + + sync_before_read(&hcca_oh0, sizeof(hcca_oh0)); + struct general_td *n = phys_to_virt(LE(hcca_oh0.done_head)); + printf("done_head: 0x%08X\n", n); +#if 0 + struct general_td *prev = 0; + while(n) { + if(prev) { + free(prev); + } + sync_before_read((void*) n, sizeof(struct general_td)); + dump_address(n, sizeof(struct general_td), "n(after)"); + dump_address((void*) phys_to_virt(LE(n->cbp)), n->buflen, "n->cbp(after)"); + dump_address((void*) n->bufaddr, n->buflen, "n->bufaddr(after)"); + dbg_td_flag(LE(n->flags)); + n = prev = phys_to_virt(LE(n->nexttd)); + } + hcca_oh0.done_head = 0; + sync_after_write(&hcca_oh0, sizeof(hcca_oh0)); +#endif + + write32(OHCI0_HC_CONTROL, read32(OHCI0_HC_CONTROL)&~OHCI_CTRL_CLE); + +// free(edhead); + + edhead = 0; + printf("<^> <^> <^> hcdi_fire(end)\n"); +} /** * Enqueue a transfer descriptor. */ -u8 hcdi_enqueue(usb_transfer_descriptor *td) { - printf("===========================\ndone head (vor sync): 0x%08X\n", hcca_oh0.done_head); - sync_before_read(&hcca_oh0, 256); - printf("done head (nach sync): 0x%08X\n", hcca_oh0.done_head); - - struct general_td *tmptd = allocate_general_td(sizeof(td->buffer)); - (void) memcpy((void*) tmptd->cbp, td->buffer, sizeof(td->buffer)); - - printf("tmptd hexump (before):\n"); - hexdump((void*) tmptd, sizeof(tmptd)); - printf("tmptd-cbp hexump (before):\n"); - hexdump((void*) (tmptd->cbp), sizeof(tmptd->cbp)); +u8 hcdi_enqueue(const usb_transfer_descriptor *td) { + printf("*()*()*()*()*()*()*() hcdi_enqueue(start)\n"); + if(!edhead) { + edhead = allocate_endpoint(); + edhead->flags = LE(OHCI_ENDPOINT_GENERAL_FORMAT); + edhead->headp = edhead->tailp = edhead->nexted = LE(0); + edhead->flags |= LE(OHCI_ENDPOINT_LOW_SPEED | + OHCI_ENDPOINT_SET_DEVICE_ADDRESS(td->devaddress) | + OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(td->endpoint) | + OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(td->maxp)); + write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(edhead)); + } - sync_after_write((void*) (tmptd->cbp), sizeof(tmptd->cbp)); - sync_after_write(tmptd, sizeof(tmptd)); + struct general_td *tdhw = allocate_general_td(); + general_td_fill(tdhw, td); - dummyconfig->headp = virt_to_phys(tmptd); - sync_after_write(dummyconfig, 64); +#define ED_MASK ((u32)~0x0f) + if(!edhead->headp) { + /* first transfer */ + edhead->headp = LE(virt_to_phys((void*) ((u32)tdhw & ED_MASK))); + } + else { + /* headp in endpoint already exists + * => get to list end + */ + struct general_td *n = (struct general_td*) phys_to_virt(LE(edhead->headp)); + while(LE(n->nexttd)) { + n = phys_to_virt(LE(n->nexttd)); + } + n->nexttd = LE(virt_to_phys((void*) ((u32)tdhw & ED_MASK))); + } - printf("+++++++++++++++++++++++++++++\n"); - udelay(2000); - udelay(2000); - udelay(2000); - udelay(2000); - udelay(2000); - udelay(2000); - udelay(2000); - udelay(2000); - - sync_before_read(tmptd, sizeof(tmptd)); - printf("tmptd hexump (after):\n"); - hexdump((void*) tmptd, sizeof(tmptd)); - - sync_before_read((void*) (tmptd->cbp), sizeof(tmptd->cbp)); - printf("tmptd-cbp hexump (after):\n"); - hexdump((void*) (tmptd->cbp), sizeof(tmptd->cbp)); - - printf("done head (vor sync): 0x%08X\n", hcca_oh0.done_head); - sync_before_read(&hcca_oh0, 256); - printf("done head (nach sync): 0x%08X\n", hcca_oh0.done_head); + printf("*()*()*()*()*()*()*() hcdi_enqueue(end)\n"); return 0; } + /** * Remove an transfer descriptor from transfer queue. */ @@ -118,7 +340,6 @@ u8 hcdi_dequeue(usb_transfer_descriptor *td) { void hcdi_init() { - dummyconfig = allocate_endpoint(); printf("ohci-- init\n"); dbg_op_state(); @@ -157,8 +378,7 @@ void hcdi_init() /* Tell the controller where the control and bulk lists are * The lists are empty now. */ - sync_after_write(dummyconfig, 64); - write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(dummyconfig)); + write32(OHCI0_HC_CTRL_HEAD_ED, 0); write32(OHCI0_HC_BULK_HEAD_ED, 0); /* set hcca adress */ @@ -182,17 +402,59 @@ void hcdi_init() write32(OHCI0_HC_CONTROL, OHCI_CONTROL_INIT | OHCI_USB_OPER); /* wake on ConnectStatusChange, matching external hubs */ - set32(OHCI0_HC_RH_STATUS, RH_HS_DRWE); + write32(OHCI0_HC_RH_STATUS, /*RH_HS_DRWE |*/ RH_HS_LPSC); /* Choose the interrupts we care about now, others later on demand */ write32(OHCI0_HC_INT_STATUS, ~0); write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_INIT); + //wtf? + wait_ms ((read32(OHCI0_HC_RH_DESCRIPTOR_A) >> 23) & 0x1fe); + + configure_ports((u8)1); irq_restore(cookie); dbg_op_state(); } +static void configure_ports(u8 from_init) +{ + printf("OHCI0_HC_RH_DESCRIPTOR_A:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_A)); + printf("OHCI0_HC_RH_DESCRIPTOR_B:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_B)); + printf("OHCI0_HC_RH_STATUS:\t\t0x%08X\n", read32(OHCI0_HC_RH_STATUS)); + printf("OHCI0_HC_RH_PORT_STATUS_1:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_1)); + printf("OHCI0_HC_RH_PORT_STATUS_2:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_2)); + + setup_port(OHCI0_HC_RH_PORT_STATUS_1, from_init); + setup_port(OHCI0_HC_RH_PORT_STATUS_2, from_init); + printf("configure_ports done\n"); +} + +static void setup_port(u32 reg, u8 from_init) +{ + u32 port = read32(reg); + if((port & RH_PS_CCS) && ((port & RH_PS_CSC) || from_init)) { + write32(reg, RH_PS_CSC); + + wait_ms(120); + + /* clear CSC flag, set PES and start port reset (PRS) */ + write32(reg, RH_PS_PES); + while(!(read32(reg) & RH_PS_PES)) { + printf("fu\n"); + return; + } + + write32(reg, RH_PS_PRS); + + /* spin until port reset is complete */ + while(!(read32(reg) & RH_PS_PRSC)); // hint: it may stuck here + printf("loop done\n"); + + (void) usb_add_device(); + } +} + void hcdi_irq() { /* read interrupt status */ @@ -208,8 +470,10 @@ void hcdi_irq() flags &= read32(OHCI0_HC_INT_ENABLE); /* nothing to do? */ - if (flags == 0) + if (flags == 0) { + printf("OHCI Interrupt occured: but not for you! WTF?!\n"); return; + } printf("OHCI Interrupt occured: "); /* UnrecoverableError */ @@ -223,6 +487,7 @@ void hcdi_irq() if (flags & OHCI_INTR_RHSC) { printf("RootHubStatusChange\n"); /* TODO: set some next_statechange variable... */ + configure_ports(0); write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD | OHCI_INTR_RHSC); } /* ResumeDetected */ @@ -235,7 +500,17 @@ void hcdi_irq() /* WritebackDoneHead */ if (flags & OHCI_INTR_WDH) { printf("WritebackDoneHead\n"); - /* TODO: figure out what the linux kernel does here... */ + /* basically the linux irq handler reverse TDs to their urbs + * and set done_head to null. + * since we are polling atm, just should do the latter task. + * however, this won't work for now (i don't know why...) + * TODO! + */ +#if 0 + sync_before_read(&hcca_oh0, 256); + hcca_oh0.done_head = 0; + sync_after_write(&hcca_oh0, 256); +#endif } /* TODO: handle any pending URB/ED unlinks... */ @@ -247,3 +522,8 @@ void hcdi_irq() } } +void show_frame_no() +{ + sync_before_read(&hcca_oh0, 256); + printf("***** frame_no: %d *****\n", LE(hcca_oh0.frame_no)); +}