X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fvm%2Fjit%2Fx86_64%2Fcodegen.h;h=4fa215d54d72f7cd4fed04f964900501a2edda81;hb=d1377204f560df4d6656f58914bc4d242193c5e0;hp=1be675c64c74d448e9f60a1a34290e087eeea67b;hpb=9485802e10eaa8799469d3e1b27269c6e6f6877f;p=cacao.git diff --git a/src/vm/jit/x86_64/codegen.h b/src/vm/jit/x86_64/codegen.h index 1be675c64..4fa215d54 100644 --- a/src/vm/jit/x86_64/codegen.h +++ b/src/vm/jit/x86_64/codegen.h @@ -1,9 +1,7 @@ /* src/vm/jit/x86_64/codegen.h - code generation macros for x86_64 - Copyright (C) 1996-2005, 2006 R. Grafl, A. Krall, C. Kruegel, - C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring, - E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich, - J. Wenninger, Institut f. Computersprachen - TU Wien + Copyright (C) 1996-2005, 2006, 2007, 2008, 2009 + CACAOVM - Verein zur Foerderung der freien virtuellen Maschine CACAO This file is part of CACAO. @@ -22,15 +20,6 @@ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - Contact: cacao@cacaojvm.org - - Authors: Andreas Krall - Christian Thalinger - - Changes: - - $Id: codegen.h 4941 2006-05-23 08:25:14Z twisti $ - */ @@ -43,57 +32,13 @@ #include "vm/types.h" -#include "vm/jit/jit.h" - - -/* some defines ***************************************************************/ +#include "vm/jit/x86_64/emit.h" -#define PATCHER_CALL_SIZE 5 /* size in bytes of a patcher call */ +#include "vm/jit/jit.hpp" /* additional functions and macros to generate code ***************************/ -#define CALCOFFSETBYTES(var, reg, val) \ - if ((s4) (val) < -128 || (s4) (val) > 127) (var) += 4; \ - else if ((s4) (val) != 0) (var) += 1; \ - else if ((reg) == RBP || (reg) == RSP || (reg) == R12 || (reg) == R13) (var) += 1; - - -#define CALCIMMEDIATEBYTES(var, val) \ - if ((s4) (val) < -128 || (s4) (val) > 127) (var) += 4; \ - else (var) += 1; - - -/* gen_nullptr_check(objreg) */ - -#define gen_nullptr_check(objreg) \ - if (checknull) { \ - M_TEST(objreg); \ - M_BEQ(0); \ - codegen_add_nullpointerexception_ref(cd); \ - } - - -#define gen_bound_check \ - if (checkbounds) { \ - M_ICMP_MEMBASE(s1, OFFSET(java_arrayheader, size), s2); \ - M_BAE(0); \ - codegen_add_arrayindexoutofboundsexception_ref(cd, s2); \ - } - - -#define gen_div_check(v) \ - if (checknull) { \ - if ((v)->flags & INMEMORY) { \ - M_CMP_IMM_MEMBASE(0, REG_SP, src->regoff * 8); \ - } else { \ - M_TEST(src->regoff); \ - } \ - M_BEQ(0); \ - codegen_add_arithmeticexception_ref(cd); \ - } - - /* MCODECHECK(icnt) */ #define MCODECHECK(icnt) \ @@ -104,61 +49,75 @@ #define ALIGNCODENOP \ - if ((s4) (((ptrint) cd->mcodeptr) & 7)) { \ - M_NOP; \ - } + do { \ + int len = (-(ptrint) cd->mcodeptr) & 7; \ + if (len) \ + emit_nop(cd, len); \ + } while (0) + +#define ICONST(r,c) \ + do { \ + if ((c) == 0) \ + M_CLR((d)); \ + else \ + M_IMOV_IMM((c), (d)); \ + } while (0) +/* do { \ */ +/* M_IMOV_IMM((c), (d)); \ */ +/* } while (0) */ -/* M_INTMOVE: - generates an integer-move from register a to b. - if a and b are the same int-register, no code will be generated. -*/ -#define M_INTMOVE(reg,dreg) \ +#define LCONST(r,c) \ do { \ - if ((reg) != (dreg)) { \ - M_MOV(reg, dreg); \ - } \ + if ((c) == 0) \ + M_CLR((d)); \ + else \ + M_MOV_IMM((c), (d)); \ } while (0) -/* M_FLTMOVE: - generates a floating-point-move from register a to b. - if a and b are the same float-register, no code will be generated -*/ +/* branch defines *************************************************************/ -#define M_FLTMOVE(reg,dreg) \ +#define BRANCH_UNCONDITIONAL_SIZE 5 /* size in bytes of a branch */ +#define BRANCH_CONDITIONAL_SIZE 6 /* size in bytes of a branch */ + +#define BRANCH_NOPS \ do { \ - if ((reg) != (dreg)) { \ - M_FMOV(reg, dreg); \ - } \ + M_NOP; \ + M_NOP; \ + M_NOP; \ + M_NOP; \ + M_NOP; \ + M_NOP; \ } while (0) -#define M_COPY(s,d) emit_copy(jd, iptr, (s), (d)) +/* patcher defines ************************************************************/ -#define ICONST(r,c) \ +#define PATCHER_CALL_SIZE 2 /* size in bytes of a patcher call */ + +#define PATCHER_NOPS \ do { \ - if (iptr->val.i == 0) \ - M_CLR(d); \ - else \ - M_IMOV_IMM(iptr->val.i, d); \ + emit_nop(cd, 2); \ } while (0) -/* do { \ */ -/* M_IMOV_IMM(iptr->val.i, d); \ */ -/* } while (0) */ -#define LCONST(r,c) \ +/* macros to create code ******************************************************/ + +#define M_BYTE1(a) \ do { \ - if (iptr->val.l == 0) \ - M_CLR(d); \ - else \ - M_MOV_IMM(iptr->val.l, d); \ + *(cd->mcodeptr) = (a); \ + cd->mcodeptr++; \ } while (0) -/* macros to create code ******************************************************/ +#define M_BYTE2(a, b) \ + do { \ + M_BYTE1(a); \ + M_BYTE1(b); \ + } while (0) + #define M_MOV(a,b) emit_mov_reg_reg(cd, (a), (b)) #define M_MOV_IMM(a,b) emit_mov_imm_reg(cd, (u8) (a), (b)) @@ -167,6 +126,7 @@ #define M_IMOV_IMM(a,b) emit_movl_imm_reg(cd, (u4) (a), (b)) #define M_FMOV(a,b) emit_movq_reg_reg(cd, (a), (b)) +#define M_DMOV(a,b) M_FMOV(a,b) #define M_ILD(a,b,disp) emit_movl_membase_reg(cd, (b), (disp), (a)) #define M_LLD(a,b,disp) emit_mov_membase_reg(cd, (b), (disp), (a)) @@ -187,22 +147,43 @@ #define M_LST32_IMM32(a,b,disp) emit_mov_imm_membase32(cd, (a), (b), (disp)) #define M_IADD(a,b) emit_alul_reg_reg(cd, ALU_ADD, (a), (b)) -#define M_IADD_IMM(a,b) emit_alul_reg_reg(cd, ALU_ADD, (a), (b)) +#define M_ISUB(a,b) emit_alul_reg_reg(cd, ALU_SUB, (a), (b)) +#define M_IMUL(a,b) emit_imull_reg_reg(cd, (a), (b)) + +#define M_IADD_IMM(a,b) emit_alul_imm_reg(cd, ALU_ADD, (a), (b)) +#define M_ISUB_IMM(a,b) emit_alul_imm_reg(cd, ALU_SUB, (a), (b)) +#define M_IMUL_IMM(a,b,c) emit_imull_imm_reg_reg(cd, (b), (a), (c)) #define M_LADD(a,b) emit_alu_reg_reg(cd, ALU_ADD, (a), (b)) -#define M_LADD_IMM(a,b) emit_alu_imm_reg(cd, ALU_ADD, (a), (b)) #define M_LSUB(a,b) emit_alu_reg_reg(cd, ALU_SUB, (a), (b)) +#define M_LMUL(a,b) emit_imul_reg_reg(cd, (a), (b)) + +#define M_LADD_IMM(a,b) emit_alu_imm_reg(cd, ALU_ADD, (a), (b)) #define M_LSUB_IMM(a,b) emit_alu_imm_reg(cd, ALU_SUB, (a), (b)) +#define M_LMUL_IMM(a,b,c) emit_imul_imm_reg_reg(cd, (b), (a), (c)) -#define M_IINC_MEMBASE(a,b) emit_incl_membase(cd, (a), (b)) +#define M_IINC(a) emit_incl_reg(cd, (a)) +#define M_LINC(a) emit_incq_reg(cd, (a)) +#define M_IDEC(a) emit_decl_reg(cd, (a)) -#define M_IADD_MEMBASE(a,b,c) emit_alul_reg_membase(cd, ALU_ADD, (a), (b), (c)) -#define M_IADC_MEMBASE(a,b,c) emit_alul_reg_membase(cd, ALU_ADC, (a), (b), (c)) -#define M_ISUB_MEMBASE(a,b,c) emit_alul_reg_membase(cd, ALU_SUB, (a), (b), (c)) -#define M_ISBB_MEMBASE(a,b,c) emit_alul_reg_membase(cd, ALU_SBB, (a), (b), (c)) +#define M_ALD(a,b,disp) \ + do { \ + if (b == RIP) \ + M_LLD(a, b, disp + -((cd->mcodeptr + 7) - cd->mcodebase)); \ + else \ + M_LLD(a, b, disp); \ + } while (0) -#define M_ALD(a,b,disp) M_LLD(a,b,disp) #define M_ALD32(a,b,disp) M_LLD32(a,b,disp) +#define M_ALD_DSEG(a,disp) M_ALD(a,RIP,disp) + +#define M_ALD_MEM(a,disp) emit_mov_mem_reg(cd, (disp), (a)) + +#define M_ALD_MEM_GET_OPC(p) ( *( (p) + 1)) +#define M_ALD_MEM_GET_MOD(p) (((*( (p) + 2)) >> 6) & 0x03) +#define M_ALD_MEM_GET_REG(p) ((((*( (p) + 2)) >> 3) & 0x07) + (((*(p) >> 2) & 0x01) << 3)) +#define M_ALD_MEM_GET_RM(p) (((*( (p) + 2)) ) & 0x07) +#define M_ALD_MEM_GET_DISP(p) ( *((u4 *) ((p) + 4))) #define M_AST(a,b,c) M_LST(a,b,c) #define M_AST_IMM32(a,b,c) M_LST_IMM32(a,b,c) @@ -211,10 +192,13 @@ #define M_AADD_IMM(a,b) M_LADD_IMM(a,b) #define M_ASUB_IMM(a,b) M_LSUB_IMM(a,b) +#define M_ISUB_IMM32(a,b) emit_alul_imm32_reg(cd, ALU_SUB, (a), (b)) + #define M_LADD_IMM32(a,b) emit_alu_imm32_reg(cd, ALU_ADD, (a), (b)) -#define M_AADD_IMM32(a,b) M_LADD_IMM32(a,b) #define M_LSUB_IMM32(a,b) emit_alu_imm32_reg(cd, ALU_SUB, (a), (b)) +#define M_AADD_IMM32(a,b) M_LADD_IMM32(a,b) + #define M_ILEA(a,b,c) emit_leal_membase_reg(cd, (a), (b), (c)) #define M_LLEA(a,b,c) emit_lea_membase_reg(cd, (a), (b), (c)) #define M_ALEA(a,b,c) M_LLEA(a,b,c) @@ -222,47 +206,70 @@ #define M_INEG(a) emit_negl_reg(cd, (a)) #define M_LNEG(a) emit_neg_reg(cd, (a)) -#define M_INEG_MEMBASE(a,b) emit_negl_membase(cd, (a), (b)) -#define M_LNEG_MEMBASE(a,b) emit_neg_membase(cd, (a), (b)) - -#define M_AND(a,b) emit_alu_reg_reg(cd, ALU_AND, (a), (b)) -#define M_XOR(a,b) emit_alu_reg_reg(cd, ALU_XOR, (a), (b)) - #define M_IAND(a,b) emit_alul_reg_reg(cd, ALU_AND, (a), (b)) -#define M_IAND_IMM(a,b) emit_alul_imm_reg(cd, ALU_AND, (a), (b)) +#define M_IOR(a,b) emit_alul_reg_reg(cd, ALU_OR, (a), (b)) #define M_IXOR(a,b) emit_alul_reg_reg(cd, ALU_XOR, (a), (b)) +#define M_IAND_IMM(a,b) emit_alul_imm_reg(cd, ALU_AND, (a), (b)) +#define M_IOR_IMM(a,b) emit_alul_imm_reg(cd, ALU_OR, (a), (b)) +#define M_IXOR_IMM(a,b) emit_alul_imm_reg(cd, ALU_XOR, (a), (b)) + +#define M_LAND(a,b) emit_alu_reg_reg(cd, ALU_AND, (a), (b)) +#define M_LOR(a,b) emit_alu_reg_reg(cd, ALU_OR, (a), (b)) +#define M_LXOR(a,b) emit_alu_reg_reg(cd, ALU_XOR, (a), (b)) + +#define M_LAND_IMM(a,b) emit_alu_imm_reg(cd, ALU_AND, (a), (b)) +#define M_LOR_IMM(a,b) emit_alu_imm_reg(cd, ALU_OR, (a), (b)) +#define M_LXOR_IMM(a,b) emit_alu_imm_reg(cd, ALU_XOR, (a), (b)) + #define M_BSEXT(a,b) emit_movsbq_reg_reg(cd, (a), (b)) #define M_SSEXT(a,b) emit_movswq_reg_reg(cd, (a), (b)) #define M_ISEXT(a,b) emit_movslq_reg_reg(cd, (a), (b)) +#define M_BZEXT(a,b) emit_movzbq_reg_reg(cd, (a), (b)) #define M_CZEXT(a,b) emit_movzwq_reg_reg(cd, (a), (b)) -#define M_BSEXT_MEMBASE(a,disp,b) emit_movsbq_membase_reg(cd, (a), (disp), (b)) -#define M_SSEXT_MEMBASE(a,disp,b) emit_movswq_membase_reg(cd, (a), (disp), (b)) -#define M_ISEXT_MEMBASE(a,disp,b) emit_movslq_membase_reg(cd, (a), (disp), (b)) +#define M_ISLL_IMM(a,b) emit_shiftl_imm_reg(cd, SHIFT_SHL, (a), (b)) +#define M_ISRA_IMM(a,b) emit_shiftl_imm_reg(cd, SHIFT_SAR, (a), (b)) +#define M_ISRL_IMM(a,b) emit_shiftl_imm_reg(cd, SHIFT_SHR, (a), (b)) -#define M_CZEXT_MEMBASE(a,disp,b) emit_movzwq_membase_reg(cd, (a), (disp), (b)) +#define M_LSLL_IMM(a,b) emit_shift_imm_reg(cd, SHIFT_SHL, (a), (b)) +#define M_LSRA_IMM(a,b) emit_shift_imm_reg(cd, SHIFT_SAR, (a), (b)) +#define M_LSRL_IMM(a,b) emit_shift_imm_reg(cd, SHIFT_SHR, (a), (b)) #define M_TEST(a) emit_test_reg_reg(cd, (a), (a)) #define M_ITEST(a) emit_testl_reg_reg(cd, (a), (a)) -#define M_CMP(a,b) emit_alu_reg_reg(cd, ALU_CMP, (a), (b)) -#define M_CMP_IMM(a,b) emit_alu_imm_reg(cd, ALU_CMP, (a), (b)) -#define M_CMP_IMM_MEMBASE(a,b,c) emit_alu_imm_membase(cd, ALU_CMP, (a), (b), (c)) -#define M_CMP_MEMBASE(a,b,c) emit_alu_membase_reg(cd, ALU_CMP, (a), (b), (c)) +#define M_LCMP(a,b) emit_alu_reg_reg(cd, ALU_CMP, (a), (b)) +#define M_LCMP_IMM(a,b) emit_alu_imm_reg(cd, ALU_CMP, (a), (b)) +#define M_LCMP_IMM_MEMBASE(a,b,c) emit_alu_imm_membase(cd, ALU_CMP, (a), (b), (c)) +#define M_LCMP_MEMBASE(a,b,c) emit_alu_membase_reg(cd, ALU_CMP, (a), (b), (c)) +#define M_LCMP_MEMINDEX(a,b,c,d,e) emit_alul_memindex_reg(cd, ALU_CMP, (b), (a), (c), (d), (e)) #define M_ICMP(a,b) emit_alul_reg_reg(cd, ALU_CMP, (a), (b)) #define M_ICMP_IMM(a,b) emit_alul_imm_reg(cd, ALU_CMP, (a), (b)) +#define M_ICMP_IMM32(a,b) emit_alul_imm32_reg(cd, ALU_CMP, (a), (b)) #define M_ICMP_IMM_MEMBASE(a,b,c) emit_alul_imm_membase(cd, ALU_CMP, (a), (b), (c)) #define M_ICMP_MEMBASE(a,b,c) emit_alul_membase_reg(cd, ALU_CMP, (a), (b), (c)) +#define M_ICMP_MEMINDEX(a,b,c,d,e) emit_alu_memindex_reg(cd, ALU_CMP, (b), (a), (c), (d), (e)) + +#define M_ACMP(a,b) M_LCMP(a,b) #define M_BEQ(disp) emit_jcc(cd, CC_E, (disp)) #define M_BNE(disp) emit_jcc(cd, CC_NE, (disp)) #define M_BLT(disp) emit_jcc(cd, CC_L, (disp)) #define M_BLE(disp) emit_jcc(cd, CC_LE, (disp)) -#define M_BAE(disp) emit_jcc(cd, CC_AE, (disp)) -#define M_BA(disp) emit_jcc(cd, CC_A, (disp)) +#define M_BGE(disp) emit_jcc(cd, CC_GE, (disp)) +#define M_BGT(disp) emit_jcc(cd, CC_G, (disp)) + +#define M_BULT(disp) emit_jcc(cd, CC_B, (disp)) +#define M_BULE(disp) emit_jcc(cd, CC_BE, (disp)) +#define M_BUGE(disp) emit_jcc(cd, CC_AE, (disp)) +#define M_BUGT(disp) emit_jcc(cd, CC_A, (disp)) + +#define M_SETE(a) emit_setcc_reg(cd, CC_E, (a)) +#define M_SETNE(a) emit_setcc_reg(cd, CC_NE, (a)) +#define M_SETULE(a) emit_setcc_reg(cd, CC_BE, (a)) #define M_CMOVEQ(a,b) emit_cmovcc_reg_reg(cd, CC_E, (a), (b)) #define M_CMOVNE(a,b) emit_cmovcc_reg_reg(cd, CC_NE, (a), (b)) @@ -271,15 +278,8 @@ #define M_CMOVGE(a,b) emit_cmovcc_reg_reg(cd, CC_GE, (a), (b)) #define M_CMOVGT(a,b) emit_cmovcc_reg_reg(cd, CC_G, (a), (b)) -#define M_CMOVEQ_MEMBASE(a,b,c) emit_cmovcc_reg_membase(cd, CC_E, (a), (b)) -#define M_CMOVNE_MEMBASE(a,b,c) emit_cmovcc_reg_membase(cd, CC_NE, (a), (b)) -#define M_CMOVLT_MEMBASE(a,b,c) emit_cmovcc_reg_membase(cd, CC_L, (a), (b)) -#define M_CMOVLE_MEMBASE(a,b,c) emit_cmovcc_reg_membase(cd, CC_LE, (a), (b)) -#define M_CMOVGE_MEMBASE(a,b,c) emit_cmovcc_reg_membase(cd, CC_GE, (a), (b)) -#define M_CMOVGT_MEMBASE(a,b,c) emit_cmovcc_reg_membase(cd, CC_G, (a), (b)) - -#define M_CMOVB(a,b) emit_cmovcc_reg_reg(cd, CC_B, (a), (b)) -#define M_CMOVA(a,b) emit_cmovcc_reg_reg(cd, CC_A, (a), (b)) +#define M_CMOVULT(a,b) emit_cmovcc_reg_reg(cd, CC_B, (a), (b)) +#define M_CMOVUGT(a,b) emit_cmovcc_reg_reg(cd, CC_A, (a), (b)) #define M_CMOVP(a,b) emit_cmovcc_reg_reg(cd, CC_P, (a), (b)) #define M_PUSH(a) emit_push_reg(cd, (a)) @@ -288,76 +288,64 @@ #define M_JMP(a) emit_jmp_reg(cd, (a)) #define M_JMP_IMM(a) emit_jmp_imm(cd, (a)) +#define M_JMP_IMM2(a) emit_jmp_imm2(cd, (a)) #define M_CALL(a) emit_call_reg(cd, (a)) #define M_CALL_IMM(a) emit_call_imm(cd, (a)) -#define M_RET emit_ret(cd) +#define M_RET M_BYTE1(0xc3) -#define M_NOP emit_nop(cd) +#define M_NOP M_BYTE1(0x90) +#define M_UD2 M_BYTE2(0x0f, 0x0b) -#define M_CLR(a) M_XOR(a,a) +#define M_CLR(a) M_LXOR(a,a) -#if 0 -#define M_FLD(a,b,c) emit_movlps_membase_reg(cd, (a), (b), (c)) -#define M_DLD(a,b,c) emit_movlpd_membase_reg(cd, (a), (b), (c)) +#define M_FLD(a,b,disp) emit_movss_membase_reg(cd, (b), (disp), (a)) +#define M_DLD(a,b,disp) emit_movsd_membase_reg(cd, (b), (disp), (a)) -#define M_FST(a,b,c) emit_movlps_reg_membase(cd, (a), (b), (c)) -#define M_DST(a,b,c) emit_movlpd_reg_membase(cd, (a), (b), (c)) -#endif +#define M_FLD32(a,b,disp) emit_movss_membase32_reg(cd, (b), (disp), (a)) +#define M_DLD32(a,b,disp) emit_movsd_membase32_reg(cd, (b), (disp), (a)) -#define M_DLD(a,b,disp) emit_movq_membase_reg(cd, (b), (disp), (a)) -#define M_DST(a,b,disp) emit_movq_reg_membase(cd, (a), (b), (disp)) +#define M_FST(a,b,disp) emit_movss_reg_membase(cd, (a), (b), (disp)) +#define M_DST(a,b,disp) emit_movsd_reg_membase(cd, (a), (b), (disp)) +#define M_FST32(a,b,disp) emit_movss_reg_membase32(cd, (a), (b), (disp)) +#define M_DST32(a,b,disp) emit_movsd_reg_membase32(cd, (a), (b), (disp)) -/* system instructions ********************************************************/ +#define M_FADD(a,b) emit_addss_reg_reg(cd, (a), (b)) +#define M_DADD(a,b) emit_addsd_reg_reg(cd, (a), (b)) +#define M_FSUB(a,b) emit_subss_reg_reg(cd, (a), (b)) +#define M_DSUB(a,b) emit_subsd_reg_reg(cd, (a), (b)) +#define M_FMUL(a,b) emit_mulss_reg_reg(cd, (a), (b)) +#define M_DMUL(a,b) emit_mulsd_reg_reg(cd, (a), (b)) +#define M_FDIV(a,b) emit_divss_reg_reg(cd, (a), (b)) +#define M_DDIV(a,b) emit_divsd_reg_reg(cd, (a), (b)) -#define M_RDTSC emit_rdtsc(cd) +#define M_CVTIF(a,b) emit_cvtsi2ss_reg_reg(cd, (a), (b)) +#define M_CVTID(a,b) emit_cvtsi2sd_reg_reg(cd, (a), (b)) +#define M_CVTLF(a,b) emit_cvtsi2ssq_reg_reg(cd, (a), (b)) +#define M_CVTLD(a,b) emit_cvtsi2sdq_reg_reg(cd, (a), (b)) +#define M_CVTFI(a,b) emit_cvttss2si_reg_reg(cd, (a), (b)) +#define M_CVTDI(a,b) emit_cvttsd2si_reg_reg(cd, (a), (b)) +#define M_CVTFL(a,b) emit_cvttss2siq_reg_reg(cd, (a), (b)) +#define M_CVTDL(a,b) emit_cvttsd2siq_reg_reg(cd, (a), (b)) -#define PROFILE_CYCLE_START \ - do { \ - if (opt_prof) { \ - M_PUSH(RAX); \ - M_PUSH(RDX); \ - \ - M_MOV_IMM((ptrint) m, REG_ITMP3); \ - M_RDTSC; \ - M_ISUB_MEMBASE(RAX, REG_ITMP3, OFFSET(methodinfo, cycles)); \ - M_ISBB_MEMBASE(RDX, REG_ITMP3, OFFSET(methodinfo, cycles) + 4); \ - \ - M_POP(RDX); \ - M_POP(RAX); \ - } \ - } while (0) - -#define PROFILE_CYCLE_STOP \ - do { \ - if (opt_prof) { \ - M_PUSH(RAX); \ - M_PUSH(RDX); \ - \ - M_MOV_IMM((ptrint) m, REG_ITMP3); \ - M_RDTSC; \ - M_IADD_MEMBASE(RAX, REG_ITMP3, OFFSET(methodinfo, cycles)); \ - M_IADC_MEMBASE(RDX, REG_ITMP3, OFFSET(methodinfo, cycles) + 4); \ - \ - M_POP(RDX); \ - M_POP(RAX); \ - } \ - } while (0) +#define M_CVTFD(a,b) emit_cvtss2sd_reg_reg(cd, (a), (b)) +#define M_CVTDF(a,b) emit_cvtsd2ss_reg_reg(cd, (a), (b)) -/* function gen_resolvebranch ************************************************** +/* system instructions ********************************************************/ - backpatches a branch instruction +#define M_MFENCE emit_mfence(cd) +#define M_RDTSC emit_rdtsc(cd) - parameters: ip ... pointer to instruction after branch (void*) - so ... offset of instruction after branch (s8) - to ... offset of branch target (s8) +#define M_IINC_MEMBASE(a,b) emit_incl_membase(cd, (a), (b)) +#define M_LINC_MEMBASE(a,b) emit_incq_membase(cd, (a), (b)) -*******************************************************************************/ +#define M_IADD_MEMBASE(a,b,c) emit_alul_reg_membase(cd, ALU_ADD, (a), (b), (c)) +#define M_IADC_MEMBASE(a,b,c) emit_alul_reg_membase(cd, ALU_ADC, (a), (b), (c)) +#define M_ISUB_MEMBASE(a,b,c) emit_alul_reg_membase(cd, ALU_SUB, (a), (b), (c)) +#define M_ISBB_MEMBASE(a,b,c) emit_alul_reg_membase(cd, ALU_SBB, (a), (b), (c)) -#define gen_resolvebranch(ip,so,to) \ - *((s4*) ((ip) - 4)) = (s4) ((to) - (so)); #endif /* _CODEGEN_H */ @@ -373,4 +361,5 @@ * c-basic-offset: 4 * tab-width: 4 * End: + * vim:noexpandtab:sw=4:ts=4: */