X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fvm%2Fjit%2Fi386%2Fcodegen.c;h=4a6eecc0246279d4dcfc9628a4515b3d8a319239;hb=ec8a7825ec4c6c114b39cb3cfb5694bc68c8fc59;hp=22006907a1bca5c4238a56524cdfdf1be881620e;hpb=3ae649d7d8c0f0c0301b33e9bbbc76361c7e4af5;p=cacao.git diff --git a/src/vm/jit/i386/codegen.c b/src/vm/jit/i386/codegen.c index 22006907a..4a6eecc02 100644 --- a/src/vm/jit/i386/codegen.c +++ b/src/vm/jit/i386/codegen.c @@ -31,7 +31,7 @@ Christian Ullrich Edwin Steiner - $Id: codegen.c 4734 2006-04-05 09:57:55Z edwin $ + $Id: codegen.c 5401 2006-09-07 12:52:31Z twisti $ */ @@ -46,11 +46,16 @@ #include "vm/jit/i386/md-abi.h" #include "vm/jit/i386/codegen.h" -#include "vm/jit/i386/emitfuncs.h" +#include "vm/jit/i386/md-emit.h" #include "mm/memory.h" #include "native/jni.h" #include "native/native.h" + +#if defined(ENABLE_THREADS) +# include "threads/native/lock.h" +#endif + #include "vm/builtin.h" #include "vm/exceptions.h" #include "vm/global.h" @@ -62,18 +67,20 @@ #include "vm/jit/asmpart.h" #include "vm/jit/codegen-common.h" #include "vm/jit/dseg.h" +#include "vm/jit/emit.h" #include "vm/jit/jit.h" #include "vm/jit/parse.h" #include "vm/jit/patcher.h" #include "vm/jit/reg.h" #include "vm/jit/replace.h" -#if defined(ENABLE_LSRA) -# ifdef LSRA_USES_REG_RES -# include "vm/jit/i386/icmd_uses_reg_res.inc" -# endif +#if defined(ENABLE_LSRA) && !defined(ENABLE_SSA) # include "vm/jit/allocator/lsra.h" #endif +#if defined(ENABLE_SSA) +# include "vm/jit/optimizing/lsra.h" +# include "vm/jit/optimizing/ssa.h" +#endif /* codegen ********************************************************************* @@ -82,13 +89,20 @@ *******************************************************************************/ +#if defined(ENABLE_SSA) +void cg_move(codegendata *cd, s4 type, s4 src_regoff, s4 src_flags, + s4 dst_regoff, s4 dst_flags); +void codegen_insert_phi_moves(codegendata *cd, registerdata *rd, lsradata *ls, + basicblock *bptr); +#endif + bool codegen(jitdata *jd) { methodinfo *m; + codeinfo *code; codegendata *cd; registerdata *rd; - s4 len, s1, s2, s3, d, off, disp; - s4 stackframesize; + s4 len, s1, s2, s3, d, disp; stackptr src; varinfo *var; basicblock *bptr; @@ -96,16 +110,25 @@ bool codegen(jitdata *jd) exceptiontable *ex; u2 currentline; methodinfo *lm; /* local methodinfo for ICMD_INVOKE* */ + unresolved_method *um; builtintable_entry *bte; methoddesc *md; - s4 fpu_st_offset = 0; rplpoint *replacementpoint; + s4 fieldtype; +#if defined(ENABLE_SSA) + lsradata *ls; + bool last_cmd_was_goto; + + last_cmd_was_goto = false; + ls = jd->ls; +#endif /* get required compiler data */ - m = jd->m; - cd = jd->cd; - rd = jd->rd; + m = jd->m; + code = jd->code; + cd = jd->cd; + rd = jd->rd; /* prevent compiler warnings */ @@ -127,19 +150,19 @@ bool codegen(jitdata *jd) /* float register are saved on 2 4-byte stackslots */ savedregs_num += (FLT_SAV_CNT - rd->savfltreguse) * 2; - stackframesize = rd->memuse + savedregs_num; + cd->stackframesize = rd->memuse + savedregs_num; -#if defined(USE_THREADS) +#if defined(ENABLE_THREADS) /* space to save argument of monitor_enter */ if (checksync && (m->flags & ACC_SYNCHRONIZED)) { /* reserve 2 slots for long/double return values for monitorexit */ if (IS_2_WORD_TYPE(m->parseddesc->returntype.type)) - stackframesize += 2; + cd->stackframesize += 2; else - stackframesize++; + cd->stackframesize++; } #endif @@ -147,13 +170,13 @@ bool codegen(jitdata *jd) /* Keep stack of non-leaf functions 16-byte aligned. */ - if (!m->isleafmethod) - stackframesize |= 0x3; + if (!jd->isleafmethod) + cd->stackframesize |= 0x3; - (void) dseg_addaddress(cd, m); /* MethodPointer */ - (void) dseg_adds4(cd, stackframesize * 4); /* FrameSize */ + (void) dseg_addaddress(cd, code); /* CodeinfoPointer */ + (void) dseg_adds4(cd, cd->stackframesize * 4); /* FrameSize */ -#if defined(USE_THREADS) +#if defined(ENABLE_THREADS) /* IsSync contains the offset relative to the stack pointer for the argument of monitor_exit used in the exception handler. Since the offset could be zero and give a wrong meaning of the flag it is @@ -161,14 +184,14 @@ bool codegen(jitdata *jd) */ if (checksync && (m->flags & ACC_SYNCHRONIZED)) - (void) dseg_adds4(cd, (rd->memuse + 1) * 4); /* IsSync */ + (void) dseg_adds4(cd, (rd->memuse + 1) * 4); /* IsSync */ else #endif - (void) dseg_adds4(cd, 0); /* IsSync */ + (void) dseg_adds4(cd, 0); /* IsSync */ - (void) dseg_adds4(cd, m->isleafmethod); /* IsLeaf */ - (void) dseg_adds4(cd, INT_SAV_CNT - rd->savintreguse); /* IntSave */ - (void) dseg_adds4(cd, FLT_SAV_CNT - rd->savfltreguse); /* FltSave */ + (void) dseg_adds4(cd, jd->isleafmethod); /* IsLeaf */ + (void) dseg_adds4(cd, INT_SAV_CNT - rd->savintreguse); /* IntSave */ + (void) dseg_adds4(cd, FLT_SAV_CNT - rd->savfltreguse); /* FltSave */ /* adds a reference for the length of the line number counter. We don't know the size yet, since we evaluate the information during code @@ -177,7 +200,7 @@ bool codegen(jitdata *jd) to the information gotten from the class file */ (void) dseg_addlinenumbertablesize(cd); - (void) dseg_adds4(cd, cd->exceptiontablelength); /* ExTableSize */ + (void) dseg_adds4(cd, cd->exceptiontablelength); /* ExTableSize */ /* create exception table */ @@ -188,37 +211,28 @@ bool codegen(jitdata *jd) (void) dseg_addaddress(cd, ex->catchtype.cls); } - /* initialize mcode variables */ - - cd->mcodeptr = cd->mcodebase; - cd->mcodeend = (s4 *) (cd->mcodebase + cd->mcodesize); - - /* initialize the last patcher pointer */ - - cd->lastmcodeptr = cd->mcodeptr; - /* generate method profiling code */ - if (opt_prof) { + if (JITDATA_HAS_FLAG_INSTRUMENT(jd)) { /* count frequency */ - M_MOV_IMM(m, REG_ITMP1); - M_IADD_IMM_MEMBASE(1, REG_ITMP1, OFFSET(methodinfo, frequency)); + M_MOV_IMM(code, REG_ITMP3); + M_IADD_IMM_MEMBASE(1, REG_ITMP3, OFFSET(codeinfo, frequency)); } /* create stack frame (if necessary) */ - if (stackframesize) - M_ASUB_IMM(stackframesize * 4, REG_SP); + if (cd->stackframesize) + M_ASUB_IMM(cd->stackframesize * 4, REG_SP); /* save return address and used callee saved registers */ - p = stackframesize; + p = cd->stackframesize; for (i = INT_SAV_CNT - 1; i >= rd->savintreguse; i--) { p--; M_AST(rd->savintregs[i], REG_SP, p * 4); } for (i = FLT_SAV_CNT - 1; i >= rd->savfltreguse; i--) { - p-=2; i386_fld_reg(cd, rd->savfltregs[i]); i386_fstpl_membase(cd, REG_SP, p * 4); + p-=2; emit_fld_reg(cd, rd->savfltregs[i]); emit_fstpl_membase(cd, REG_SP, p * 4); } /* take arguments out of register or stack frame */ @@ -228,6 +242,11 @@ bool codegen(jitdata *jd) stack_off = 0; for (p = 0, l = 0; p < md->paramcount; p++) { t = md->paramtypes[p].type; +#if defined(ENABLE_SSA) + if ( ls != NULL ) { + l = ls->local_0[p]; + } +#endif var = &(rd->locals[l][t]); l++; if (IS_2_WORD_TYPE(t)) /* increment local counter for 2 word types */ @@ -235,99 +254,114 @@ bool codegen(jitdata *jd) if (var->type < 0) continue; s1 = md->params[p].regoff; + if (IS_INT_LNG_TYPE(t)) { /* integer args */ if (!md->params[p].inmemory) { /* register arguments */ log_text("integer register argument"); assert(0); - if (!(var->flags & INMEMORY)) { /* reg arg -> register */ + if (!IS_INMEMORY(var->flags)) { /* reg arg -> register */ /* rd->argintregs[md->params[p].regoff -> var->regoff */ - } else { /* reg arg -> spilled */ + } + else { /* reg arg -> spilled */ /* rd->argintregs[md->params[p].regoff -> var->regoff * 4 */ } - } else { /* stack arguments */ - if (!(var->flags & INMEMORY)) { /* stack arg -> register */ - i386_mov_membase_reg( /* + 4 for return address */ - cd, REG_SP, (stackframesize + s1) * 4 + 4, var->regoff); + } + else { /* stack arguments */ + if (!IS_INMEMORY(var->flags)) { /* stack arg -> register */ + emit_mov_membase_reg( /* + 4 for return address */ + cd, REG_SP, (cd->stackframesize + s1) * 4 + 4, var->regoff); /* + 4 for return address */ - } else { /* stack arg -> spilled */ + } + else { /* stack arg -> spilled */ if (!IS_2_WORD_TYPE(t)) { -#if 0 - i386_mov_membase_reg( /* + 4 for return address */ - cd, REG_SP, (stackframesize + s1) * 4 + 4, - REG_ITMP1); - i386_mov_reg_membase( - cd, REG_ITMP1, REG_SP, var->regoff * 4); -#else +#if defined(ENABLE_SSA) + /* no copy avoiding by now possible with SSA */ + if (ls != NULL) { + emit_mov_membase_reg( /* + 4 for return address */ + cd, REG_SP, (cd->stackframesize + s1) * 4 + 4, + REG_ITMP1); + emit_mov_reg_membase( + cd, REG_ITMP1, REG_SP, var->regoff * 4); + } + else +#endif /*defined(ENABLE_SSA)*/ /* reuse Stackslotand avoid copying */ - var->regoff = stackframesize + s1 + 1; -#endif + var->regoff = cd->stackframesize + s1 + 1; - } else { -#if 0 - i386_mov_membase_reg( /* + 4 for return address */ - cd, REG_SP, (stackframesize + s1) * 4 + 4, - REG_ITMP1); - i386_mov_reg_membase( - cd, REG_ITMP1, REG_SP, var->regoff * 4); - i386_mov_membase_reg( /* + 4 for return address */ - cd, REG_SP, (stackframesize + s1) * 4 + 4 + 4, - REG_ITMP1); - i386_mov_reg_membase( - cd, REG_ITMP1, REG_SP, var->regoff * 4 + 4); -#else + } + else { +#if defined(ENABLE_SSA) + /* no copy avoiding by now possible with SSA */ + if (ls != NULL) { + emit_mov_membase_reg( /* + 4 for return address */ + cd, REG_SP, (cd->stackframesize + s1) * 4 + 4, + REG_ITMP1); + emit_mov_reg_membase( + cd, REG_ITMP1, REG_SP, var->regoff * 4); + emit_mov_membase_reg( /* + 4 for return address */ + cd, REG_SP, (cd->stackframesize + s1) * 4 + 4 + 4, + REG_ITMP1); + emit_mov_reg_membase( + cd, REG_ITMP1, REG_SP, var->regoff * 4 + 4); + } + else +#endif /*defined(ENABLE_SSA)*/ /* reuse Stackslotand avoid copying */ - var->regoff = stackframesize + s1 + 1; -#endif + var->regoff = cd->stackframesize + s1 + 1; } } } - - } else { /* floating args */ + } + else { /* floating args */ if (!md->params[p].inmemory) { /* register arguments */ log_text("There are no float argument registers!"); assert(0); - if (!(var->flags & INMEMORY)) { /* reg arg -> register */ + if (!IS_INMEMORY(var->flags)) { /* reg arg -> register */ /* rd->argfltregs[md->params[p].regoff -> var->regoff */ } else { /* reg arg -> spilled */ /* rd->argfltregs[md->params[p].regoff -> var->regoff * 4 */ } - } else { /* stack arguments */ - if (!(var->flags & INMEMORY)) { /* stack-arg -> register */ + } + else { /* stack arguments */ + if (!IS_INMEMORY(var->flags)) { /* stack-arg -> register */ if (t == TYPE_FLT) { - i386_flds_membase( - cd, REG_SP, (stackframesize + s1) * 4 + 4); - fpu_st_offset++; - i386_fstp_reg(cd, var->regoff + fpu_st_offset); - fpu_st_offset--; + emit_flds_membase( + cd, REG_SP, (cd->stackframesize + s1) * 4 + 4); + assert(0); +/* emit_fstp_reg(cd, var->regoff + fpu_st_offset); */ - } else { - i386_fldl_membase( - cd, REG_SP, (stackframesize + s1) * 4 + 4); - fpu_st_offset++; - i386_fstp_reg(cd, var->regoff + fpu_st_offset); - fpu_st_offset--; + } + else { + emit_fldl_membase( + cd, REG_SP, (cd->stackframesize + s1) * 4 + 4); + assert(0); +/* emit_fstp_reg(cd, var->regoff + fpu_st_offset); */ } } else { /* stack-arg -> spilled */ -#if 0 - i386_mov_membase_reg( - cd, REG_SP, (stackframesize + s1) * 4 + 4, REG_ITMP1); - i386_mov_reg_membase( - cd, REG_ITMP1, REG_SP, var->regoff * 4); - if (t == TYPE_FLT) { - i386_flds_membase( - cd, REG_SP, (stackframesize + s1) * 4 + 4); - i386_fstps_membase(cd, REG_SP, var->regoff * 4); - } else { - i386_fldl_membase( - cd, REG_SP, (stackframesize + s1) * 4 + 4); - i386_fstpl_membase(cd, REG_SP, var->regoff * 4); +#if defined(ENABLE_SSA) + /* no copy avoiding by now possible with SSA */ + if (ls != NULL) { + emit_mov_membase_reg( + cd, REG_SP, (cd->stackframesize + s1) * 4 + 4, REG_ITMP1); + emit_mov_reg_membase( + cd, REG_ITMP1, REG_SP, var->regoff * 4); + if (t == TYPE_FLT) { + emit_flds_membase( + cd, REG_SP, (cd->stackframesize + s1) * 4 + 4); + emit_fstps_membase(cd, REG_SP, var->regoff * 4); + } + else { + emit_fldl_membase( + cd, REG_SP, (cd->stackframesize + s1) * 4 + 4); + emit_fstpl_membase(cd, REG_SP, var->regoff * 4); + } } -#else + else +#endif /*defined(ENABLE_SSA)*/ /* reuse Stackslotand avoid copying */ - var->regoff = stackframesize + s1 + 1; -#endif + var->regoff = cd->stackframesize + s1 + 1; } } } @@ -335,113 +369,46 @@ bool codegen(jitdata *jd) /* call monitorenter function */ -#if defined(USE_THREADS) +#if defined(ENABLE_THREADS) if (checksync && (m->flags & ACC_SYNCHRONIZED)) { s1 = rd->memuse; if (m->flags & ACC_STATIC) { - M_MOV_IMM(m->class, REG_ITMP1); - M_AST(REG_ITMP1, REG_SP, s1 * 4); - M_AST(REG_ITMP1, REG_SP, 0 * 4); - M_MOV_IMM(BUILTIN_staticmonitorenter, REG_ITMP1); - M_CALL(REG_ITMP1); - - } else { - M_ALD(REG_ITMP1, REG_SP, stackframesize * 4 + 4); + M_MOV_IMM(&m->class->object.header, REG_ITMP1); + } + else { + M_ALD(REG_ITMP1, REG_SP, cd->stackframesize * 4 + 4); M_TEST(REG_ITMP1); M_BEQ(0); - codegen_add_nullpointerexception_ref(cd, cd->mcodeptr); - M_AST(REG_ITMP1, REG_SP, s1 * 4); - M_AST(REG_ITMP1, REG_SP, 0 * 4); - M_MOV_IMM(BUILTIN_monitorenter, REG_ITMP1); - M_CALL(REG_ITMP1); + codegen_add_nullpointerexception_ref(cd); } + + M_AST(REG_ITMP1, REG_SP, s1 * 4); + M_AST(REG_ITMP1, REG_SP, 0 * 4); + M_MOV_IMM(LOCK_monitor_enter, REG_ITMP3); + M_CALL(REG_ITMP3); } #endif - /* copy argument registers to stack and call trace function with pointer - to arguments on stack. - */ - #if !defined(NDEBUG) - if (opt_verbosecall) { - stack_off = 0; - s1 = INT_TMP_CNT * 4 + TRACE_ARGS_NUM * 8 + 4 + 4 + stackframesize * 4; - - M_ISUB_IMM(INT_TMP_CNT * 4 + TRACE_ARGS_NUM * 8 + 4, REG_SP); - - /* save temporary registers for leaf methods */ - - for (p = 0; p < INT_TMP_CNT; p++) - M_IST(rd->tmpintregs[p], REG_SP, TRACE_ARGS_NUM * 8 + 4 + p * 4); - - for (p = 0, l = 0; p < md->paramcount && p < TRACE_ARGS_NUM; p++) { - t = md->paramtypes[p].type; - - if (IS_INT_LNG_TYPE(t)) { - if (IS_2_WORD_TYPE(t)) { - i386_mov_membase_reg(cd, REG_SP, s1 + stack_off, REG_ITMP1); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, p * 8); - i386_mov_membase_reg(cd, REG_SP, s1 + stack_off + 4, REG_ITMP1); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, p * 8 + 4); - - } else if (t == TYPE_ADR) { -/* } else { */ - i386_mov_membase_reg(cd, REG_SP, s1 + stack_off, REG_ITMP1); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, p * 8); - i386_alu_reg_reg(cd, ALU_XOR, REG_ITMP1, REG_ITMP1); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, p * 8 + 4); - - } else { - i386_mov_membase_reg(cd, REG_SP, s1 + stack_off, EAX); - i386_cltd(cd); - i386_mov_reg_membase(cd, EAX, REG_SP, p * 8); - i386_mov_reg_membase(cd, EDX, REG_SP, p * 8 + 4); - } - - } else { - if (!IS_2_WORD_TYPE(t)) { - i386_flds_membase(cd, REG_SP, s1 + stack_off); - i386_fstps_membase(cd, REG_SP, p * 8); - i386_alu_reg_reg(cd, ALU_XOR, REG_ITMP1, REG_ITMP1); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, p * 8 + 4); - - } else { - i386_fldl_membase(cd, REG_SP, s1 + stack_off); - i386_fstpl_membase(cd, REG_SP, p * 8); - } - } - stack_off += (IS_2_WORD_TYPE(t)) ? 8 : 4; - } - - /* fill up the remaining arguments */ - i386_alu_reg_reg(cd, ALU_XOR, REG_ITMP1, REG_ITMP1); - for (p = md->paramcount; p < TRACE_ARGS_NUM; p++) { - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, p * 8); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, p * 8 + 4); - } - - i386_mov_imm_membase(cd, (ptrint) m, REG_SP, TRACE_ARGS_NUM * 8); - i386_mov_imm_reg(cd, (ptrint) builtin_trace_args, REG_ITMP1); - i386_call_reg(cd, REG_ITMP1); - - /* restore temporary registers for leaf methods */ - - for (p = 0; p < INT_TMP_CNT; p++) - M_ILD(rd->tmpintregs[p], REG_SP, TRACE_ARGS_NUM * 8 + 4 + p * 4); + if (JITDATA_HAS_FLAG_VERBOSECALL(jd)) + emit_verbosecall_enter(jd); +#endif - M_IADD_IMM(INT_TMP_CNT * 4 + TRACE_ARGS_NUM * 8 + 4, REG_SP); - } -#endif /* !defined(NDEBUG) */ + } - } +#if defined(ENABLE_SSA) + /* with SSA Header is Basic Block 0 - insert phi Moves if necessary */ + if ( ls != NULL) + codegen_insert_phi_moves(cd, rd, ls, ls->basicblocks[0]); +#endif /* end of header generation */ replacementpoint = jd->code->rplpoints; /* walk through all basic blocks */ - for (bptr = m->basicblocks; bptr != NULL; bptr = bptr->next) { + for (bptr = jd->new_basicblocks; bptr != NULL; bptr = bptr->next) { bptr->mpc = (s4) (cd->mcodeptr - cd->mcodebase); @@ -456,6 +423,7 @@ bool codegen(jitdata *jd) bptr->mpc); } +#if 0 /* handle replacement points */ if (bptr->bitflags & BBFLAG_REPLACEMENT) { @@ -466,47 +434,51 @@ bool codegen(jitdata *jd) assert(cd->lastmcodeptr <= cd->mcodeptr); cd->lastmcodeptr = cd->mcodeptr + 5; /* 5 byte jmp patch */ } +#endif /* copy interface registers to their destination */ - src = bptr->instack; len = bptr->indepth; MCODECHECK(512); +#if 0 /* generate basic block profiling code */ - if (opt_prof) { + if (JITDATA_HAS_FLAG_INSTRUMENT(jd)) { /* count frequency */ - M_MOV_IMM(m->bbfrequency, REG_ITMP1); - M_IADD_IMM_MEMBASE(1, REG_ITMP1, bptr->debug_nr * 4); + M_MOV_IMM(code->bbfrequency, REG_ITMP3); + M_IADD_IMM_MEMBASE(1, REG_ITMP3, bptr->nr * 4); } +#endif - -#if defined(ENABLE_LSRA) +#if defined(ENABLE_LSRA) || defined(ENABLE_SSA) +# if defined(ENABLE_LSRA) && !defined(ENABLE_SSA) if (opt_lsra) { - while (src != NULL) { +# endif +# if defined(ENABLE_SSA) + if (ls != NULL) { + last_cmd_was_goto = false; +# endif + if (len > 0) { len--; - if ((len == 0) && (bptr->type != BBTYPE_STD)) { + src = bptr->invars[len]; + if (bptr->type != BBTYPE_STD) { if (!IS_2_WORD_TYPE(src->type)) { if (bptr->type == BBTYPE_SBR) { - /* d = reg_of_var(m, src, REG_ITMP1); */ - if (!(src->flags & INMEMORY)) + if (!IS_INMEMORY(src->flags)) d = src->regoff; else d = REG_ITMP1; - - i386_pop_reg(cd, d); - store_reg_to_var_int(src, d); - + emit_pop_reg(cd, d); + emit_store(jd, NULL, src, d); } else if (bptr->type == BBTYPE_EXH) { - /* d = reg_of_var(m, src, REG_ITMP1); */ - if (!(src->flags & INMEMORY)) + if (!IS_INMEMORY(src->flags)) d = src->regoff; else d = REG_ITMP1; M_INTMOVE(REG_ITMP1, d); - store_reg_to_var_int(src, d); + emit_store(jd, NULL, src, d); } } else { @@ -514,86 +486,92 @@ bool codegen(jitdata *jd) assert(0); } } - src = src->prev; } - } else { -#endif - while (src != NULL) { - len--; - if ((len == bptr->indepth-1) && (bptr->type != BBTYPE_STD)) { - if (!IS_2_WORD_TYPE(src->type)) { - if (bptr->type == BBTYPE_SBR) { - d = codegen_reg_of_var(rd, 0, src, REG_ITMP1); - i386_pop_reg(cd, d); - store_reg_to_var_int(src, d); + } else +#endif /* defined(ENABLE_LSRA) || defined(ENABLE_SSA) */ + { + while (len) { + len--; + src = bptr->invars[len]; + if ((len == bptr->indepth-1) && (bptr->type != BBTYPE_STD)) { + if (!IS_2_WORD_TYPE(src->type)) { + if (bptr->type == BBTYPE_SBR) { + d = codegen_reg_of_var(rd, 0, src, REG_ITMP1); + emit_pop_reg(cd, d); + emit_store(jd, NULL, src, d); + } else if (bptr->type == BBTYPE_EXH) { d = codegen_reg_of_var(rd, 0, src, REG_ITMP1); M_INTMOVE(REG_ITMP1, d); - store_reg_to_var_int(src, d); + emit_store(jd, NULL, src, d); } - } else { - log_text("copy interface registers: longs have to be in memory (begin 1)"); + log_text("copy interface registers: longs have to be in \ + memory (begin 1)"); assert(0); } } else { +#if defined(NEW_VAR) + assert(src->varkind == STACKVAR); + /* will be done directly in simplereg lateron */ + /* for now codegen_reg_of_var has to be called here to */ + /* set the regoff and flags for all bptr->invars[] */ d = codegen_reg_of_var(rd, 0, src, REG_ITMP1); +#else + if (IS_LNG_TYPE(src->type)) + d = codegen_reg_of_var(rd, 0, src, + PACK_REGS(REG_ITMP1, REG_ITMP2)); + else + d = codegen_reg_of_var(rd, 0, src, REG_ITMP1); +/* d = codegen_reg_of_var(rd, 0, src, REG_IFTMP); */ + if ((src->varkind != STACKVAR)) { s2 = src->type; + s1 = rd->interfaces[len][s2].regoff; + if (IS_FLT_DBL_TYPE(s2)) { - s1 = rd->interfaces[len][s2].regoff; - if (!(rd->interfaces[len][s2].flags & INMEMORY)) { + if (!IS_INMEMORY(rd->interfaces[len][s2].flags)) { M_FLTMOVE(s1, d); - + } else { - if (s2 == TYPE_FLT) { - i386_flds_membase(cd, REG_SP, s1 * 4); - - } else { - i386_fldl_membase(cd, REG_SP, s1 * 4); - } + if (IS_2_WORD_TYPE(s2)) + M_DLD(d, REG_SP, s1 * 4); + else + M_FLD(d, REG_SP, s1 * 4); } - store_reg_to_var_flt(src, d); - + } else { - s1 = rd->interfaces[len][s2].regoff; - if (!IS_2_WORD_TYPE(rd->interfaces[len][s2].type)) { - if (!(rd->interfaces[len][s2].flags & INMEMORY)) { + if (!IS_INMEMORY(rd->interfaces[len][s2].flags)) { + if (IS_2_WORD_TYPE(s2)) + M_LNGMOVE(s1, d); + else M_INTMOVE(s1, d); - - } else { - i386_mov_membase_reg(cd, REG_SP, s1 * 4, d); - } - store_reg_to_var_int(src, d); - + } else { - if (rd->interfaces[len][s2].flags & INMEMORY) { - M_LNGMEMMOVE(s1, src->regoff); - - } else { - log_text("copy interface registers: longs have to be in memory (begin 2)"); - assert(0); - } + if (IS_2_WORD_TYPE(s2)) + M_LLD(d, REG_SP, s1 * 4); + else + M_ILD(d, REG_SP, s1 * 4); } } + + emit_store(jd, NULL, src, d); } +#endif } - src = src->prev; } -#if defined(ENABLE_LSRA) } -#endif /* walk through all instructions */ - src = bptr->instack; len = bptr->icount; currentline = 0; - for (iptr = bptr->iinstr; len > 0; src = iptr->dst, len--, iptr++) { + + for (iptr = bptr->iinstr; len > 0; len--, iptr++) { if (iptr->line != currentline) { - dseg_addlinenumber(cd, iptr->line, cd->mcodeptr); + dseg_addlinenumber(cd, iptr->line); currentline = iptr->line; } @@ -601,230 +579,176 @@ bool codegen(jitdata *jd) switch (iptr->opc) { case ICMD_INLINE_START: +#if 0 { insinfo_inline *insinfo = (insinfo_inline *) iptr->target; -#if defined(USE_THREADS) +#if defined(ENABLE_THREADS) if (insinfo->synchronize) { /* add monitor enter code */ if (insinfo->method->flags & ACC_STATIC) { - M_MOV_IMM(insinfo->method->class, REG_ITMP1); + M_MOV_IMM(&insinfo->method->class->object.header, REG_ITMP1); M_AST(REG_ITMP1, REG_SP, 0 * 4); - M_MOV_IMM(BUILTIN_staticmonitorenter, REG_ITMP1); - M_CALL(REG_ITMP1); } else { /* nullpointer check must have been performed before */ /* (XXX not done, yet) */ var = &(rd->locals[insinfo->synclocal][TYPE_ADR]); - if (var->flags & INMEMORY) { - i386_mov_membase_reg(cd, REG_SP, var->regoff * 4, REG_ITMP1); + if (IS_INMEMORY(var->flags)) { + emit_mov_membase_reg(cd, REG_SP, var->regoff * 4, REG_ITMP1); M_AST(REG_ITMP1, REG_SP, 0 * 4); } else { M_AST(var->regoff, REG_SP, 0 * 4); } - M_MOV_IMM(BUILTIN_monitorenter, REG_ITMP1); - M_CALL(REG_ITMP1); } + + M_MOV_IMM(LOCK_monitor_enter, REG_ITMP3); + M_CALL(REG_ITMP3); } #endif - dseg_addlinenumber_inline_start(cd, iptr, cd->mcodeptr); + dseg_addlinenumber_inline_start(cd, iptr); } +#endif break; case ICMD_INLINE_END: +#if 0 { insinfo_inline *insinfo = (insinfo_inline *) iptr->target; dseg_addlinenumber_inline_end(cd, iptr); - dseg_addlinenumber(cd, iptr->line, cd->mcodeptr); + dseg_addlinenumber(cd, iptr->line); -#if defined(USE_THREADS) +#if defined(ENABLE_THREADS) if (insinfo->synchronize) { /* add monitor exit code */ if (insinfo->method->flags & ACC_STATIC) { - M_MOV_IMM(insinfo->method->class, REG_ITMP1); + M_MOV_IMM(&insinfo->method->class->object.header, REG_ITMP1); M_AST(REG_ITMP1, REG_SP, 0 * 4); - M_MOV_IMM(BUILTIN_monitorexit, REG_ITMP1); - M_CALL(REG_ITMP1); } else { var = &(rd->locals[insinfo->synclocal][TYPE_ADR]); - if (var->flags & INMEMORY) { - i386_mov_membase_reg(cd, REG_SP, var->regoff * 4, REG_ITMP1); + if (IS_INMEMORY(var->flags)) { + M_ALD(REG_ITMP1, REG_SP, var->regoff * 4); M_AST(REG_ITMP1, REG_SP, 0 * 4); } else { M_AST(var->regoff, REG_SP, 0 * 4); } - M_MOV_IMM(BUILTIN_monitorexit, REG_ITMP1); - M_CALL(REG_ITMP1); } + + M_MOV_IMM(LOCK_monitor_exit, REG_ITMP3); + M_CALL(REG_ITMP3); } #endif } +#endif break; case ICMD_NOP: /* ... ==> ... */ - /* REG_RES Register usage: see lsra.inc icmd_uses_tmp */ - /* EAX: NO ECX: NO EDX: NO */ break; case ICMD_CHECKNULL: /* ..., objectref ==> ..., objectref */ - /* REG_RES Register usage: see lsra.inc icmd_uses_tmp */ - /* EAX: NO ECX: NO EDX: NO */ - if (src->flags & INMEMORY) - M_CMP_IMM_MEMBASE(0, REG_SP, src->regoff * 4); - else - M_TEST(src->regoff); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + M_TEST(s1); M_BEQ(0); - codegen_add_nullpointerexception_ref(cd, cd->mcodeptr); + codegen_add_nullpointerexception_ref(cd); break; /* constant operations ************************************************/ case ICMD_ICONST: /* ... ==> ..., constant */ - /* op1 = 0, val.i = constant */ - - /* REG_RES Register usage: see lsra.inc icmd_uses_tmp */ - /* EAX: NO ECX: NO EDX: NO */ - - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1); - if (iptr->dst->flags & INMEMORY) { - M_IST_IMM(iptr->val.i, REG_SP, iptr->dst->regoff * 4); - - } else { - if (iptr->val.i == 0) { - M_CLR(d); - } else { - M_MOV_IMM(iptr->val.i, d); - } - } + d = codegen_reg_of_dst(jd, iptr, REG_ITMP1); + ICONST(d, iptr->sx.val.i); + emit_store_dst(jd, iptr, d); break; case ICMD_LCONST: /* ... ==> ..., constant */ - /* op1 = 0, val.l = constant */ - - /* REG_RES Register usage: see lsra.inc icmd_uses_tmp */ - /* EAX: NO ECX: NO EDX: NO */ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1); - if (iptr->dst->flags & INMEMORY) { - M_IST_IMM(iptr->val.l, REG_SP, iptr->dst->regoff * 4); - M_IST_IMM(iptr->val.l >> 32, REG_SP, iptr->dst->regoff * 4 + 4); - - } else { - log_text("LCONST: longs have to be in memory"); - assert(0); - } + d = codegen_reg_of_dst(jd, iptr, REG_ITMP12_PACKED); + LCONST(d, iptr->sx.val.l); + emit_store_dst(jd, iptr, d); break; case ICMD_FCONST: /* ... ==> ..., constant */ - /* op1 = 0, val.f = constant */ - /* REG_RES Register usage: see lsra.inc icmd_uses_tmp */ - /* EAX: YES ECX: NO EDX: NO */ - - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP1); - if (iptr->val.f == 0.0) { - i386_fldz(cd); - fpu_st_offset++; + d = codegen_reg_of_dst(jd, iptr, REG_FTMP1); + if (iptr->sx.val.f == 0.0) { + emit_fldz(cd); /* -0.0 */ - if (iptr->val.i == 0x80000000) { - i386_fchs(cd); + if (iptr->sx.val.i == 0x80000000) { + emit_fchs(cd); } - } else if (iptr->val.f == 1.0) { - i386_fld1(cd); - fpu_st_offset++; + } else if (iptr->sx.val.f == 1.0) { + emit_fld1(cd); - } else if (iptr->val.f == 2.0) { - i386_fld1(cd); - i386_fld1(cd); - i386_faddp(cd); - fpu_st_offset++; + } else if (iptr->sx.val.f == 2.0) { + emit_fld1(cd); + emit_fld1(cd); + emit_faddp(cd); } else { - disp = dseg_addfloat(cd, iptr->val.f); - i386_mov_imm_reg(cd, 0, REG_ITMP1); - dseg_adddata(cd, cd->mcodeptr); - i386_flds_membase(cd, REG_ITMP1, disp); - fpu_st_offset++; + disp = dseg_addfloat(cd, iptr->sx.val.f); + emit_mov_imm_reg(cd, 0, REG_ITMP1); + dseg_adddata(cd); + emit_flds_membase(cd, REG_ITMP1, disp); } - store_reg_to_var_flt(iptr->dst, d); + emit_store_dst(jd, iptr, d); break; case ICMD_DCONST: /* ... ==> ..., constant */ - /* op1 = 0, val.d = constant */ - - /* REG_RES Register usage: see lsra.inc icmd_uses_tmp */ - /* EAX: YES ECX: NO EDX: NO */ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP1); - if (iptr->val.d == 0.0) { - i386_fldz(cd); - fpu_st_offset++; + d = codegen_reg_of_dst(jd, iptr, REG_FTMP1); + if (iptr->sx.val.d == 0.0) { + emit_fldz(cd); /* -0.0 */ - if (iptr->val.l == 0x8000000000000000LL) { - i386_fchs(cd); + if (iptr->sx.val.l == 0x8000000000000000LL) { + emit_fchs(cd); } - } else if (iptr->val.d == 1.0) { - i386_fld1(cd); - fpu_st_offset++; + } else if (iptr->sx.val.d == 1.0) { + emit_fld1(cd); - } else if (iptr->val.d == 2.0) { - i386_fld1(cd); - i386_fld1(cd); - i386_faddp(cd); - fpu_st_offset++; + } else if (iptr->sx.val.d == 2.0) { + emit_fld1(cd); + emit_fld1(cd); + emit_faddp(cd); } else { - disp = dseg_adddouble(cd, iptr->val.d); - i386_mov_imm_reg(cd, 0, REG_ITMP1); - dseg_adddata(cd, cd->mcodeptr); - i386_fldl_membase(cd, REG_ITMP1, disp); - fpu_st_offset++; + disp = dseg_adddouble(cd, iptr->sx.val.d); + emit_mov_imm_reg(cd, 0, REG_ITMP1); + dseg_adddata(cd); + emit_fldl_membase(cd, REG_ITMP1, disp); } - store_reg_to_var_flt(iptr->dst, d); + emit_store_dst(jd, iptr, d); break; case ICMD_ACONST: /* ... ==> ..., constant */ - /* op1 = 0, val.a = constant */ - /* REG_RES Register usage: see lsra.inc icmd_uses_tmp */ - /* EAX: YES ECX: NO EDX: NO */ + d = codegen_reg_of_dst(jd, iptr, REG_ITMP1); - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1); - - if ((iptr->target != NULL) && (iptr->val.a == NULL)) { - codegen_addpatchref(cd, cd->mcodeptr, - PATCHER_aconst, - (unresolved_class *) iptr->target, 0); + if (INSTRUCTION_IS_UNRESOLVED(iptr)) { + codegen_addpatchref(cd, PATCHER_aconst, + iptr->sx.val.c.ref, 0); if (opt_showdisassemble) { M_NOP; M_NOP; M_NOP; M_NOP; M_NOP; } - M_MOV_IMM(iptr->val.a, d); - store_reg_to_var_int(iptr->dst, d); + M_MOV_IMM(NULL, d); } else { - if (iptr->dst->flags & INMEMORY) { - M_AST_IMM((ptrint) iptr->val.a, REG_SP, iptr->dst->regoff * 4); - - } else { - if ((ptrint) iptr->val.a == 0) { - M_CLR(d); - } else { - M_MOV_IMM(iptr->val.a, d); - } - } + if (iptr->sx.val.anyptr == NULL) + M_CLR(d); + else + M_MOV_IMM(iptr->sx.val.anyptr, d); } + emit_store_dst(jd, iptr, d); break; @@ -832,193 +756,129 @@ bool codegen(jitdata *jd) case ICMD_ILOAD: /* ... ==> ..., content of local variable */ case ICMD_ALOAD: /* op1 = local variable */ - /* REG_RES Register usage: see lsra.inc icmd_uses_tmp */ - /* EAX: YES ECX: NO EDX: NO */ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1); - if ((iptr->dst->varkind == LOCALVAR) && - (iptr->dst->varnum == iptr->op1)) { + d = codegen_reg_of_dst(jd, iptr, REG_ITMP1); + if ((iptr->dst.var->varkind == LOCALVAR) && + (iptr->dst.var->varnum == iptr->s1.localindex)) break; - } - var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ILOAD]); - if (iptr->dst->flags & INMEMORY) { - if (var->flags & INMEMORY) { - i386_mov_membase_reg(cd, REG_SP, var->regoff * 4, REG_ITMP1); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); - - } else { - i386_mov_reg_membase(cd, var->regoff, REG_SP, iptr->dst->regoff * 4); - } - - } else { - if (var->flags & INMEMORY) { - i386_mov_membase_reg(cd, REG_SP, var->regoff * 4, iptr->dst->regoff); - - } else { - M_INTMOVE(var->regoff, iptr->dst->regoff); - } - } + var = &(rd->locals[iptr->s1.localindex][iptr->opc - ICMD_ILOAD]); + if (IS_INMEMORY(var->flags)) + M_ILD(d, REG_SP, var->regoff * 4); + else + M_INTMOVE(var->regoff, d); + emit_store_dst(jd, iptr, d); break; case ICMD_LLOAD: /* ... ==> ..., content of local variable */ - /* op1 = local variable */ - /* REG_RES Register usage: see lsra.inc icmd_uses_tmp */ - /* EAX: NO ECX: NO EDX: NO */ + /* s1.localindex = local variable */ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1); - if ((iptr->dst->varkind == LOCALVAR) && - (iptr->dst->varnum == iptr->op1)) { + d = codegen_reg_of_dst(jd, iptr, REG_ITMP12_PACKED); + if ((iptr->dst.var->varkind == LOCALVAR) && + (iptr->dst.var->varnum == iptr->s1.localindex)) break; - } - var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ILOAD]); - if (iptr->dst->flags & INMEMORY) { - if (var->flags & INMEMORY) { - M_LNGMEMMOVE(var->regoff, iptr->dst->regoff); - - } else { - log_text("LLOAD: longs have to be in memory"); - assert(0); - } - - } else { - log_text("LLOAD: longs have to be in memory"); - assert(0); - } + var = &(rd->locals[iptr->s1.localindex][iptr->opc - ICMD_ILOAD]); + if (IS_INMEMORY(var->flags)) + M_LLD(d, REG_SP, var->regoff * 4); + else + M_LNGMOVE(var->regoff, d); + emit_store_dst(jd, iptr, d); break; case ICMD_FLOAD: /* ... ==> ..., content of local variable */ - /* op1 = local variable */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: NO ECX: NO EDX: NO */ + /* s1.localindex = local variable */ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP1); - if ((iptr->dst->varkind == LOCALVAR) && - (iptr->dst->varnum == iptr->op1)) { + d = codegen_reg_of_dst(jd, iptr, REG_FTMP1); + if ((iptr->dst.var->varkind == LOCALVAR) && + (iptr->dst.var->varnum == iptr->s1.localindex)) break; - } - var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ILOAD]); - if (var->flags & INMEMORY) { - i386_flds_membase(cd, REG_SP, var->regoff * 4); - fpu_st_offset++; - } else { - i386_fld_reg(cd, var->regoff + fpu_st_offset); - fpu_st_offset++; - } - store_reg_to_var_flt(iptr->dst, d); + var = &(rd->locals[iptr->s1.localindex][iptr->opc - ICMD_ILOAD]); + if (IS_INMEMORY(var->flags)) + M_FLD(d, REG_SP, var->regoff * 4); + else + M_FLTMOVE(var->regoff, d); + emit_store_dst(jd, iptr, d); break; case ICMD_DLOAD: /* ... ==> ..., content of local variable */ - /* op1 = local variable */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: NO ECX: NO EDX: NO */ + /* s1.localindex = local variable */ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP1); - if ((iptr->dst->varkind == LOCALVAR) && - (iptr->dst->varnum == iptr->op1)) { - break; - } - var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ILOAD]); - if (var->flags & INMEMORY) { - i386_fldl_membase(cd, REG_SP, var->regoff * 4); - fpu_st_offset++; - } else { - i386_fld_reg(cd, var->regoff + fpu_st_offset); - fpu_st_offset++; - } - store_reg_to_var_flt(iptr->dst, d); + d = codegen_reg_of_dst(jd, iptr, REG_FTMP1); + if ((iptr->dst.var->varkind == LOCALVAR) && + (iptr->dst.var->varnum == iptr->s1.localindex)) + break; + var = &(rd->locals[iptr->s1.localindex][iptr->opc - ICMD_ILOAD]); + if (IS_INMEMORY(var->flags)) + M_DLD(d, REG_SP, var->regoff * 4); + else + M_FLTMOVE(var->regoff, d); + emit_store_dst(jd, iptr, d); break; case ICMD_ISTORE: /* ..., value ==> ... */ case ICMD_ASTORE: /* op1 = local variable */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: NO EDX: NO */ - if ((src->varkind == LOCALVAR) && - (src->varnum == iptr->op1)) { + if ((iptr->s1.var->varkind == LOCALVAR) && + (iptr->s1.var->varnum == iptr->dst.localindex)) break; + var = &(rd->locals[iptr->dst.localindex][iptr->opc - ICMD_ISTORE]); + if (IS_INMEMORY(var->flags)) { + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + M_IST(s1, REG_SP, var->regoff * 4); } - var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ISTORE]); - if (var->flags & INMEMORY) { - if (src->flags & INMEMORY) { - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, var->regoff * 4); - - } else { - i386_mov_reg_membase(cd, src->regoff, REG_SP, var->regoff * 4); - } - - } else { - var_to_reg_int(s1, src, var->regoff); + else { + s1 = emit_load_s1(jd, iptr, var->regoff); M_INTMOVE(s1, var->regoff); } break; case ICMD_LSTORE: /* ..., value ==> ... */ - /* op1 = local variable */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: NO ECX: NO EDX: NO */ + /* dst.localindex = local variable */ - if ((src->varkind == LOCALVAR) && - (src->varnum == iptr->op1)) { + if ((iptr->s1.var->varkind == LOCALVAR) && + (iptr->s1.var->varnum == iptr->dst.localindex)) break; + var = &(rd->locals[iptr->dst.localindex][iptr->opc - ICMD_ISTORE]); + if (IS_INMEMORY(var->flags)) { + s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED); + M_LST(s1, REG_SP, var->regoff * 4); } - var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ISTORE]); - if (var->flags & INMEMORY) { - if (src->flags & INMEMORY) { - M_LNGMEMMOVE(src->regoff, var->regoff); - - } else { - log_text("LSTORE: longs have to be in memory"); - assert(0); - } - - } else { - log_text("LSTORE: longs have to be in memory"); - assert(0); + else { + s1 = emit_load_s1(jd, iptr, var->regoff); + M_LNGMOVE(s1, var->regoff); } break; case ICMD_FSTORE: /* ..., value ==> ... */ - /* op1 = local variable */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: NO ECX: NO EDX: NO */ + /* dst.localindex = local variable */ - if ((src->varkind == LOCALVAR) && - (src->varnum == iptr->op1)) { + if ((iptr->s1.var->varkind == LOCALVAR) && + (iptr->s1.var->varnum == iptr->dst.localindex)) break; + var = &(rd->locals[iptr->dst.localindex][iptr->opc - ICMD_ISTORE]); + if (IS_INMEMORY(var->flags)) { + s1 = emit_load_s1(jd, iptr, REG_FTMP1); + M_FST(s1, REG_SP, var->regoff * 4); } - var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ISTORE]); - if (var->flags & INMEMORY) { - var_to_reg_flt(s1, src, REG_FTMP1); - i386_fstps_membase(cd, REG_SP, var->regoff * 4); - fpu_st_offset--; - } else { - var_to_reg_flt(s1, src, var->regoff); -/* M_FLTMOVE(s1, var->regoff); */ - i386_fstp_reg(cd, var->regoff + fpu_st_offset); - fpu_st_offset--; + else { + s1 = emit_load_s1(jd, iptr, var->regoff); + M_FLTMOVE(s1, var->regoff); } break; case ICMD_DSTORE: /* ..., value ==> ... */ - /* op1 = local variable */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: NO ECX: NO EDX: NO */ + /* dst.localindex = local variable */ - if ((src->varkind == LOCALVAR) && - (src->varnum == iptr->op1)) { + if ((iptr->s1.var->varkind == LOCALVAR) && + (iptr->s1.var->varnum == iptr->dst.localindex)) break; + var = &(rd->locals[iptr->dst.localindex][iptr->opc - ICMD_ISTORE]); + if (IS_INMEMORY(var->flags)) { + s1 = emit_load_s1(jd, iptr, REG_FTMP1); + M_DST(s1, REG_SP, var->regoff * 4); } - var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ISTORE]); - if (var->flags & INMEMORY) { - var_to_reg_flt(s1, src, REG_FTMP1); - i386_fstpl_membase(cd, REG_SP, var->regoff * 4); - fpu_st_offset--; - } else { - var_to_reg_flt(s1, src, var->regoff); -/* M_FLTMOVE(s1, var->regoff); */ - i386_fstp_reg(cd, var->regoff + fpu_st_offset); - fpu_st_offset--; + else { + s1 = emit_load_s1(jd, iptr, var->regoff); + M_FLTMOVE(s1, var->regoff); } break; @@ -1029,831 +889,483 @@ bool codegen(jitdata *jd) case ICMD_POP: /* ..., value ==> ... */ case ICMD_POP2: /* ..., value, value ==> ... */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: NO ECX: NO EDX: NO */ break; case ICMD_DUP: /* ..., a ==> ..., a, a */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: NO EDX: NO */ - M_COPY(src, iptr->dst); - break; - - case ICMD_DUP2: /* ..., a, b ==> ..., a, b, a, b */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: NO EDX: NO */ - M_COPY(src, iptr->dst); - M_COPY(src->prev, iptr->dst->prev); + M_COPY(iptr->s1.var, iptr->dst.var); break; case ICMD_DUP_X1: /* ..., a, b ==> ..., b, a, b */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: NO EDX: NO */ - M_COPY(src, iptr->dst); - M_COPY(src->prev, iptr->dst->prev); - M_COPY(iptr->dst, iptr->dst->prev->prev); + M_COPY(iptr->dst.dupslots[ 1], iptr->dst.dupslots[2+2]); + M_COPY(iptr->dst.dupslots[ 0], iptr->dst.dupslots[2+1]); + M_COPY(iptr->dst.dupslots[2+2], iptr->dst.dupslots[2+0]); break; case ICMD_DUP_X2: /* ..., a, b, c ==> ..., c, a, b, c */ - M_COPY(src, iptr->dst); - M_COPY(src->prev, iptr->dst->prev); - M_COPY(src->prev->prev, iptr->dst->prev->prev); - M_COPY(iptr->dst, iptr->dst->prev->prev->prev); + M_COPY(iptr->dst.dupslots[ 2], iptr->dst.dupslots[3+3]); + M_COPY(iptr->dst.dupslots[ 1], iptr->dst.dupslots[3+2]); + M_COPY(iptr->dst.dupslots[ 0], iptr->dst.dupslots[3+1]); + M_COPY(iptr->dst.dupslots[3+3], iptr->dst.dupslots[3+0]); + break; + + case ICMD_DUP2: /* ..., a, b ==> ..., a, b, a, b */ + + M_COPY(iptr->dst.dupslots[ 1], iptr->dst.dupslots[2+1]); + M_COPY(iptr->dst.dupslots[ 0], iptr->dst.dupslots[2+0]); break; case ICMD_DUP2_X1: /* ..., a, b, c ==> ..., b, c, a, b, c */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: NO EDX: NO */ - M_COPY(src, iptr->dst); - M_COPY(src->prev, iptr->dst->prev); - M_COPY(src->prev->prev, iptr->dst->prev->prev); - M_COPY(iptr->dst, iptr->dst->prev->prev->prev); - M_COPY(iptr->dst->prev, iptr->dst->prev->prev->prev->prev); + M_COPY(iptr->dst.dupslots[ 2], iptr->dst.dupslots[3+4]); + M_COPY(iptr->dst.dupslots[ 1], iptr->dst.dupslots[3+3]); + M_COPY(iptr->dst.dupslots[ 0], iptr->dst.dupslots[3+2]); + M_COPY(iptr->dst.dupslots[3+4], iptr->dst.dupslots[3+1]); + M_COPY(iptr->dst.dupslots[3+3], iptr->dst.dupslots[3+0]); break; case ICMD_DUP2_X2: /* ..., a, b, c, d ==> ..., c, d, a, b, c, d */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: NO EDX: NO */ - M_COPY(src, iptr->dst); - M_COPY(src->prev, iptr->dst->prev); - M_COPY(src->prev->prev, iptr->dst->prev->prev); - M_COPY(src->prev->prev->prev, iptr->dst->prev->prev->prev); - M_COPY(iptr->dst, iptr->dst->prev->prev->prev->prev); - M_COPY(iptr->dst->prev, iptr->dst->prev->prev->prev->prev->prev); + M_COPY(iptr->dst.dupslots[ 3], iptr->dst.dupslots[4+5]); + M_COPY(iptr->dst.dupslots[ 2], iptr->dst.dupslots[4+4]); + M_COPY(iptr->dst.dupslots[ 1], iptr->dst.dupslots[4+3]); + M_COPY(iptr->dst.dupslots[ 0], iptr->dst.dupslots[4+2]); + M_COPY(iptr->dst.dupslots[4+5], iptr->dst.dupslots[4+1]); + M_COPY(iptr->dst.dupslots[4+4], iptr->dst.dupslots[4+0]); break; case ICMD_SWAP: /* ..., a, b ==> ..., b, a */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: NO EDX: NO */ - M_COPY(src, iptr->dst->prev); - M_COPY(src->prev, iptr->dst); + M_COPY(iptr->dst.dupslots[ 1], iptr->dst.dupslots[2+0]); + M_COPY(iptr->dst.dupslots[ 0], iptr->dst.dupslots[2+1]); break; - /* integer operations *************************************************/ +#if 0 + case ICMD_DUP_X1: /* ..., a, b ==> ..., b, a, b */ - case ICMD_INEG: /* ..., value ==> ..., - value */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: NO EDX: NO */ + M_COPY(src, iptr->dst); + M_COPY(src->prev, iptr->dst->prev); +#if defined(ENABLE_SSA) + if ((ls==NULL) || (iptr->dst->varkind != TEMPVAR) || + (ls->lifetime[-iptr->dst->varnum-1].type != -1)) { +#endif + M_COPY(iptr->dst, iptr->dst->prev->prev); +#if defined(ENABLE_SSA) + } else { + M_COPY(src, iptr->dst->prev->prev); + } +#endif + break; - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - if (iptr->dst->flags & INMEMORY) { - if (src->flags & INMEMORY) { - if (src->regoff == iptr->dst->regoff) { - i386_neg_membase(cd, REG_SP, iptr->dst->regoff * 4); + case ICMD_DUP_X2: /* ..., a, b, c ==> ..., c, a, b, c */ - } else { - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1); - i386_neg_reg(cd, REG_ITMP1); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); - } + M_COPY(src, iptr->dst); + M_COPY(src->prev, iptr->dst->prev); + M_COPY(src->prev->prev, iptr->dst->prev->prev); +#if defined(ENABLE_SSA) + if ((ls==NULL) || (iptr->dst->varkind != TEMPVAR) || + (ls->lifetime[-iptr->dst->varnum-1].type != -1)) { +#endif + M_COPY(iptr->dst, iptr->dst->prev->prev->prev); +#if defined(ENABLE_SSA) + } else { + M_COPY(src, iptr->dst->prev->prev->prev); + } +#endif + break; +#endif - } else { - i386_mov_reg_membase(cd, src->regoff, REG_SP, iptr->dst->regoff * 4); - i386_neg_membase(cd, REG_SP, iptr->dst->regoff * 4); - } + /* integer operations *************************************************/ - } else { - if (src->flags & INMEMORY) { - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, iptr->dst->regoff); - i386_neg_reg(cd, iptr->dst->regoff); + case ICMD_INEG: /* ..., value ==> ..., - value */ - } else { - M_INTMOVE(src->regoff, iptr->dst->regoff); - i386_neg_reg(cd, iptr->dst->regoff); - } - } + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP1); + M_INTMOVE(s1, d); + M_NEG(d); + emit_store_dst(jd, iptr, d); break; case ICMD_LNEG: /* ..., value ==> ..., - value */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: NO EDX: NO */ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - if (iptr->dst->flags & INMEMORY) { - if (src->flags & INMEMORY) { - if (src->regoff == iptr->dst->regoff) { - i386_neg_membase(cd, REG_SP, iptr->dst->regoff * 4); - i386_alu_imm_membase(cd, ALU_ADC, 0, REG_SP, iptr->dst->regoff * 4 + 4); - i386_neg_membase(cd, REG_SP, iptr->dst->regoff * 4 + 4); - - } else { - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1); - i386_neg_reg(cd, REG_ITMP1); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP1); - i386_alu_imm_reg(cd, ALU_ADC, 0, REG_ITMP1); - i386_neg_reg(cd, REG_ITMP1); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4 + 4); - } - } - } + s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP12_PACKED); + M_LNGMOVE(s1, d); + M_NEG(GET_LOW_REG(d)); + M_IADDC_IMM(0, GET_HIGH_REG(d)); + M_NEG(GET_HIGH_REG(d)); + emit_store_dst(jd, iptr, d); break; case ICMD_I2L: /* ..., value ==> ..., value */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: NO EDX: YES */ - - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - if (iptr->dst->flags & INMEMORY) { - if (src->flags & INMEMORY) { - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, EAX); - i386_cltd(cd); - i386_mov_reg_membase(cd, EAX, REG_SP, iptr->dst->regoff * 4); - i386_mov_reg_membase(cd, EDX, REG_SP, iptr->dst->regoff * 4 + 4); - } else { - M_INTMOVE(src->regoff, EAX); - i386_cltd(cd); - i386_mov_reg_membase(cd, EAX, REG_SP, iptr->dst->regoff * 4); - i386_mov_reg_membase(cd, EDX, REG_SP, iptr->dst->regoff * 4 + 4); - } - } + s1 = emit_load_s1(jd, iptr, EAX); + d = codegen_reg_of_dst(jd, iptr, EAX_EDX_PACKED); + M_INTMOVE(s1, EAX); + M_CLTD; + M_LNGMOVE(EAX_EDX_PACKED, d); + emit_store_dst(jd, iptr, d); break; case ICMD_L2I: /* ..., value ==> ..., value */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: NO EDX: NO */ - - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - if (iptr->dst->flags & INMEMORY) { - if (src->flags & INMEMORY) { - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); - } - } else { - if (src->flags & INMEMORY) { - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, iptr->dst->regoff); - } - } + s1 = emit_load_s1_low(jd, iptr, REG_ITMP2); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP2); + M_INTMOVE(s1, d); + emit_store_dst(jd, iptr, d); break; case ICMD_INT2BYTE: /* ..., value ==> ..., value */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: NO EDX: NO */ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - if (iptr->dst->flags & INMEMORY) { - if (src->flags & INMEMORY) { - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1); - i386_shift_imm_reg(cd, I386_SHL, 24, REG_ITMP1); - i386_shift_imm_reg(cd, I386_SAR, 24, REG_ITMP1); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP1); + M_INTMOVE(s1, d); + M_SLL_IMM(24, d); + M_SRA_IMM(24, d); + emit_store_dst(jd, iptr, d); + break; - } else { - i386_mov_reg_membase(cd, src->regoff, REG_SP, iptr->dst->regoff * 4); - i386_shift_imm_membase(cd, I386_SHL, 24, REG_SP, iptr->dst->regoff * 4); - i386_shift_imm_membase(cd, I386_SAR, 24, REG_SP, iptr->dst->regoff * 4); - } + case ICMD_INT2CHAR: /* ..., value ==> ..., value */ - } else { - if (src->flags & INMEMORY) { - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, iptr->dst->regoff); - i386_shift_imm_reg(cd, I386_SHL, 24, iptr->dst->regoff); - i386_shift_imm_reg(cd, I386_SAR, 24, iptr->dst->regoff); - - } else { - M_INTMOVE(src->regoff, iptr->dst->regoff); - i386_shift_imm_reg(cd, I386_SHL, 24, iptr->dst->regoff); - i386_shift_imm_reg(cd, I386_SAR, 24, iptr->dst->regoff); - } - } - break; - - case ICMD_INT2CHAR: /* ..., value ==> ..., value */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: NO EDX: NO */ - - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - if (iptr->dst->flags & INMEMORY) { - if (src->flags & INMEMORY) { - if (src->regoff == iptr->dst->regoff) { - i386_alu_imm_membase(cd, ALU_AND, 0x0000ffff, REG_SP, iptr->dst->regoff * 4); - - } else { - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1); - i386_alu_imm_reg(cd, ALU_AND, 0x0000ffff, REG_ITMP1); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); - } - - } else { - i386_mov_reg_membase(cd, src->regoff, REG_SP, iptr->dst->regoff * 4); - i386_alu_imm_membase(cd, ALU_AND, 0x0000ffff, REG_SP, iptr->dst->regoff * 4); - } - - } else { - if (src->flags & INMEMORY) { - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, iptr->dst->regoff); - i386_alu_imm_reg(cd, ALU_AND, 0x0000ffff, iptr->dst->regoff); - - } else { - M_INTMOVE(src->regoff, iptr->dst->regoff); - i386_alu_imm_reg(cd, ALU_AND, 0x0000ffff, iptr->dst->regoff); - } - } - break; + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP2); + M_CZEXT(s1, d); + emit_store_dst(jd, iptr, d); + break; case ICMD_INT2SHORT: /* ..., value ==> ..., value */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: NO EDX: NO */ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - if (iptr->dst->flags & INMEMORY) { - if (src->flags & INMEMORY) { - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1); - i386_shift_imm_reg(cd, I386_SHL, 16, REG_ITMP1); - i386_shift_imm_reg(cd, I386_SAR, 16, REG_ITMP1); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); - - } else { - i386_mov_reg_membase(cd, src->regoff, REG_SP, iptr->dst->regoff * 4); - i386_shift_imm_membase(cd, I386_SHL, 16, REG_SP, iptr->dst->regoff * 4); - i386_shift_imm_membase(cd, I386_SAR, 16, REG_SP, iptr->dst->regoff * 4); - } - - } else { - if (src->flags & INMEMORY) { - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, iptr->dst->regoff); - i386_shift_imm_reg(cd, I386_SHL, 16, iptr->dst->regoff); - i386_shift_imm_reg(cd, I386_SAR, 16, iptr->dst->regoff); - - } else { - M_INTMOVE(src->regoff, iptr->dst->regoff); - i386_shift_imm_reg(cd, I386_SHL, 16, iptr->dst->regoff); - i386_shift_imm_reg(cd, I386_SAR, 16, iptr->dst->regoff); - } - } + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP2); + M_SSEXT(s1, d); + emit_store_dst(jd, iptr, d); break; case ICMD_IADD: /* ..., val1, val2 ==> ..., val1 + val2 */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: NO EDX: NO */ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - i386_emit_ialu(cd, ALU_ADD, src, iptr); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP2); + if (s2 == d) + M_IADD(s1, d); + else { + M_INTMOVE(s1, d); + M_IADD(s2, d); + } + emit_store_dst(jd, iptr, d); break; case ICMD_IADDCONST: /* ..., value ==> ..., value + constant */ - /* val.i = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: NO ECX: NO EDX: NO */ + /* sx.val.i = constant */ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - i386_emit_ialuconst(cd, ALU_ADD, src, iptr); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP1); + M_INTMOVE(s1, d); + M_IADD_IMM(iptr->sx.val.i, d); + emit_store_dst(jd, iptr, d); break; case ICMD_LADD: /* ..., val1, val2 ==> ..., val1 + val2 */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: NO EDX: NO */ - - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - if (iptr->dst->flags & INMEMORY) { - if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) { - if (src->regoff == iptr->dst->regoff) { - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1); - i386_alu_reg_membase(cd, ALU_ADD, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP1); - i386_alu_reg_membase(cd, ALU_ADC, REG_ITMP1, REG_SP, iptr->dst->regoff * 4 + 4); - - } else if (src->prev->regoff == iptr->dst->regoff) { - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1); - i386_alu_reg_membase(cd, ALU_ADD, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP1); - i386_alu_reg_membase(cd, ALU_ADC, REG_ITMP1, REG_SP, iptr->dst->regoff * 4 + 4); - - } else { - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1); - i386_alu_membase_reg(cd, ALU_ADD, REG_SP, src->regoff * 4, REG_ITMP1); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP1); - i386_alu_membase_reg(cd, ALU_ADC, REG_SP, src->regoff * 4 + 4, REG_ITMP1); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4 + 4); - } - } - } + s1 = emit_load_s1_low(jd, iptr, REG_ITMP1); + s2 = emit_load_s2_low(jd, iptr, REG_ITMP2); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP12_PACKED); + M_INTMOVE(s1, GET_LOW_REG(d)); + M_IADD(s2, GET_LOW_REG(d)); + /* don't use REG_ITMP1 */ + s1 = emit_load_s1_high(jd, iptr, REG_ITMP2); + s2 = emit_load_s2_high(jd, iptr, REG_ITMP3); + M_INTMOVE(s1, GET_HIGH_REG(d)); + M_IADDC(s2, GET_HIGH_REG(d)); + emit_store_dst(jd, iptr, d); break; case ICMD_LADDCONST: /* ..., value ==> ..., value + constant */ - /* val.l = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: NO ECX: NO EDX: NO */ - /* else path can never happen? longs stay in memory! */ - - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - if (iptr->dst->flags & INMEMORY) { - if (src->flags & INMEMORY) { - if (src->regoff == iptr->dst->regoff) { - i386_alu_imm_membase(cd, ALU_ADD, iptr->val.l, REG_SP, iptr->dst->regoff * 4); - i386_alu_imm_membase(cd, ALU_ADC, iptr->val.l >> 32, REG_SP, iptr->dst->regoff * 4 + 4); + /* sx.val.l = constant */ - } else { - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1); - i386_alu_imm_reg(cd, ALU_ADD, iptr->val.l, REG_ITMP1); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP1); - i386_alu_imm_reg(cd, ALU_ADC, iptr->val.l >> 32, REG_ITMP1); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4 + 4); - } - } - } + s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP12_PACKED); + M_LNGMOVE(s1, d); + M_IADD_IMM(iptr->sx.val.l, GET_LOW_REG(d)); + M_IADDC_IMM(iptr->sx.val.l >> 32, GET_HIGH_REG(d)); + emit_store_dst(jd, iptr, d); break; case ICMD_ISUB: /* ..., val1, val2 ==> ..., val1 - val2 */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: NO EDX: NO */ - - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - if (iptr->dst->flags & INMEMORY) { - if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) { - if (src->prev->regoff == iptr->dst->regoff) { - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1); - i386_alu_reg_membase(cd, ALU_SUB, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); - - } else { - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1); - i386_alu_membase_reg(cd, ALU_SUB, REG_SP, src->regoff * 4, REG_ITMP1); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); - } - - } else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) { - M_INTMOVE(src->prev->regoff, REG_ITMP1); - i386_alu_membase_reg(cd, ALU_SUB, REG_SP, src->regoff * 4, REG_ITMP1); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); - - } else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) { - if (src->prev->regoff == iptr->dst->regoff) { - i386_alu_reg_membase(cd, ALU_SUB, src->regoff, REG_SP, iptr->dst->regoff * 4); - - } else { - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1); - i386_alu_reg_reg(cd, ALU_SUB, src->regoff, REG_ITMP1); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); - } - - } else { - i386_mov_reg_membase(cd, src->prev->regoff, REG_SP, iptr->dst->regoff * 4); - i386_alu_reg_membase(cd, ALU_SUB, src->regoff, REG_SP, iptr->dst->regoff * 4); - } - - } else { - if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) { - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, d); - i386_alu_membase_reg(cd, ALU_SUB, REG_SP, src->regoff * 4, d); - - } else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) { - M_INTMOVE(src->prev->regoff, d); - i386_alu_membase_reg(cd, ALU_SUB, REG_SP, src->regoff * 4, d); - - } else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) { - /* workaround for reg alloc */ - if (src->regoff == iptr->dst->regoff) { - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1); - i386_alu_reg_reg(cd, ALU_SUB, src->regoff, REG_ITMP1); - M_INTMOVE(REG_ITMP1, d); - - } else { - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, d); - i386_alu_reg_reg(cd, ALU_SUB, src->regoff, d); - } - - } else { - /* workaround for reg alloc */ - if (src->regoff == iptr->dst->regoff) { - M_INTMOVE(src->prev->regoff, REG_ITMP1); - i386_alu_reg_reg(cd, ALU_SUB, src->regoff, REG_ITMP1); - M_INTMOVE(REG_ITMP1, d); - } else { - M_INTMOVE(src->prev->regoff, d); - i386_alu_reg_reg(cd, ALU_SUB, src->regoff, d); - } - } + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP1); + if (s2 == d) { + M_INTMOVE(s1, REG_ITMP1); + M_ISUB(s2, REG_ITMP1); + M_INTMOVE(REG_ITMP1, d); + } + else { + M_INTMOVE(s1, d); + M_ISUB(s2, d); } + emit_store_dst(jd, iptr, d); break; case ICMD_ISUBCONST: /* ..., value ==> ..., value + constant */ - /* val.i = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: NO ECX: NO EDX: NO */ + /* sx.val.i = constant */ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - i386_emit_ialuconst(cd, ALU_SUB, src, iptr); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP1); + M_INTMOVE(s1, d); + M_ISUB_IMM(iptr->sx.val.i, d); + emit_store_dst(jd, iptr, d); break; case ICMD_LSUB: /* ..., val1, val2 ==> ..., val1 - val2 */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: NO EDX: NO */ - - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - if (iptr->dst->flags & INMEMORY) { - if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) { - if (src->prev->regoff == iptr->dst->regoff) { - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1); - i386_alu_reg_membase(cd, ALU_SUB, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP1); - i386_alu_reg_membase(cd, ALU_SBB, REG_ITMP1, REG_SP, iptr->dst->regoff * 4 + 4); - } else { - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1); - i386_alu_membase_reg(cd, ALU_SUB, REG_SP, src->regoff * 4, REG_ITMP1); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP1); - i386_alu_membase_reg(cd, ALU_SBB, REG_SP, src->regoff * 4 + 4, REG_ITMP1); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4 + 4); - } - } + s1 = emit_load_s1_low(jd, iptr, REG_ITMP1); + s2 = emit_load_s2_low(jd, iptr, REG_ITMP2); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP12_PACKED); + if (s2 == GET_LOW_REG(d)) { + M_INTMOVE(s1, REG_ITMP1); + M_ISUB(s2, REG_ITMP1); + M_INTMOVE(REG_ITMP1, GET_LOW_REG(d)); + } + else { + M_INTMOVE(s1, GET_LOW_REG(d)); + M_ISUB(s2, GET_LOW_REG(d)); } + /* don't use REG_ITMP1 */ + s1 = emit_load_s1_high(jd, iptr, REG_ITMP2); + s2 = emit_load_s2_high(jd, iptr, REG_ITMP3); + if (s2 == GET_HIGH_REG(d)) { + M_INTMOVE(s1, REG_ITMP2); + M_ISUBB(s2, REG_ITMP2); + M_INTMOVE(REG_ITMP2, GET_HIGH_REG(d)); + } + else { + M_INTMOVE(s1, GET_HIGH_REG(d)); + M_ISUBB(s2, GET_HIGH_REG(d)); + } + emit_store_dst(jd, iptr, d); break; case ICMD_LSUBCONST: /* ..., value ==> ..., value - constant */ - /* val.l = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: NO ECX: NO EDX: NO */ - /* else path can never happen? longs stay in memory! */ - - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - if (iptr->dst->flags & INMEMORY) { - if (src->flags & INMEMORY) { - if (src->regoff == iptr->dst->regoff) { - i386_alu_imm_membase(cd, ALU_SUB, iptr->val.l, REG_SP, iptr->dst->regoff * 4); - i386_alu_imm_membase(cd, ALU_SBB, iptr->val.l >> 32, REG_SP, iptr->dst->regoff * 4 + 4); + /* sx.val.l = constant */ - } else { - /* TODO: could be size optimized with lea -- see gcc output */ - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1); - i386_alu_imm_reg(cd, ALU_SUB, iptr->val.l, REG_ITMP1); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP1); - i386_alu_imm_reg(cd, ALU_SBB, iptr->val.l >> 32, REG_ITMP1); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4 + 4); - } - } - } + s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP12_PACKED); + M_LNGMOVE(s1, d); + M_ISUB_IMM(iptr->sx.val.l, GET_LOW_REG(d)); + M_ISUBB_IMM(iptr->sx.val.l >> 32, GET_HIGH_REG(d)); + emit_store_dst(jd, iptr, d); break; case ICMD_IMUL: /* ..., val1, val2 ==> ..., val1 * val2 */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: NO EDX: NO OUTPUT: EAX*/ /* EDX really not destroyed by IMUL? */ - - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - if (iptr->dst->flags & INMEMORY) { - if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) { - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1); - i386_imul_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); - - } else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) { - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1); - i386_imul_reg_reg(cd, src->prev->regoff, REG_ITMP1); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); - - } else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) { - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1); - i386_imul_reg_reg(cd, src->regoff, REG_ITMP1); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); - - } else { - i386_mov_reg_reg(cd, src->prev->regoff, REG_ITMP1); - i386_imul_reg_reg(cd, src->regoff, REG_ITMP1); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); - } - - } else { - if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) { - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, iptr->dst->regoff); - i386_imul_membase_reg(cd, REG_SP, src->regoff * 4, iptr->dst->regoff); - - } else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) { - M_INTMOVE(src->prev->regoff, iptr->dst->regoff); - i386_imul_membase_reg(cd, REG_SP, src->regoff * 4, iptr->dst->regoff); - - } else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) { - M_INTMOVE(src->regoff, iptr->dst->regoff); - i386_imul_membase_reg(cd, REG_SP, src->prev->regoff * 4, iptr->dst->regoff); - - } else { - if (src->regoff == iptr->dst->regoff) { - i386_imul_reg_reg(cd, src->prev->regoff, iptr->dst->regoff); - } else { - M_INTMOVE(src->prev->regoff, iptr->dst->regoff); - i386_imul_reg_reg(cd, src->regoff, iptr->dst->regoff); - } - } + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP2); + if (s2 == d) + M_IMUL(s1, d); + else { + M_INTMOVE(s1, d); + M_IMUL(s2, d); } + emit_store_dst(jd, iptr, d); break; case ICMD_IMULCONST: /* ..., value ==> ..., value * constant */ - /* val.i = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: NO EDX: NO OUTPUT: EAX*/ /* EDX really not destroyed by IMUL? */ + /* sx.val.i = constant */ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - if (iptr->dst->flags & INMEMORY) { - if (src->flags & INMEMORY) { - i386_imul_imm_membase_reg(cd, iptr->val.i, REG_SP, src->regoff * 4, REG_ITMP1); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP2); + M_IMUL_IMM(s1, iptr->sx.val.i, d); + emit_store_dst(jd, iptr, d); + break; - } else { - i386_imul_imm_reg_reg(cd, iptr->val.i, src->regoff, REG_ITMP1); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); - } + case ICMD_LMUL: /* ..., val1, val2 ==> ..., val1 * val2 */ - } else { - if (src->flags & INMEMORY) { - i386_imul_imm_membase_reg(cd, iptr->val.i, REG_SP, src->regoff * 4, iptr->dst->regoff); + s1 = emit_load_s1_high(jd, iptr, REG_ITMP2); + s2 = emit_load_s2_low(jd, iptr, EDX); + d = codegen_reg_of_dst(jd, iptr, EAX_EDX_PACKED); - } else { - i386_imul_imm_reg_reg(cd, iptr->val.i, src->regoff, iptr->dst->regoff); - } - } - break; + M_INTMOVE(s1, REG_ITMP2); + M_IMUL(s2, REG_ITMP2); - case ICMD_LMUL: /* ..., val1, val2 ==> ..., val1 * val2 */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL*/ - - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - if (iptr->dst->flags & INMEMORY) { - if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) { - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, EAX); /* mem -> EAX */ - /* optimize move EAX -> REG_ITMP3 is slower??? */ -/* i386_mov_reg_reg(cd, EAX, REG_ITMP3); */ - i386_mul_membase(cd, REG_SP, src->regoff * 4); /* mem * EAX -> EDX:EAX */ - - /* TODO: optimize move EAX -> REG_ITMP3 */ - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP2); /* mem -> ITMP3 */ - i386_imul_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP2); /* mem * ITMP3 -> ITMP3 */ - i386_alu_reg_reg(cd, ALU_ADD, REG_ITMP2, EDX); /* ITMP3 + EDX -> EDX */ - - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP2); /* mem -> ITMP3 */ - i386_imul_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP2); /* mem * ITMP3 -> ITMP3 */ - - i386_alu_reg_reg(cd, ALU_ADD, REG_ITMP2, EDX); /* ITMP3 + EDX -> EDX */ - i386_mov_reg_membase(cd, EAX, REG_SP, iptr->dst->regoff * 4); - i386_mov_reg_membase(cd, EDX, REG_SP, iptr->dst->regoff * 4 + 4); - } - } + s1 = emit_load_s1_low(jd, iptr, EAX); + s2 = emit_load_s2_high(jd, iptr, EDX); + M_INTMOVE(s2, EDX); + M_IMUL(s1, EDX); + M_IADD(EDX, REG_ITMP2); + + s1 = emit_load_s1_low(jd, iptr, EAX); + s2 = emit_load_s2_low(jd, iptr, EDX); + M_INTMOVE(s1, EAX); + M_MUL(s2); + M_INTMOVE(EAX, GET_LOW_REG(d)); + M_IADD(REG_ITMP2, GET_HIGH_REG(d)); + + emit_store_dst(jd, iptr, d); break; case ICMD_LMULCONST: /* ..., value ==> ..., value * constant */ - /* val.l = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL*/ - - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - if (iptr->dst->flags & INMEMORY) { - if (src->flags & INMEMORY) { - i386_mov_imm_reg(cd, iptr->val.l, EAX); /* imm -> EAX */ - i386_mul_membase(cd, REG_SP, src->regoff * 4); /* mem * EAX -> EDX:EAX */ - /* TODO: optimize move EAX -> REG_ITMP3 */ - i386_mov_imm_reg(cd, iptr->val.l >> 32, REG_ITMP2); /* imm -> ITMP3 */ - i386_imul_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP2); /* mem * ITMP3 -> ITMP3 */ - - i386_alu_reg_reg(cd, ALU_ADD, REG_ITMP2, EDX); /* ITMP3 + EDX -> EDX */ - i386_mov_imm_reg(cd, iptr->val.l, REG_ITMP2); /* imm -> ITMP3 */ - i386_imul_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP2); /* mem * ITMP3 -> ITMP3 */ - - i386_alu_reg_reg(cd, ALU_ADD, REG_ITMP2, EDX); /* ITMP3 + EDX -> EDX */ - i386_mov_reg_membase(cd, EAX, REG_SP, iptr->dst->regoff * 4); - i386_mov_reg_membase(cd, EDX, REG_SP, iptr->dst->regoff * 4 + 4); - } - } + /* sx.val.l = constant */ + + s1 = emit_load_s1_low(jd, iptr, REG_ITMP2); + d = codegen_reg_of_dst(jd, iptr, EAX_EDX_PACKED); + ICONST(EAX, iptr->sx.val.l); + M_MUL(s1); + M_IMUL_IMM(s1, iptr->sx.val.l >> 32, REG_ITMP2); + M_IADD(REG_ITMP2, EDX); + s1 = emit_load_s1_high(jd, iptr, REG_ITMP2); + M_IMUL_IMM(s1, iptr->sx.val.l, REG_ITMP2); + M_IADD(REG_ITMP2, EDX); + M_LNGMOVE(EAX_EDX_PACKED, d); + emit_store_dst(jd, iptr, d); break; case ICMD_IDIV: /* ..., val1, val2 ==> ..., val1 / val2 */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: EAX */ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - var_to_reg_int(s1, src, REG_ITMP2); - gen_div_check(src); - if (src->prev->flags & INMEMORY) { - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, EAX); + s1 = emit_load_s1(jd, iptr, EAX); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + d = codegen_reg_of_dst(jd, iptr, EAX); - } else { - M_INTMOVE(src->prev->regoff, EAX); + if (checknull) { + M_TEST(s2); + M_BEQ(0); + codegen_add_arithmeticexception_ref(cd); } - /* check as described in jvm spec */ - - i386_alu_imm_reg(cd, ALU_CMP, 0x80000000, EAX); - i386_jcc(cd, I386_CC_NE, 3 + 6); - i386_alu_imm_reg(cd, ALU_CMP, -1, s1); - i386_jcc(cd, I386_CC_E, 1 + 2); + M_INTMOVE(s1, EAX); /* we need the first operand in EAX */ - i386_cltd(cd); - i386_idiv_reg(cd, s1); + /* check as described in jvm spec */ - if (iptr->dst->flags & INMEMORY) { - i386_mov_reg_membase(cd, EAX, REG_SP, iptr->dst->regoff * 4); + M_CMP_IMM(0x80000000, EAX); + M_BNE(3 + 6); + M_CMP_IMM(-1, s2); + M_BEQ(1 + 2); + M_CLTD; + M_IDIV(s2); - } else { - M_INTMOVE(EAX, iptr->dst->regoff); - } + M_INTMOVE(EAX, d); /* if INMEMORY then d is already EAX */ + emit_store_dst(jd, iptr, d); break; case ICMD_IREM: /* ..., val1, val2 ==> ..., val1 % val2 */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: EDX */ - - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - var_to_reg_int(s1, src, REG_ITMP2); - gen_div_check(src); - if (src->prev->flags & INMEMORY) { - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, EAX); + s1 = emit_load_s1(jd, iptr, EAX); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + d = codegen_reg_of_dst(jd, iptr, EDX); - } else { - M_INTMOVE(src->prev->regoff, EAX); + if (checknull) { + M_TEST(s2); + M_BEQ(0); + codegen_add_arithmeticexception_ref(cd); } - /* check as described in jvm spec */ + M_INTMOVE(s1, EAX); /* we need the first operand in EAX */ - i386_alu_imm_reg(cd, ALU_CMP, 0x80000000, EAX); - i386_jcc(cd, I386_CC_NE, 2 + 3 + 6); - i386_alu_reg_reg(cd, ALU_XOR, EDX, EDX); - i386_alu_imm_reg(cd, ALU_CMP, -1, s1); - i386_jcc(cd, I386_CC_E, 1 + 2); - - i386_cltd(cd); - i386_idiv_reg(cd, s1); + /* check as described in jvm spec */ - if (iptr->dst->flags & INMEMORY) { - i386_mov_reg_membase(cd, EDX, REG_SP, iptr->dst->regoff * 4); + M_CMP_IMM(0x80000000, EAX); + M_BNE(2 + 3 + 6); + M_CLR(EDX); + M_CMP_IMM(-1, s2); + M_BEQ(1 + 2); + M_CLTD; + M_IDIV(s2); - } else { - M_INTMOVE(EDX, iptr->dst->regoff); - } + M_INTMOVE(EDX, d); /* if INMEMORY then d is already EDX */ + emit_store_dst(jd, iptr, d); break; case ICMD_IDIVPOW2: /* ..., value ==> ..., value >> constant */ - /* val.i = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL */ + /* sx.val.i = constant */ /* TODO: optimize for `/ 2' */ - var_to_reg_int(s1, src, REG_ITMP1); - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1); - + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP1); M_INTMOVE(s1, d); - i386_test_reg_reg(cd, d, d); - disp = 2; - CALCIMMEDIATEBYTES(disp, (1 << iptr->val.i) - 1); - i386_jcc(cd, I386_CC_NS, disp); - i386_alu_imm_reg(cd, ALU_ADD, (1 << iptr->val.i) - 1, d); - - i386_shift_imm_reg(cd, I386_SAR, iptr->val.i, d); - store_reg_to_var_int(iptr->dst, d); + M_TEST(d); + M_BNS(6); + M_IADD_IMM32((1 << iptr->sx.val.i) - 1, d); /* 32-bit for jump off. */ + M_SRA_IMM(iptr->sx.val.i, d); + emit_store_dst(jd, iptr, d); break; case ICMD_IREMPOW2: /* ..., value ==> ..., value % constant */ - /* val.i = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: NO OUTPUT: REG_NULL */ + /* sx.val.i = constant */ - var_to_reg_int(s1, src, REG_ITMP1); - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP2); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP2); if (s1 == d) { - M_INTMOVE(s1, REG_ITMP1); + M_MOV(s1, REG_ITMP1); s1 = REG_ITMP1; } - - disp = 2; - disp += 2; - disp += 2; - CALCIMMEDIATEBYTES(disp, iptr->val.i); - disp += 2; - - /* TODO: optimize */ M_INTMOVE(s1, d); - i386_alu_imm_reg(cd, ALU_AND, iptr->val.i, d); - i386_test_reg_reg(cd, s1, s1); - i386_jcc(cd, I386_CC_GE, disp); - i386_mov_reg_reg(cd, s1, d); - i386_neg_reg(cd, d); - i386_alu_imm_reg(cd, ALU_AND, iptr->val.i, d); - i386_neg_reg(cd, d); - -/* M_INTMOVE(s1, EAX); */ -/* i386_cltd(cd); */ -/* i386_alu_reg_reg(cd, ALU_XOR, EDX, EAX); */ -/* i386_alu_reg_reg(cd, ALU_SUB, EDX, EAX); */ -/* i386_alu_reg_reg(cd, ALU_AND, iptr->val.i, EAX); */ -/* i386_alu_reg_reg(cd, ALU_XOR, EDX, EAX); */ -/* i386_alu_reg_reg(cd, ALU_SUB, EDX, EAX); */ -/* M_INTMOVE(EAX, d); */ - -/* i386_alu_reg_reg(cd, ALU_XOR, d, d); */ -/* i386_mov_imm_reg(cd, iptr->val.i, ECX); */ -/* i386_shrd_reg_reg(cd, s1, d); */ -/* i386_shift_imm_reg(cd, I386_SHR, 32 - iptr->val.i, d); */ - - store_reg_to_var_int(iptr->dst, d); + M_AND_IMM(iptr->sx.val.i, d); + M_TEST(s1); + M_BGE(2 + 2 + 6 + 2); + M_MOV(s1, d); /* don't use M_INTMOVE, so we know the jump offset */ + M_NEG(d); + M_AND_IMM32(iptr->sx.val.i, d); /* use 32-bit for jump offset */ + M_NEG(d); + emit_store_dst(jd, iptr, d); break; case ICMD_LDIV: /* ..., val1, val2 ==> ..., val1 / val2 */ case ICMD_LREM: /* ..., val1, val2 ==> ..., val1 % val2 */ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - M_ILD(REG_ITMP2, REG_SP, src->regoff * 4); - M_OR_MEMBASE(REG_SP, src->regoff * 4 + 4, REG_ITMP2); - M_TEST(REG_ITMP2); + s2 = emit_load_s2(jd, iptr, REG_ITMP12_PACKED); + d = codegen_reg_of_dst(jd, iptr, REG_RESULT_PACKED); + + M_INTMOVE(GET_LOW_REG(s2), REG_ITMP3); + M_OR(GET_HIGH_REG(s2), REG_ITMP3); M_BEQ(0); - codegen_add_arithmeticexception_ref(cd, cd->mcodeptr); + codegen_add_arithmeticexception_ref(cd); - bte = iptr->val.a; + bte = iptr->sx.s23.s3.bte; md = bte->md; - M_ILD(REG_ITMP1, REG_SP, src->prev->regoff * 4); - M_ILD(REG_ITMP2, REG_SP, src->prev->regoff * 4 + 4); - M_IST(REG_ITMP1, REG_SP, 0 * 4); - M_IST(REG_ITMP2, REG_SP, 0 * 4 + 4); + M_LST(s2, REG_SP, 2 * 4); - M_ILD(REG_ITMP1, REG_SP, src->regoff * 4); - M_ILD(REG_ITMP2, REG_SP, src->regoff * 4 + 4); - M_IST(REG_ITMP1, REG_SP, 2 * 4); - M_IST(REG_ITMP2, REG_SP, 2 * 4 + 4); + s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED); + M_LST(s1, REG_SP, 0 * 4); M_MOV_IMM(bte->fp, REG_ITMP3); M_CALL(REG_ITMP3); - - M_IST(REG_RESULT, REG_SP, iptr->dst->regoff * 4); - M_IST(REG_RESULT2, REG_SP, iptr->dst->regoff * 4 + 4); + emit_store_dst(jd, iptr, d); break; case ICMD_LDIVPOW2: /* ..., value ==> ..., value >> constant */ - /* val.i = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: NO OUTPUT: REG_NULL */ - - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - if (iptr->dst->flags & INMEMORY) { - if (src->flags & INMEMORY) { - disp = 2; - CALCIMMEDIATEBYTES(disp, (1 << iptr->val.i) - 1); - disp += 3; - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1); - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP2); - - i386_test_reg_reg(cd, REG_ITMP2, REG_ITMP2); - i386_jcc(cd, I386_CC_NS, disp); - i386_alu_imm_reg(cd, ALU_ADD, (1 << iptr->val.i) - 1, REG_ITMP1); - i386_alu_imm_reg(cd, ALU_ADC, 0, REG_ITMP2); - i386_shrd_imm_reg_reg(cd, iptr->val.i, REG_ITMP2, REG_ITMP1); - i386_shift_imm_reg(cd, I386_SAR, iptr->val.i, REG_ITMP2); - - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); - i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 4 + 4); - } - } + /* sx.val.i = constant */ + + s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED); + d = codegen_reg_of_dst(jd, iptr, REG_RESULT_PACKED); + M_LNGMOVE(s1, d); + M_TEST(GET_HIGH_REG(d)); + M_BNS(6 + 3); + M_IADD_IMM32((1 << iptr->sx.val.i) - 1, GET_LOW_REG(d)); + M_IADDC_IMM(0, GET_HIGH_REG(d)); + M_SRLD_IMM(iptr->sx.val.i, GET_HIGH_REG(d), GET_LOW_REG(d)); + M_SRA_IMM(iptr->sx.val.i, GET_HIGH_REG(d)); + emit_store_dst(jd, iptr, d); break; +#if 0 case ICMD_LREMPOW2: /* ..., value ==> ..., value % constant */ - /* val.l = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: NO OUTPUT: REG_NULL */ - - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - if (iptr->dst->flags & INMEMORY) { - if (src->flags & INMEMORY) { - /* Intel algorithm -- does not work, because constant is wrong */ -/* i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1); */ -/* i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP3); */ - -/* M_INTMOVE(REG_ITMP1, REG_ITMP2); */ -/* i386_test_reg_reg(cd, REG_ITMP3, REG_ITMP3); */ -/* i386_jcc(cd, I386_CC_NS, offset); */ -/* i386_alu_imm_reg(cd, ALU_ADD, (1 << iptr->val.l) - 1, REG_ITMP2); */ -/* i386_alu_imm_reg(cd, ALU_ADC, 0, REG_ITMP3); */ - -/* i386_shrd_imm_reg_reg(cd, iptr->val.l, REG_ITMP3, REG_ITMP2); */ -/* i386_shift_imm_reg(cd, I386_SAR, iptr->val.l, REG_ITMP3); */ -/* i386_shld_imm_reg_reg(cd, iptr->val.l, REG_ITMP2, REG_ITMP3); */ - -/* i386_shift_imm_reg(cd, I386_SHL, iptr->val.l, REG_ITMP2); */ - -/* i386_alu_reg_reg(cd, ALU_SUB, REG_ITMP2, REG_ITMP1); */ -/* i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP2); */ -/* i386_alu_reg_reg(cd, ALU_SBB, REG_ITMP3, REG_ITMP2); */ - -/* i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); */ -/* i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 4 + 4); */ + /* sx.val.l = constant */ + d = codegen_reg_of_dst(jd, iptr, REG_NULL); + if (IS_INMEMORY(iptr->dst.var->flags)) { + if (IS_INMEMORY(iptr->s1.var->flags)) { /* Alpha algorithm */ disp = 3; - CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4); + CALCOFFSETBYTES(disp, REG_SP, iptr->s1.var->regoff * 4); disp += 3; - CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4 + 4); + CALCOFFSETBYTES(disp, REG_SP, iptr->s1.var->regoff * 4 + 4); disp += 2; disp += 3; @@ -1861,864 +1373,766 @@ bool codegen(jitdata *jd) /* TODO: hmm, don't know if this is always correct */ disp += 2; - CALCIMMEDIATEBYTES(disp, iptr->val.l & 0x00000000ffffffff); + CALCIMMEDIATEBYTES(disp, iptr->sx.val.l & 0x00000000ffffffff); disp += 2; - CALCIMMEDIATEBYTES(disp, iptr->val.l >> 32); + CALCIMMEDIATEBYTES(disp, iptr->sx.val.l >> 32); disp += 2; disp += 3; disp += 2; - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1); - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP2); + emit_mov_membase_reg(cd, REG_SP, iptr->s1.var->regoff * 4, REG_ITMP1); + emit_mov_membase_reg(cd, REG_SP, iptr->s1.var->regoff * 4 + 4, REG_ITMP2); - i386_alu_imm_reg(cd, ALU_AND, iptr->val.l, REG_ITMP1); - i386_alu_imm_reg(cd, ALU_AND, iptr->val.l >> 32, REG_ITMP2); - i386_alu_imm_membase(cd, ALU_CMP, 0, REG_SP, src->regoff * 4 + 4); - i386_jcc(cd, I386_CC_GE, disp); + emit_alu_imm_reg(cd, ALU_AND, iptr->sx.val.l, REG_ITMP1); + emit_alu_imm_reg(cd, ALU_AND, iptr->sx.val.l >> 32, REG_ITMP2); + emit_alu_imm_membase(cd, ALU_CMP, 0, REG_SP, iptr->s1.var->regoff * 4 + 4); + emit_jcc(cd, CC_GE, disp); - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1); - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP2); + emit_mov_membase_reg(cd, REG_SP, iptr->s1.var->regoff * 4, REG_ITMP1); + emit_mov_membase_reg(cd, REG_SP, iptr->s1.var->regoff * 4 + 4, REG_ITMP2); - i386_neg_reg(cd, REG_ITMP1); - i386_alu_imm_reg(cd, ALU_ADC, 0, REG_ITMP2); - i386_neg_reg(cd, REG_ITMP2); + emit_neg_reg(cd, REG_ITMP1); + emit_alu_imm_reg(cd, ALU_ADC, 0, REG_ITMP2); + emit_neg_reg(cd, REG_ITMP2); - i386_alu_imm_reg(cd, ALU_AND, iptr->val.l, REG_ITMP1); - i386_alu_imm_reg(cd, ALU_AND, iptr->val.l >> 32, REG_ITMP2); + emit_alu_imm_reg(cd, ALU_AND, iptr->sx.val.l, REG_ITMP1); + emit_alu_imm_reg(cd, ALU_AND, iptr->sx.val.l >> 32, REG_ITMP2); - i386_neg_reg(cd, REG_ITMP1); - i386_alu_imm_reg(cd, ALU_ADC, 0, REG_ITMP2); - i386_neg_reg(cd, REG_ITMP2); + emit_neg_reg(cd, REG_ITMP1); + emit_alu_imm_reg(cd, ALU_ADC, 0, REG_ITMP2); + emit_neg_reg(cd, REG_ITMP2); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); - i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 4 + 4); + emit_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst.var->regoff * 4); + emit_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst.var->regoff * 4 + 4); } } - break; + + s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED); + d = codegen_reg_of_dst(jd, iptr, REG_RESULT_PACKED); + M_LNGMOVE(s1, d); + M_AND_IMM(iptr->sx.val.l, GET_LOW_REG(d)); + M_AND_IMM(iptr->sx.val.l >> 32, GET_HIGH_REG(d)); + M_TEST(GET_LOW_REG(s1)); + M_BGE(0); + M_LNGMOVE(s1, d); + break; +#endif case ICMD_ISHL: /* ..., val1, val2 ==> ..., val1 << val2 */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: D|S|YES EDX: NO OUTPUT: REG_NULL*/ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - i386_emit_ishift(cd, I386_SHL, src, iptr); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP1); + M_INTMOVE(s2, ECX); /* s2 may be equal to d */ + M_INTMOVE(s1, d); + M_SLL(d); + emit_store_dst(jd, iptr, d); break; case ICMD_ISHLCONST: /* ..., value ==> ..., value << constant */ - /* val.i = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL*/ + /* sx.val.i = constant */ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - i386_emit_ishiftconst(cd, I386_SHL, src, iptr); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP1); + M_INTMOVE(s1, d); + M_SLL_IMM(iptr->sx.val.i, d); + emit_store_dst(jd, iptr, d); break; case ICMD_ISHR: /* ..., val1, val2 ==> ..., val1 >> val2 */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: D|S|YES EDX: NO OUTPUT: REG_NULL*/ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - i386_emit_ishift(cd, I386_SAR, src, iptr); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP1); + M_INTMOVE(s2, ECX); /* s2 may be equal to d */ + M_INTMOVE(s1, d); + M_SRA(d); + emit_store_dst(jd, iptr, d); break; case ICMD_ISHRCONST: /* ..., value ==> ..., value >> constant */ - /* val.i = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL*/ + /* sx.val.i = constant */ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - i386_emit_ishiftconst(cd, I386_SAR, src, iptr); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP1); + M_INTMOVE(s1, d); + M_SRA_IMM(iptr->sx.val.i, d); + emit_store_dst(jd, iptr, d); break; case ICMD_IUSHR: /* ..., val1, val2 ==> ..., val1 >>> val2 */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: D|S|YES EDX: NO OUTPUT: REG_NULL*/ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - i386_emit_ishift(cd, I386_SHR, src, iptr); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP1); + M_INTMOVE(s2, ECX); /* s2 may be equal to d */ + M_INTMOVE(s1, d); + M_SRL(d); + emit_store_dst(jd, iptr, d); break; case ICMD_IUSHRCONST: /* ..., value ==> ..., value >>> constant */ - /* val.i = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL*/ + /* sx.val.i = constant */ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - i386_emit_ishiftconst(cd, I386_SHR, src, iptr); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP1); + M_INTMOVE(s1, d); + M_SRL_IMM(iptr->sx.val.i, d); + emit_store_dst(jd, iptr, d); break; case ICMD_LSHL: /* ..., val1, val2 ==> ..., val1 << val2 */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: YES EDX: S|YES OUTPUT: REG_NULL*/ - - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - if (iptr->dst->flags & INMEMORY ){ - if (src->prev->flags & INMEMORY) { -/* if (src->prev->regoff == iptr->dst->regoff) { */ -/* i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1); */ - -/* if (src->flags & INMEMORY) { */ -/* i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, ECX); */ -/* } else { */ -/* M_INTMOVE(src->regoff, ECX); */ -/* } */ - -/* i386_test_imm_reg(cd, 32, ECX); */ -/* i386_jcc(cd, I386_CC_E, 2 + 2); */ -/* i386_mov_reg_reg(cd, REG_ITMP1, REG_ITMP2); */ -/* i386_alu_reg_reg(cd, ALU_XOR, REG_ITMP1, REG_ITMP1); */ - -/* i386_shld_reg_membase(cd, REG_ITMP1, REG_SP, src->prev->regoff * 4 + 4); */ -/* i386_shift_membase(cd, I386_SHL, REG_SP, iptr->dst->regoff * 4); */ -/* } else { */ - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1); - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP3); - - if (src->flags & INMEMORY) { - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, ECX); - } else { - M_INTMOVE(src->regoff, ECX); - } - - i386_test_imm_reg(cd, 32, ECX); - i386_jcc(cd, I386_CC_E, 2 + 2); - i386_mov_reg_reg(cd, REG_ITMP1, REG_ITMP3); - i386_alu_reg_reg(cd, ALU_XOR, REG_ITMP1, REG_ITMP1); - - i386_shld_reg_reg(cd, REG_ITMP1, REG_ITMP3); - i386_shift_reg(cd, I386_SHL, REG_ITMP1); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); - i386_mov_reg_membase(cd, REG_ITMP3, REG_SP, iptr->dst->regoff * 4 + 4); -/* } */ - } - } + s1 = emit_load_s1(jd, iptr, REG_ITMP13_PACKED); + s2 = emit_load_s2(jd, iptr, ECX); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP13_PACKED); + M_LNGMOVE(s1, d); + M_INTMOVE(s2, ECX); + M_TEST_IMM(32, ECX); + M_BEQ(2 + 2); + M_MOV(GET_LOW_REG(d), GET_HIGH_REG(d)); + M_CLR(GET_LOW_REG(d)); + M_SLLD(GET_LOW_REG(d), GET_HIGH_REG(d)); + M_SLL(GET_LOW_REG(d)); + emit_store_dst(jd, iptr, d); break; case ICMD_LSHLCONST: /* ..., value ==> ..., value << constant */ - /* val.i = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: NO OUTPUT: REG_NULL*/ - - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - if (iptr->dst->flags & INMEMORY ) { - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1); - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP2); - - if (iptr->val.i & 0x20) { - i386_mov_reg_reg(cd, REG_ITMP1, REG_ITMP2); - i386_alu_reg_reg(cd, ALU_XOR, REG_ITMP1, REG_ITMP1); - i386_shld_imm_reg_reg(cd, iptr->val.i & 0x3f, REG_ITMP1, REG_ITMP2); - - } else { - i386_shld_imm_reg_reg(cd, iptr->val.i & 0x3f, REG_ITMP1, REG_ITMP2); - i386_shift_imm_reg(cd, I386_SHL, iptr->val.i & 0x3f, REG_ITMP1); - } + /* sx.val.i = constant */ - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); - i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 4 + 4); + s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP12_PACKED); + M_LNGMOVE(s1, d); + if (iptr->sx.val.i & 0x20) { + M_MOV(GET_LOW_REG(d), GET_HIGH_REG(d)); + M_CLR(GET_LOW_REG(d)); + M_SLLD_IMM(iptr->sx.val.i & 0x3f, GET_LOW_REG(d), GET_HIGH_REG(d)); } + else { + M_SLLD_IMM(iptr->sx.val.i & 0x3f, GET_LOW_REG(d), GET_HIGH_REG(d)); + M_SLL_IMM(iptr->sx.val.i & 0x3f, GET_LOW_REG(d)); + } + emit_store_dst(jd, iptr, d); break; case ICMD_LSHR: /* ..., val1, val2 ==> ..., val1 >> val2 */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: YES S|EDX: YES OUTPUT: REG_NULL*/ - - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - if (iptr->dst->flags & INMEMORY ){ - if (src->prev->flags & INMEMORY) { -/* if (src->prev->regoff == iptr->dst->regoff) { */ - /* TODO: optimize */ -/* i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1); */ -/* i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP2); */ - -/* if (src->flags & INMEMORY) { */ -/* i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, ECX); */ -/* } else { */ -/* M_INTMOVE(src->regoff, ECX); */ -/* } */ - -/* i386_test_imm_reg(cd, 32, ECX); */ -/* i386_jcc(cd, I386_CC_E, 2 + 3); */ -/* i386_mov_reg_reg(cd, REG_ITMP2, REG_ITMP1); */ -/* i386_shift_imm_reg(cd, I386_SAR, 31, REG_ITMP2); */ - -/* i386_shrd_reg_reg(cd, REG_ITMP2, REG_ITMP1); */ -/* i386_shift_reg(cd, I386_SAR, REG_ITMP2); */ -/* i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); */ -/* i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 4 + 4); */ -/* } else { */ - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1); - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP3); - - if (src->flags & INMEMORY) { - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, ECX); - } else { - M_INTMOVE(src->regoff, ECX); - } - - i386_test_imm_reg(cd, 32, ECX); - i386_jcc(cd, I386_CC_E, 2 + 3); - i386_mov_reg_reg(cd, REG_ITMP3, REG_ITMP1); - i386_shift_imm_reg(cd, I386_SAR, 31, REG_ITMP3); - - i386_shrd_reg_reg(cd, REG_ITMP3, REG_ITMP1); - i386_shift_reg(cd, I386_SAR, REG_ITMP3); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); - i386_mov_reg_membase(cd, REG_ITMP3, REG_SP, iptr->dst->regoff * 4 + 4); -/* } */ - } - } + s1 = emit_load_s1(jd, iptr, REG_ITMP13_PACKED); + s2 = emit_load_s2(jd, iptr, ECX); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP13_PACKED); + M_LNGMOVE(s1, d); + M_INTMOVE(s2, ECX); + M_TEST_IMM(32, ECX); + M_BEQ(2 + 3); + M_MOV(GET_HIGH_REG(d), GET_LOW_REG(d)); + M_SRA_IMM(31, GET_HIGH_REG(d)); + M_SRLD(GET_HIGH_REG(d), GET_LOW_REG(d)); + M_SRA(GET_HIGH_REG(d)); + emit_store_dst(jd, iptr, d); break; case ICMD_LSHRCONST: /* ..., value ==> ..., value >> constant */ - /* val.i = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: NO OUTPUT: REG_NULL*/ - - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - if (iptr->dst->flags & INMEMORY ) { - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1); - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP2); - - if (iptr->val.i & 0x20) { - i386_mov_reg_reg(cd, REG_ITMP2, REG_ITMP1); - i386_shift_imm_reg(cd, I386_SAR, 31, REG_ITMP2); - i386_shrd_imm_reg_reg(cd, iptr->val.i & 0x3f, REG_ITMP2, REG_ITMP1); - - } else { - i386_shrd_imm_reg_reg(cd, iptr->val.i & 0x3f, REG_ITMP2, REG_ITMP1); - i386_shift_imm_reg(cd, I386_SAR, iptr->val.i & 0x3f, REG_ITMP2); - } + /* sx.val.i = constant */ - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); - i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 4 + 4); + s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP12_PACKED); + M_LNGMOVE(s1, d); + if (iptr->sx.val.i & 0x20) { + M_MOV(GET_HIGH_REG(d), GET_LOW_REG(d)); + M_SRA_IMM(31, GET_HIGH_REG(d)); + M_SRLD_IMM(iptr->sx.val.i & 0x3f, GET_HIGH_REG(d), + GET_LOW_REG(d)); } + else { + M_SRLD_IMM(iptr->sx.val.i & 0x3f, GET_HIGH_REG(d), + GET_LOW_REG(d)); + M_SRA_IMM(iptr->sx.val.i & 0x3f, GET_HIGH_REG(d)); + } + emit_store_dst(jd, iptr, d); break; case ICMD_LUSHR: /* ..., val1, val2 ==> ..., val1 >>> val2 */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: YES EDX: S|YES OUTPUT: REG_NULL*/ - - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - if (iptr->dst->flags & INMEMORY ){ - if (src->prev->flags & INMEMORY) { -/* if (src->prev->regoff == iptr->dst->regoff) { */ - /* TODO: optimize */ -/* i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1); */ -/* i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP2); */ - -/* if (src->flags & INMEMORY) { */ -/* i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, ECX); */ -/* } else { */ -/* M_INTMOVE(src->regoff, ECX); */ -/* } */ - -/* i386_test_imm_reg(cd, 32, ECX); */ -/* i386_jcc(cd, I386_CC_E, 2 + 2); */ -/* i386_mov_reg_reg(cd, REG_ITMP2, REG_ITMP1); */ -/* i386_alu_reg_reg(cd, ALU_XOR, REG_ITMP2, REG_ITMP2); */ - -/* i386_shrd_reg_reg(cd, REG_ITMP2, REG_ITMP1); */ -/* i386_shift_reg(cd, I386_SHR, REG_ITMP2); */ -/* i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); */ -/* i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 4 + 4); */ -/* } else { */ - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1); - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP3); - - if (src->flags & INMEMORY) { - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, ECX); - } else { - M_INTMOVE(src->regoff, ECX); - } - - i386_test_imm_reg(cd, 32, ECX); - i386_jcc(cd, I386_CC_E, 2 + 2); - i386_mov_reg_reg(cd, REG_ITMP3, REG_ITMP1); - i386_alu_reg_reg(cd, ALU_XOR, REG_ITMP3, REG_ITMP3); - - i386_shrd_reg_reg(cd, REG_ITMP3, REG_ITMP1); - i386_shift_reg(cd, I386_SHR, REG_ITMP3); - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); - i386_mov_reg_membase(cd, REG_ITMP3, REG_SP, iptr->dst->regoff * 4 + 4); -/* } */ - } - } + s1 = emit_load_s1(jd, iptr, REG_ITMP13_PACKED); + s2 = emit_load_s2(jd, iptr, ECX); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP13_PACKED); + M_LNGMOVE(s1, d); + M_INTMOVE(s2, ECX); + M_TEST_IMM(32, ECX); + M_BEQ(2 + 2); + M_MOV(GET_HIGH_REG(d), GET_LOW_REG(d)); + M_CLR(GET_HIGH_REG(d)); + M_SRLD(GET_HIGH_REG(d), GET_LOW_REG(d)); + M_SRL(GET_HIGH_REG(d)); + emit_store_dst(jd, iptr, d); break; case ICMD_LUSHRCONST: /* ..., value ==> ..., value >>> constant */ - /* val.l = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: NO OUTPUT: REG_NULL*/ - - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - if (iptr->dst->flags & INMEMORY ) { - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1); - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP2); - - if (iptr->val.i & 0x20) { - i386_mov_reg_reg(cd, REG_ITMP2, REG_ITMP1); - i386_alu_reg_reg(cd, ALU_XOR, REG_ITMP2, REG_ITMP2); - i386_shrd_imm_reg_reg(cd, iptr->val.i & 0x3f, REG_ITMP2, REG_ITMP1); - - } else { - i386_shrd_imm_reg_reg(cd, iptr->val.i & 0x3f, REG_ITMP2, REG_ITMP1); - i386_shift_imm_reg(cd, I386_SHR, iptr->val.i & 0x3f, REG_ITMP2); - } + /* sx.val.l = constant */ - i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 4); - i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 4 + 4); + s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP12_PACKED); + M_LNGMOVE(s1, d); + if (iptr->sx.val.i & 0x20) { + M_MOV(GET_HIGH_REG(d), GET_LOW_REG(d)); + M_CLR(GET_HIGH_REG(d)); + M_SRLD_IMM(iptr->sx.val.i & 0x3f, GET_HIGH_REG(d), + GET_LOW_REG(d)); } + else { + M_SRLD_IMM(iptr->sx.val.i & 0x3f, GET_HIGH_REG(d), + GET_LOW_REG(d)); + M_SRL_IMM(iptr->sx.val.i & 0x3f, GET_HIGH_REG(d)); + } + emit_store_dst(jd, iptr, d); break; case ICMD_IAND: /* ..., val1, val2 ==> ..., val1 & val2 */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: NO EDX: NO OUTPUT: REG_NULL*/ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - i386_emit_ialu(cd, ALU_AND, src, iptr); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP2); + if (s2 == d) + M_AND(s1, d); + else { + M_INTMOVE(s1, d); + M_AND(s2, d); + } + emit_store_dst(jd, iptr, d); break; case ICMD_IANDCONST: /* ..., value ==> ..., value & constant */ - /* val.i = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL*/ + /* sx.val.i = constant */ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - i386_emit_ialuconst(cd, ALU_AND, src, iptr); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP1); + M_INTMOVE(s1, d); + M_AND_IMM(iptr->sx.val.i, d); + emit_store_dst(jd, iptr, d); break; case ICMD_LAND: /* ..., val1, val2 ==> ..., val1 & val2 */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL*/ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - i386_emit_lalu(cd, ALU_AND, src, iptr); + s1 = emit_load_s1_low(jd, iptr, REG_ITMP1); + s2 = emit_load_s2_low(jd, iptr, REG_ITMP2); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP12_PACKED); + if (s2 == GET_LOW_REG(d)) + M_AND(s1, GET_LOW_REG(d)); + else { + M_INTMOVE(s1, GET_LOW_REG(d)); + M_AND(s2, GET_LOW_REG(d)); + } + /* REG_ITMP1 probably contains low 32-bit of destination */ + s1 = emit_load_s1_high(jd, iptr, REG_ITMP2); + s2 = emit_load_s2_high(jd, iptr, REG_ITMP3); + if (s2 == GET_HIGH_REG(d)) + M_AND(s1, GET_HIGH_REG(d)); + else { + M_INTMOVE(s1, GET_HIGH_REG(d)); + M_AND(s2, GET_HIGH_REG(d)); + } + emit_store_dst(jd, iptr, d); break; case ICMD_LANDCONST: /* ..., value ==> ..., value & constant */ - /* val.l = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/ + /* sx.val.l = constant */ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - i386_emit_laluconst(cd, ALU_AND, src, iptr); + s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP12_PACKED); + M_LNGMOVE(s1, d); + M_AND_IMM(iptr->sx.val.l, GET_LOW_REG(d)); + M_AND_IMM(iptr->sx.val.l >> 32, GET_HIGH_REG(d)); + emit_store_dst(jd, iptr, d); break; case ICMD_IOR: /* ..., val1, val2 ==> ..., val1 | val2 */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: NO EDX: NO OUTPUT: REG_NULL*/ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - i386_emit_ialu(cd, ALU_OR, src, iptr); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP2); + if (s2 == d) + M_OR(s1, d); + else { + M_INTMOVE(s1, d); + M_OR(s2, d); + } + emit_store_dst(jd, iptr, d); break; case ICMD_IORCONST: /* ..., value ==> ..., value | constant */ - /* val.i = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL*/ + /* sx.val.i = constant */ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - i386_emit_ialuconst(cd, ALU_OR, src, iptr); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP1); + M_INTMOVE(s1, d); + M_OR_IMM(iptr->sx.val.i, d); + emit_store_dst(jd, iptr, d); break; case ICMD_LOR: /* ..., val1, val2 ==> ..., val1 | val2 */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL*/ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - i386_emit_lalu(cd, ALU_OR, src, iptr); + s1 = emit_load_s1_low(jd, iptr, REG_ITMP1); + s2 = emit_load_s2_low(jd, iptr, REG_ITMP2); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP12_PACKED); + if (s2 == GET_LOW_REG(d)) + M_OR(s1, GET_LOW_REG(d)); + else { + M_INTMOVE(s1, GET_LOW_REG(d)); + M_OR(s2, GET_LOW_REG(d)); + } + /* REG_ITMP1 probably contains low 32-bit of destination */ + s1 = emit_load_s1_high(jd, iptr, REG_ITMP2); + s2 = emit_load_s2_high(jd, iptr, REG_ITMP3); + if (s2 == GET_HIGH_REG(d)) + M_OR(s1, GET_HIGH_REG(d)); + else { + M_INTMOVE(s1, GET_HIGH_REG(d)); + M_OR(s2, GET_HIGH_REG(d)); + } + emit_store_dst(jd, iptr, d); break; case ICMD_LORCONST: /* ..., value ==> ..., value | constant */ - /* val.l = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/ + /* sx.val.l = constant */ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - i386_emit_laluconst(cd, ALU_OR, src, iptr); + s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP12_PACKED); + M_LNGMOVE(s1, d); + M_OR_IMM(iptr->sx.val.l, GET_LOW_REG(d)); + M_OR_IMM(iptr->sx.val.l >> 32, GET_HIGH_REG(d)); + emit_store_dst(jd, iptr, d); break; case ICMD_IXOR: /* ..., val1, val2 ==> ..., val1 ^ val2 */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: NO EDX: NO OUTPUT: REG_NULL*/ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - i386_emit_ialu(cd, ALU_XOR, src, iptr); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP2); + if (s2 == d) + M_XOR(s1, d); + else { + M_INTMOVE(s1, d); + M_XOR(s2, d); + } + emit_store_dst(jd, iptr, d); break; case ICMD_IXORCONST: /* ..., value ==> ..., value ^ constant */ - /* val.i = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/ + /* sx.val.i = constant */ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - i386_emit_ialuconst(cd, ALU_XOR, src, iptr); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP1); + M_INTMOVE(s1, d); + M_XOR_IMM(iptr->sx.val.i, d); + emit_store_dst(jd, iptr, d); break; case ICMD_LXOR: /* ..., val1, val2 ==> ..., val1 ^ val2 */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL*/ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - i386_emit_lalu(cd, ALU_XOR, src, iptr); + s1 = emit_load_s1_low(jd, iptr, REG_ITMP1); + s2 = emit_load_s2_low(jd, iptr, REG_ITMP2); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP12_PACKED); + if (s2 == GET_LOW_REG(d)) + M_XOR(s1, GET_LOW_REG(d)); + else { + M_INTMOVE(s1, GET_LOW_REG(d)); + M_XOR(s2, GET_LOW_REG(d)); + } + /* REG_ITMP1 probably contains low 32-bit of destination */ + s1 = emit_load_s1_high(jd, iptr, REG_ITMP2); + s2 = emit_load_s2_high(jd, iptr, REG_ITMP3); + if (s2 == GET_HIGH_REG(d)) + M_XOR(s1, GET_HIGH_REG(d)); + else { + M_INTMOVE(s1, GET_HIGH_REG(d)); + M_XOR(s2, GET_HIGH_REG(d)); + } + emit_store_dst(jd, iptr, d); break; case ICMD_LXORCONST: /* ..., value ==> ..., value ^ constant */ - /* val.l = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/ + /* sx.val.l = constant */ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - i386_emit_laluconst(cd, ALU_XOR, src, iptr); + s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP12_PACKED); + M_LNGMOVE(s1, d); + M_XOR_IMM(iptr->sx.val.l, GET_LOW_REG(d)); + M_XOR_IMM(iptr->sx.val.l >> 32, GET_HIGH_REG(d)); + emit_store_dst(jd, iptr, d); break; case ICMD_IINC: /* ..., value ==> ..., value + constant */ - /* op1 = variable, val.i = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL */ + /* s1.localindex = variable, sx.val.i = constant */ + +#if defined(ENABLE_SSA) + if ( ls != NULL ) { + varinfo *var_t; + + + var = &(rd->locals[iptr->s1.localindex][TYPE_INT]); + var_t = &(rd->locals[iptr->val._i.op1_t][TYPE_INT]); + + /* set s1 to reg of destination or REG_ITMP1 */ + if (IS_INMEMORY(var_t->flags)) + s1 = REG_ITMP1; + else + s1 = var_t->regoff; + + /* move source value to s1 */ + if (IS_INMEMORY(var->flags)) + M_ILD( s1, REG_SP, var->regoff * 4); + else + M_INTMOVE(var->regoff, s1); - var = &(rd->locals[iptr->op1][TYPE_INT]); - if (var->flags & INMEMORY) - M_IADD_IMM_MEMBASE(iptr->val.i, REG_SP, var->regoff * 4); - else { /* `inc reg' is slower on p4's (regarding to ia32 - optimization reference manual and benchmarks) and - as fast on athlon's. */ - M_IADD_IMM(iptr->val.i, var->regoff); - } - break; + optimization reference manual and benchmarks) and as + fast on athlon's. */ + M_IADD_IMM(iptr->val._i.i, s1); - /* floating operations ************************************************/ -#if 0 -#define ROUND_TO_SINGLE \ - i386_fstps_membase(cd, REG_SP, -8); \ - i386_flds_membase(cd, REG_SP, -8); + if (IS_INMEMORY(var_t->flags)) + M_IST(s1, REG_SP, var_t->regoff * 4); + + } else +#endif /* defined(ENABLE_SSA) */ + { + var = &(rd->locals[iptr->s1.localindex][TYPE_INT]); + if (IS_INMEMORY(var->flags)) { + s1 = REG_ITMP1; + M_ILD(s1, REG_SP, var->regoff * 4); + } + else + s1 = var->regoff; -#define ROUND_TO_DOUBLE \ - i386_fstpl_membase(cd, REG_SP, -8); \ - i386_fldl_membase(cd, REG_SP, -8); + /* `inc reg' is slower on p4's (regarding to ia32 + optimization reference manual and benchmarks) and as + fast on athlon's. */ -#define FPU_SET_24BIT_MODE \ - if (!fpu_in_24bit_mode) { \ - i386_fldcw_mem(cd, &fpu_ctrlwrd_24bit); \ - fpu_in_24bit_mode = 1; \ - } + M_IADD_IMM(iptr->sx.val.i, s1); -#define FPU_SET_53BIT_MODE \ - if (fpu_in_24bit_mode) { \ - i386_fldcw_mem(cd, &fpu_ctrlwrd_53bit); \ - fpu_in_24bit_mode = 0; \ + if (IS_INMEMORY(var->flags)) + M_IST(s1, REG_SP, var->regoff * 4); } -#else -#define ROUND_TO_SINGLE -#define ROUND_TO_DOUBLE -#define FPU_SET_24BIT_MODE -#define FPU_SET_53BIT_MODE -#endif + break; + + + /* floating operations ************************************************/ + case ICMD_FNEG: /* ..., value ==> ..., - value */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/ - FPU_SET_24BIT_MODE; - var_to_reg_flt(s1, src, REG_FTMP1); - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP3); - i386_fchs(cd); - store_reg_to_var_flt(iptr->dst, d); + s1 = emit_load_s1(jd, iptr, REG_FTMP1); + d = codegen_reg_of_dst(jd, iptr, REG_FTMP3); + emit_fchs(cd); + emit_store_dst(jd, iptr, d); break; case ICMD_DNEG: /* ..., value ==> ..., - value */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/ - FPU_SET_53BIT_MODE; - var_to_reg_flt(s1, src, REG_FTMP1); - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP3); - i386_fchs(cd); - store_reg_to_var_flt(iptr->dst, d); + s1 = emit_load_s1(jd, iptr, REG_FTMP1); + d = codegen_reg_of_dst(jd, iptr, REG_FTMP3); + emit_fchs(cd); + emit_store_dst(jd, iptr, d); break; case ICMD_FADD: /* ..., val1, val2 ==> ..., val1 + val2 */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/ - FPU_SET_24BIT_MODE; - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP3); - var_to_reg_flt(s1, src->prev, REG_FTMP1); - var_to_reg_flt(s2, src, REG_FTMP2); - i386_faddp(cd); - fpu_st_offset--; - store_reg_to_var_flt(iptr->dst, d); + d = codegen_reg_of_dst(jd, iptr, REG_FTMP3); + s1 = emit_load_s1(jd, iptr, REG_FTMP1); + s2 = emit_load_s2(jd, iptr, REG_FTMP2); + emit_faddp(cd); + emit_store_dst(jd, iptr, d); break; case ICMD_DADD: /* ..., val1, val2 ==> ..., val1 + val2 */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/ - FPU_SET_53BIT_MODE; - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP3); - var_to_reg_flt(s1, src->prev, REG_FTMP1); - var_to_reg_flt(s2, src, REG_FTMP2); - i386_faddp(cd); - fpu_st_offset--; - store_reg_to_var_flt(iptr->dst, d); + d = codegen_reg_of_dst(jd, iptr, REG_FTMP3); + s1 = emit_load_s1(jd, iptr, REG_FTMP1); + s2 = emit_load_s2(jd, iptr, REG_FTMP2); + emit_faddp(cd); + emit_store_dst(jd, iptr, d); break; case ICMD_FSUB: /* ..., val1, val2 ==> ..., val1 - val2 */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/ - FPU_SET_24BIT_MODE; - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP3); - var_to_reg_flt(s1, src->prev, REG_FTMP1); - var_to_reg_flt(s2, src, REG_FTMP2); - i386_fsubp(cd); - fpu_st_offset--; - store_reg_to_var_flt(iptr->dst, d); + d = codegen_reg_of_dst(jd, iptr, REG_FTMP3); + s1 = emit_load_s1(jd, iptr, REG_FTMP1); + s2 = emit_load_s2(jd, iptr, REG_FTMP2); + emit_fsubp(cd); + emit_store_dst(jd, iptr, d); break; case ICMD_DSUB: /* ..., val1, val2 ==> ..., val1 - val2 */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/ - FPU_SET_53BIT_MODE; - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP3); - var_to_reg_flt(s1, src->prev, REG_FTMP1); - var_to_reg_flt(s2, src, REG_FTMP2); - i386_fsubp(cd); - fpu_st_offset--; - store_reg_to_var_flt(iptr->dst, d); + d = codegen_reg_of_dst(jd, iptr, REG_FTMP3); + s1 = emit_load_s1(jd, iptr, REG_FTMP1); + s2 = emit_load_s2(jd, iptr, REG_FTMP2); + emit_fsubp(cd); + emit_store_dst(jd, iptr, d); break; case ICMD_FMUL: /* ..., val1, val2 ==> ..., val1 * val2 */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/ - FPU_SET_24BIT_MODE; - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP3); - var_to_reg_flt(s1, src->prev, REG_FTMP1); - var_to_reg_flt(s2, src, REG_FTMP2); - i386_fmulp(cd); - fpu_st_offset--; - ROUND_TO_SINGLE; - store_reg_to_var_flt(iptr->dst, d); + d = codegen_reg_of_dst(jd, iptr, REG_FTMP3); + s1 = emit_load_s1(jd, iptr, REG_FTMP1); + s2 = emit_load_s2(jd, iptr, REG_FTMP2); + emit_fmulp(cd); + emit_store_dst(jd, iptr, d); break; case ICMD_DMUL: /* ..., val1, val2 ==> ..., val1 * val2 */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/ - - FPU_SET_53BIT_MODE; - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP3); - var_to_reg_flt(s1, src->prev, REG_FTMP1); - -/* i386_fldt_mem(cd, subnormal_bias1); */ -/* i386_fmulp(cd); */ - - var_to_reg_flt(s2, src, REG_FTMP2); - i386_fmulp(cd); - fpu_st_offset--; - -/* i386_fldt_mem(cd, subnormal_bias2); */ -/* i386_fmulp(cd); */ - - store_reg_to_var_flt(iptr->dst, d); + d = codegen_reg_of_dst(jd, iptr, REG_FTMP3); + s1 = emit_load_s1(jd, iptr, REG_FTMP1); + s2 = emit_load_s2(jd, iptr, REG_FTMP2); + emit_fmulp(cd); + emit_store_dst(jd, iptr, d); break; case ICMD_FDIV: /* ..., val1, val2 ==> ..., val1 / val2 */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/ - FPU_SET_24BIT_MODE; - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP3); - var_to_reg_flt(s1, src->prev, REG_FTMP1); - var_to_reg_flt(s2, src, REG_FTMP2); - i386_fdivp(cd); - fpu_st_offset--; - ROUND_TO_SINGLE; - store_reg_to_var_flt(iptr->dst, d); + d = codegen_reg_of_dst(jd, iptr, REG_FTMP3); + s1 = emit_load_s1(jd, iptr, REG_FTMP1); + s2 = emit_load_s2(jd, iptr, REG_FTMP2); + emit_fdivp(cd); + emit_store_dst(jd, iptr, d); break; case ICMD_DDIV: /* ..., val1, val2 ==> ..., val1 / val2 */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/ - - FPU_SET_53BIT_MODE; - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP3); - var_to_reg_flt(s1, src->prev, REG_FTMP1); - -/* i386_fldt_mem(cd, subnormal_bias1); */ -/* i386_fmulp(cd); */ - - var_to_reg_flt(s2, src, REG_FTMP2); - i386_fdivp(cd); - fpu_st_offset--; - -/* i386_fldt_mem(cd, subnormal_bias2); */ -/* i386_fmulp(cd); */ - - store_reg_to_var_flt(iptr->dst, d); + d = codegen_reg_of_dst(jd, iptr, REG_FTMP3); + s1 = emit_load_s1(jd, iptr, REG_FTMP1); + s2 = emit_load_s2(jd, iptr, REG_FTMP2); + emit_fdivp(cd); + emit_store_dst(jd, iptr, d); break; case ICMD_FREM: /* ..., val1, val2 ==> ..., val1 % val2 */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/ - FPU_SET_24BIT_MODE; /* exchanged to skip fxch */ - var_to_reg_flt(s2, src, REG_FTMP2); - var_to_reg_flt(s1, src->prev, REG_FTMP1); - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP3); -/* i386_fxch(cd); */ - i386_fprem(cd); - i386_wait(cd); - i386_fnstsw(cd); - i386_sahf(cd); - i386_jcc(cd, I386_CC_P, -(2 + 1 + 2 + 1 + 6)); - store_reg_to_var_flt(iptr->dst, d); - i386_ffree_reg(cd, 0); - i386_fincstp(cd); - fpu_st_offset--; + s2 = emit_load_s2(jd, iptr, REG_FTMP2); + s1 = emit_load_s1(jd, iptr, REG_FTMP1); + d = codegen_reg_of_dst(jd, iptr, REG_FTMP3); +/* emit_fxch(cd); */ + emit_fprem(cd); + emit_wait(cd); + emit_fnstsw(cd); + emit_sahf(cd); + emit_jcc(cd, CC_P, -(2 + 1 + 2 + 1 + 6)); + emit_store_dst(jd, iptr, d); + emit_ffree_reg(cd, 0); + emit_fincstp(cd); break; case ICMD_DREM: /* ..., val1, val2 ==> ..., val1 % val2 */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/ - FPU_SET_53BIT_MODE; /* exchanged to skip fxch */ - var_to_reg_flt(s2, src, REG_FTMP2); - var_to_reg_flt(s1, src->prev, REG_FTMP1); - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP3); -/* i386_fxch(cd); */ - i386_fprem(cd); - i386_wait(cd); - i386_fnstsw(cd); - i386_sahf(cd); - i386_jcc(cd, I386_CC_P, -(2 + 1 + 2 + 1 + 6)); - store_reg_to_var_flt(iptr->dst, d); - i386_ffree_reg(cd, 0); - i386_fincstp(cd); - fpu_st_offset--; + s2 = emit_load_s2(jd, iptr, REG_FTMP2); + s1 = emit_load_s1(jd, iptr, REG_FTMP1); + d = codegen_reg_of_dst(jd, iptr, REG_FTMP3); +/* emit_fxch(cd); */ + emit_fprem(cd); + emit_wait(cd); + emit_fnstsw(cd); + emit_sahf(cd); + emit_jcc(cd, CC_P, -(2 + 1 + 2 + 1 + 6)); + emit_store_dst(jd, iptr, d); + emit_ffree_reg(cd, 0); + emit_fincstp(cd); break; case ICMD_I2F: /* ..., value ==> ..., (float) value */ case ICMD_I2D: /* ..., value ==> ..., (double) value */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: NO EDX: NO OUTPUT: REG_NULL*/ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP1); - if (src->flags & INMEMORY) { - i386_fildl_membase(cd, REG_SP, src->regoff * 4); - fpu_st_offset++; + d = codegen_reg_of_dst(jd, iptr, REG_FTMP1); + if (IS_INMEMORY(iptr->s1.var->flags)) { + emit_fildl_membase(cd, REG_SP, iptr->s1.var->regoff * 4); } else { disp = dseg_adds4(cd, 0); - i386_mov_imm_reg(cd, 0, REG_ITMP1); - dseg_adddata(cd, cd->mcodeptr); - i386_mov_reg_membase(cd, src->regoff, REG_ITMP1, disp); - i386_fildl_membase(cd, REG_ITMP1, disp); - fpu_st_offset++; + emit_mov_imm_reg(cd, 0, REG_ITMP1); + dseg_adddata(cd); + emit_mov_reg_membase(cd, iptr->s1.var->regoff, REG_ITMP1, disp); + emit_fildl_membase(cd, REG_ITMP1, disp); } - store_reg_to_var_flt(iptr->dst, d); + emit_store_dst(jd, iptr, d); break; case ICMD_L2F: /* ..., value ==> ..., (float) value */ case ICMD_L2D: /* ..., value ==> ..., (double) value */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP1); - if (src->flags & INMEMORY) { - i386_fildll_membase(cd, REG_SP, src->regoff * 4); - fpu_st_offset++; + d = codegen_reg_of_dst(jd, iptr, REG_FTMP1); + if (IS_INMEMORY(iptr->s1.var->flags)) { + emit_fildll_membase(cd, REG_SP, iptr->s1.var->regoff * 4); } else { log_text("L2F: longs have to be in memory"); assert(0); } - store_reg_to_var_flt(iptr->dst, d); + emit_store_dst(jd, iptr, d); break; case ICMD_F2I: /* ..., value ==> ..., (int) value */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: D|YES ECX: NO EDX: NO OUTPUT: EAX*/ - var_to_reg_flt(s1, src, REG_FTMP1); - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); + s1 = emit_load_s1(jd, iptr, REG_FTMP1); + d = codegen_reg_of_dst(jd, iptr, REG_NULL); - i386_mov_imm_reg(cd, 0, REG_ITMP1); - dseg_adddata(cd, cd->mcodeptr); + emit_mov_imm_reg(cd, 0, REG_ITMP1); + dseg_adddata(cd); /* Round to zero, 53-bit mode, exception masked */ disp = dseg_adds4(cd, 0x0e7f); - i386_fldcw_membase(cd, REG_ITMP1, disp); + emit_fldcw_membase(cd, REG_ITMP1, disp); - if (iptr->dst->flags & INMEMORY) { - i386_fistpl_membase(cd, REG_SP, iptr->dst->regoff * 4); - fpu_st_offset--; + if (IS_INMEMORY(iptr->dst.var->flags)) { + emit_fistpl_membase(cd, REG_SP, iptr->dst.var->regoff * 4); /* Round to nearest, 53-bit mode, exceptions masked */ disp = dseg_adds4(cd, 0x027f); - i386_fldcw_membase(cd, REG_ITMP1, disp); + emit_fldcw_membase(cd, REG_ITMP1, disp); - i386_alu_imm_membase(cd, ALU_CMP, 0x80000000, REG_SP, iptr->dst->regoff * 4); + emit_alu_imm_membase(cd, ALU_CMP, 0x80000000, REG_SP, iptr->dst.var->regoff * 4); disp = 3; - CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4); + CALCOFFSETBYTES(disp, REG_SP, iptr->s1.var->regoff * 4); disp += 5 + 2 + 3; - CALCOFFSETBYTES(disp, REG_SP, iptr->dst->regoff * 4); + CALCOFFSETBYTES(disp, REG_SP, iptr->dst.var->regoff * 4); } else { disp = dseg_adds4(cd, 0); - i386_fistpl_membase(cd, REG_ITMP1, disp); - fpu_st_offset--; - i386_mov_membase_reg(cd, REG_ITMP1, disp, iptr->dst->regoff); + emit_fistpl_membase(cd, REG_ITMP1, disp); + emit_mov_membase_reg(cd, REG_ITMP1, disp, iptr->dst.var->regoff); /* Round to nearest, 53-bit mode, exceptions masked */ disp = dseg_adds4(cd, 0x027f); - i386_fldcw_membase(cd, REG_ITMP1, disp); + emit_fldcw_membase(cd, REG_ITMP1, disp); - i386_alu_imm_reg(cd, ALU_CMP, 0x80000000, iptr->dst->regoff); + emit_alu_imm_reg(cd, ALU_CMP, 0x80000000, iptr->dst.var->regoff); disp = 3; - CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4); - disp += 5 + 2 + ((REG_RESULT == iptr->dst->regoff) ? 0 : 2); + CALCOFFSETBYTES(disp, REG_SP, iptr->s1.var->regoff * 4); + disp += 5 + 2 + ((REG_RESULT == iptr->dst.var->regoff) ? 0 : 2); } - i386_jcc(cd, I386_CC_NE, disp); + emit_jcc(cd, CC_NE, disp); /* XXX: change this when we use registers */ - i386_flds_membase(cd, REG_SP, src->regoff * 4); - i386_mov_imm_reg(cd, (ptrint) asm_builtin_f2i, REG_ITMP1); - i386_call_reg(cd, REG_ITMP1); + emit_flds_membase(cd, REG_SP, iptr->s1.var->regoff * 4); + emit_mov_imm_reg(cd, (ptrint) asm_builtin_f2i, REG_ITMP1); + emit_call_reg(cd, REG_ITMP1); - if (iptr->dst->flags & INMEMORY) { - i386_mov_reg_membase(cd, REG_RESULT, REG_SP, iptr->dst->regoff * 4); + if (IS_INMEMORY(iptr->dst.var->flags)) { + emit_mov_reg_membase(cd, REG_RESULT, REG_SP, iptr->dst.var->regoff * 4); } else { - M_INTMOVE(REG_RESULT, iptr->dst->regoff); + M_INTMOVE(REG_RESULT, iptr->dst.var->regoff); } break; case ICMD_D2I: /* ..., value ==> ..., (int) value */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: D|YES ECX: NO EDX: NO OUTPUT: EAX*/ - var_to_reg_flt(s1, src, REG_FTMP1); - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); + s1 = emit_load_s1(jd, iptr, REG_FTMP1); + d = codegen_reg_of_dst(jd, iptr, REG_NULL); - i386_mov_imm_reg(cd, 0, REG_ITMP1); - dseg_adddata(cd, cd->mcodeptr); + emit_mov_imm_reg(cd, 0, REG_ITMP1); + dseg_adddata(cd); /* Round to zero, 53-bit mode, exception masked */ disp = dseg_adds4(cd, 0x0e7f); - i386_fldcw_membase(cd, REG_ITMP1, disp); + emit_fldcw_membase(cd, REG_ITMP1, disp); - if (iptr->dst->flags & INMEMORY) { - i386_fistpl_membase(cd, REG_SP, iptr->dst->regoff * 4); - fpu_st_offset--; + if (IS_INMEMORY(iptr->dst.var->flags)) { + emit_fistpl_membase(cd, REG_SP, iptr->dst.var->regoff * 4); /* Round to nearest, 53-bit mode, exceptions masked */ disp = dseg_adds4(cd, 0x027f); - i386_fldcw_membase(cd, REG_ITMP1, disp); + emit_fldcw_membase(cd, REG_ITMP1, disp); - i386_alu_imm_membase(cd, ALU_CMP, 0x80000000, REG_SP, iptr->dst->regoff * 4); + emit_alu_imm_membase(cd, ALU_CMP, 0x80000000, REG_SP, iptr->dst.var->regoff * 4); disp = 3; - CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4); + CALCOFFSETBYTES(disp, REG_SP, iptr->s1.var->regoff * 4); disp += 5 + 2 + 3; - CALCOFFSETBYTES(disp, REG_SP, iptr->dst->regoff * 4); + CALCOFFSETBYTES(disp, REG_SP, iptr->dst.var->regoff * 4); } else { disp = dseg_adds4(cd, 0); - i386_fistpl_membase(cd, REG_ITMP1, disp); - fpu_st_offset--; - i386_mov_membase_reg(cd, REG_ITMP1, disp, iptr->dst->regoff); + emit_fistpl_membase(cd, REG_ITMP1, disp); + emit_mov_membase_reg(cd, REG_ITMP1, disp, iptr->dst.var->regoff); /* Round to nearest, 53-bit mode, exceptions masked */ disp = dseg_adds4(cd, 0x027f); - i386_fldcw_membase(cd, REG_ITMP1, disp); + emit_fldcw_membase(cd, REG_ITMP1, disp); - i386_alu_imm_reg(cd, ALU_CMP, 0x80000000, iptr->dst->regoff); + emit_alu_imm_reg(cd, ALU_CMP, 0x80000000, iptr->dst.var->regoff); disp = 3; - CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4); - disp += 5 + 2 + ((REG_RESULT == iptr->dst->regoff) ? 0 : 2); + CALCOFFSETBYTES(disp, REG_SP, iptr->s1.var->regoff * 4); + disp += 5 + 2 + ((REG_RESULT == iptr->dst.var->regoff) ? 0 : 2); } - i386_jcc(cd, I386_CC_NE, disp); + emit_jcc(cd, CC_NE, disp); /* XXX: change this when we use registers */ - i386_fldl_membase(cd, REG_SP, src->regoff * 4); - i386_mov_imm_reg(cd, (ptrint) asm_builtin_d2i, REG_ITMP1); - i386_call_reg(cd, REG_ITMP1); + emit_fldl_membase(cd, REG_SP, iptr->s1.var->regoff * 4); + emit_mov_imm_reg(cd, (ptrint) asm_builtin_d2i, REG_ITMP1); + emit_call_reg(cd, REG_ITMP1); - if (iptr->dst->flags & INMEMORY) { - i386_mov_reg_membase(cd, REG_RESULT, REG_SP, iptr->dst->regoff * 4); + if (IS_INMEMORY(iptr->dst.var->flags)) { + emit_mov_reg_membase(cd, REG_RESULT, REG_SP, iptr->dst.var->regoff * 4); } else { - M_INTMOVE(REG_RESULT, iptr->dst->regoff); + M_INTMOVE(REG_RESULT, iptr->dst.var->regoff); } break; case ICMD_F2L: /* ..., value ==> ..., (long) value */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: NO EDX: YES OUTPUT: REG_NULL*/ - var_to_reg_flt(s1, src, REG_FTMP1); - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); + s1 = emit_load_s1(jd, iptr, REG_FTMP1); + d = codegen_reg_of_dst(jd, iptr, REG_NULL); - i386_mov_imm_reg(cd, 0, REG_ITMP1); - dseg_adddata(cd, cd->mcodeptr); + emit_mov_imm_reg(cd, 0, REG_ITMP1); + dseg_adddata(cd); /* Round to zero, 53-bit mode, exception masked */ disp = dseg_adds4(cd, 0x0e7f); - i386_fldcw_membase(cd, REG_ITMP1, disp); + emit_fldcw_membase(cd, REG_ITMP1, disp); - if (iptr->dst->flags & INMEMORY) { - i386_fistpll_membase(cd, REG_SP, iptr->dst->regoff * 4); - fpu_st_offset--; + if (IS_INMEMORY(iptr->dst.var->flags)) { + emit_fistpll_membase(cd, REG_SP, iptr->dst.var->regoff * 4); /* Round to nearest, 53-bit mode, exceptions masked */ disp = dseg_adds4(cd, 0x027f); - i386_fldcw_membase(cd, REG_ITMP1, disp); + emit_fldcw_membase(cd, REG_ITMP1, disp); - i386_alu_imm_membase(cd, ALU_CMP, 0x80000000, REG_SP, iptr->dst->regoff * 4 + 4); + emit_alu_imm_membase(cd, ALU_CMP, 0x80000000, REG_SP, iptr->dst.var->regoff * 4 + 4); disp = 6 + 4; - CALCOFFSETBYTES(disp, REG_SP, iptr->dst->regoff * 4); + CALCOFFSETBYTES(disp, REG_SP, iptr->dst.var->regoff * 4); disp += 3; - CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4); + CALCOFFSETBYTES(disp, REG_SP, iptr->s1.var->regoff * 4); disp += 5 + 2; disp += 3; - CALCOFFSETBYTES(disp, REG_SP, iptr->dst->regoff * 4); + CALCOFFSETBYTES(disp, REG_SP, iptr->dst.var->regoff * 4); disp += 3; - CALCOFFSETBYTES(disp, REG_SP, iptr->dst->regoff * 4 + 4); + CALCOFFSETBYTES(disp, REG_SP, iptr->dst.var->regoff * 4 + 4); - i386_jcc(cd, I386_CC_NE, disp); + emit_jcc(cd, CC_NE, disp); - i386_alu_imm_membase(cd, ALU_CMP, 0, REG_SP, iptr->dst->regoff * 4); + emit_alu_imm_membase(cd, ALU_CMP, 0, REG_SP, iptr->dst.var->regoff * 4); disp = 3; - CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4); + CALCOFFSETBYTES(disp, REG_SP, iptr->s1.var->regoff * 4); disp += 5 + 2 + 3; - CALCOFFSETBYTES(disp, REG_SP, iptr->dst->regoff * 4); + CALCOFFSETBYTES(disp, REG_SP, iptr->dst.var->regoff * 4); - i386_jcc(cd, I386_CC_NE, disp); + emit_jcc(cd, CC_NE, disp); /* XXX: change this when we use registers */ - i386_flds_membase(cd, REG_SP, src->regoff * 4); - i386_mov_imm_reg(cd, (ptrint) asm_builtin_f2l, REG_ITMP1); - i386_call_reg(cd, REG_ITMP1); - i386_mov_reg_membase(cd, REG_RESULT, REG_SP, iptr->dst->regoff * 4); - i386_mov_reg_membase(cd, REG_RESULT2, REG_SP, iptr->dst->regoff * 4 + 4); + emit_flds_membase(cd, REG_SP, iptr->s1.var->regoff * 4); + emit_mov_imm_reg(cd, (ptrint) asm_builtin_f2l, REG_ITMP1); + emit_call_reg(cd, REG_ITMP1); + emit_mov_reg_membase(cd, REG_RESULT, REG_SP, iptr->dst.var->regoff * 4); + emit_mov_reg_membase(cd, REG_RESULT2, REG_SP, iptr->dst.var->regoff * 4 + 4); } else { log_text("F2L: longs have to be in memory"); @@ -2727,56 +2141,53 @@ bool codegen(jitdata *jd) break; case ICMD_D2L: /* ..., value ==> ..., (long) value */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: NO EDX: YES OUTPUT: REG_NULL*/ - var_to_reg_flt(s1, src, REG_FTMP1); - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); + s1 = emit_load_s1(jd, iptr, REG_FTMP1); + d = codegen_reg_of_dst(jd, iptr, REG_NULL); - i386_mov_imm_reg(cd, 0, REG_ITMP1); - dseg_adddata(cd, cd->mcodeptr); + emit_mov_imm_reg(cd, 0, REG_ITMP1); + dseg_adddata(cd); /* Round to zero, 53-bit mode, exception masked */ disp = dseg_adds4(cd, 0x0e7f); - i386_fldcw_membase(cd, REG_ITMP1, disp); + emit_fldcw_membase(cd, REG_ITMP1, disp); - if (iptr->dst->flags & INMEMORY) { - i386_fistpll_membase(cd, REG_SP, iptr->dst->regoff * 4); - fpu_st_offset--; + if (IS_INMEMORY(iptr->dst.var->flags)) { + emit_fistpll_membase(cd, REG_SP, iptr->dst.var->regoff * 4); /* Round to nearest, 53-bit mode, exceptions masked */ disp = dseg_adds4(cd, 0x027f); - i386_fldcw_membase(cd, REG_ITMP1, disp); + emit_fldcw_membase(cd, REG_ITMP1, disp); - i386_alu_imm_membase(cd, ALU_CMP, 0x80000000, REG_SP, iptr->dst->regoff * 4 + 4); + emit_alu_imm_membase(cd, ALU_CMP, 0x80000000, REG_SP, iptr->dst.var->regoff * 4 + 4); disp = 6 + 4; - CALCOFFSETBYTES(disp, REG_SP, iptr->dst->regoff * 4); + CALCOFFSETBYTES(disp, REG_SP, iptr->dst.var->regoff * 4); disp += 3; - CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4); + CALCOFFSETBYTES(disp, REG_SP, iptr->s1.var->regoff * 4); disp += 5 + 2; disp += 3; - CALCOFFSETBYTES(disp, REG_SP, iptr->dst->regoff * 4); + CALCOFFSETBYTES(disp, REG_SP, iptr->dst.var->regoff * 4); disp += 3; - CALCOFFSETBYTES(disp, REG_SP, iptr->dst->regoff * 4 + 4); + CALCOFFSETBYTES(disp, REG_SP, iptr->dst.var->regoff * 4 + 4); - i386_jcc(cd, I386_CC_NE, disp); + emit_jcc(cd, CC_NE, disp); - i386_alu_imm_membase(cd, ALU_CMP, 0, REG_SP, iptr->dst->regoff * 4); + emit_alu_imm_membase(cd, ALU_CMP, 0, REG_SP, iptr->dst.var->regoff * 4); disp = 3; - CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4); + CALCOFFSETBYTES(disp, REG_SP, iptr->s1.var->regoff * 4); disp += 5 + 2 + 3; - CALCOFFSETBYTES(disp, REG_SP, iptr->dst->regoff * 4); + CALCOFFSETBYTES(disp, REG_SP, iptr->dst.var->regoff * 4); - i386_jcc(cd, I386_CC_NE, disp); + emit_jcc(cd, CC_NE, disp); /* XXX: change this when we use registers */ - i386_fldl_membase(cd, REG_SP, src->regoff * 4); - i386_mov_imm_reg(cd, (ptrint) asm_builtin_d2l, REG_ITMP1); - i386_call_reg(cd, REG_ITMP1); - i386_mov_reg_membase(cd, REG_RESULT, REG_SP, iptr->dst->regoff * 4); - i386_mov_reg_membase(cd, REG_RESULT2, REG_SP, iptr->dst->regoff * 4 + 4); + emit_fldl_membase(cd, REG_SP, iptr->s1.var->regoff * 4); + emit_mov_imm_reg(cd, (ptrint) asm_builtin_d2l, REG_ITMP1); + emit_call_reg(cd, REG_ITMP1); + emit_mov_reg_membase(cd, REG_RESULT, REG_SP, iptr->dst.var->regoff * 4); + emit_mov_reg_membase(cd, REG_RESULT2, REG_SP, iptr->dst.var->regoff * 4 + 4); } else { log_text("D2L: longs have to be in memory"); @@ -2785,340 +2196,287 @@ bool codegen(jitdata *jd) break; case ICMD_F2D: /* ..., value ==> ..., (double) value */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/ - var_to_reg_flt(s1, src, REG_FTMP1); - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP3); + s1 = emit_load_s1(jd, iptr, REG_FTMP1); + d = codegen_reg_of_dst(jd, iptr, REG_FTMP3); /* nothing to do */ - store_reg_to_var_flt(iptr->dst, d); + emit_store_dst(jd, iptr, d); break; case ICMD_D2F: /* ..., value ==> ..., (float) value */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: NO ECX: NO EDX: NO OUTPUT: REG_NULL*/ - var_to_reg_flt(s1, src, REG_FTMP1); - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP3); + s1 = emit_load_s1(jd, iptr, REG_FTMP1); + d = codegen_reg_of_dst(jd, iptr, REG_FTMP3); /* nothing to do */ - store_reg_to_var_flt(iptr->dst, d); + emit_store_dst(jd, iptr, d); break; case ICMD_FCMPL: /* ..., val1, val2 ==> ..., val1 fcmpl val2 */ case ICMD_DCMPL: - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL*/ /* exchanged to skip fxch */ - var_to_reg_flt(s2, src->prev, REG_FTMP1); - var_to_reg_flt(s1, src, REG_FTMP2); - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1); -/* i386_fxch(cd); */ - i386_fucompp(cd); - fpu_st_offset -= 2; - i386_fnstsw(cd); - i386_test_imm_reg(cd, 0x400, EAX); /* unordered treat as GT */ - i386_jcc(cd, I386_CC_E, 6); - i386_alu_imm_reg(cd, ALU_AND, 0x000000ff, EAX); - i386_sahf(cd); - i386_mov_imm_reg(cd, 0, d); /* does not affect flags */ - i386_jcc(cd, I386_CC_E, 6 + 3 + 5 + 3); - i386_jcc(cd, I386_CC_B, 3 + 5); - i386_alu_imm_reg(cd, ALU_SUB, 1, d); - i386_jmp_imm(cd, 3); - i386_alu_imm_reg(cd, ALU_ADD, 1, d); - store_reg_to_var_int(iptr->dst, d); + s2 = emit_load_s1(jd, iptr, REG_FTMP1); + s1 = emit_load_s2(jd, iptr, REG_FTMP2); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP1); +/* emit_fxch(cd); */ + emit_fucompp(cd); + emit_fnstsw(cd); + emit_test_imm_reg(cd, 0x400, EAX); /* unordered treat as GT */ + emit_jcc(cd, CC_E, 6); + emit_alu_imm_reg(cd, ALU_AND, 0x000000ff, EAX); + emit_sahf(cd); + emit_mov_imm_reg(cd, 0, d); /* does not affect flags */ + emit_jcc(cd, CC_E, 6 + 3 + 5 + 3); + emit_jcc(cd, CC_B, 3 + 5); + emit_alu_imm_reg(cd, ALU_SUB, 1, d); + emit_jmp_imm(cd, 3); + emit_alu_imm_reg(cd, ALU_ADD, 1, d); + emit_store_dst(jd, iptr, d); break; case ICMD_FCMPG: /* ..., val1, val2 ==> ..., val1 fcmpg val2 */ case ICMD_DCMPG: - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL*/ /* exchanged to skip fxch */ - var_to_reg_flt(s2, src->prev, REG_FTMP1); - var_to_reg_flt(s1, src, REG_FTMP2); - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1); -/* i386_fxch(cd); */ - i386_fucompp(cd); - fpu_st_offset -= 2; - i386_fnstsw(cd); - i386_test_imm_reg(cd, 0x400, EAX); /* unordered treat as LT */ - i386_jcc(cd, I386_CC_E, 3); - i386_movb_imm_reg(cd, 1, REG_AH); - i386_sahf(cd); - i386_mov_imm_reg(cd, 0, d); /* does not affect flags */ - i386_jcc(cd, I386_CC_E, 6 + 3 + 5 + 3); - i386_jcc(cd, I386_CC_B, 3 + 5); - i386_alu_imm_reg(cd, ALU_SUB, 1, d); - i386_jmp_imm(cd, 3); - i386_alu_imm_reg(cd, ALU_ADD, 1, d); - store_reg_to_var_int(iptr->dst, d); + s2 = emit_load_s1(jd, iptr, REG_FTMP1); + s1 = emit_load_s2(jd, iptr, REG_FTMP2); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP1); +/* emit_fxch(cd); */ + emit_fucompp(cd); + emit_fnstsw(cd); + emit_test_imm_reg(cd, 0x400, EAX); /* unordered treat as LT */ + emit_jcc(cd, CC_E, 3); + emit_movb_imm_reg(cd, 1, REG_AH); + emit_sahf(cd); + emit_mov_imm_reg(cd, 0, d); /* does not affect flags */ + emit_jcc(cd, CC_E, 6 + 3 + 5 + 3); + emit_jcc(cd, CC_B, 3 + 5); + emit_alu_imm_reg(cd, ALU_SUB, 1, d); + emit_jmp_imm(cd, 3); + emit_alu_imm_reg(cd, ALU_ADD, 1, d); + emit_store_dst(jd, iptr, d); break; /* memory operations **************************************************/ case ICMD_ARRAYLENGTH: /* ..., arrayref ==> ..., length */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: NO EDX: NO OUTPUT: REG_NULL*/ - var_to_reg_int(s1, src, REG_ITMP1); - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP1); gen_nullptr_check(s1); - i386_mov_membase_reg(cd, s1, OFFSET(java_arrayheader, size), d); - store_reg_to_var_int(iptr->dst, d); + M_ILD(d, s1, OFFSET(java_arrayheader, size)); + emit_store_dst(jd, iptr, d); break; - case ICMD_AALOAD: /* ..., arrayref, index ==> ..., value */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/ + case ICMD_BALOAD: /* ..., arrayref, index ==> ..., value */ - var_to_reg_int(s1, src->prev, REG_ITMP1); - var_to_reg_int(s2, src, REG_ITMP2); - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1); - if (iptr->op1 == 0) { + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP1); + if (INSTRUCTION_MUST_CHECK(iptr)) { gen_nullptr_check(s1); gen_bound_check; } - i386_mov_memindex_reg(cd, OFFSET(java_objectarray, data[0]), s1, s2, 2, d); - store_reg_to_var_int(iptr->dst, d); + emit_movsbl_memindex_reg(cd, OFFSET(java_bytearray, data[0]), s1, s2, 0, d); + emit_store_dst(jd, iptr, d); break; - case ICMD_LALOAD: /* ..., arrayref, index ==> ..., value */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL*/ + case ICMD_CALOAD: /* ..., arrayref, index ==> ..., value */ - var_to_reg_int(s1, src->prev, REG_ITMP1); - var_to_reg_int(s2, src, REG_ITMP2); - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP3); - if (iptr->op1 == 0) { + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP1); + if (INSTRUCTION_MUST_CHECK(iptr)) { gen_nullptr_check(s1); gen_bound_check; } - - if (iptr->dst->flags & INMEMORY) { - i386_mov_memindex_reg(cd, OFFSET(java_longarray, data[0]), s1, s2, 3, REG_ITMP3); - i386_mov_reg_membase(cd, REG_ITMP3, REG_SP, iptr->dst->regoff * 4); - i386_mov_memindex_reg(cd, OFFSET(java_longarray, data[0]) + 4, s1, s2, 3, REG_ITMP3); - i386_mov_reg_membase(cd, REG_ITMP3, REG_SP, iptr->dst->regoff * 4 + 4); - } - break; + emit_movzwl_memindex_reg(cd, OFFSET(java_chararray, data[0]), s1, s2, 1, d); + emit_store_dst(jd, iptr, d); + break; - case ICMD_IALOAD: /* ..., arrayref, index ==> ..., value */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/ + case ICMD_SALOAD: /* ..., arrayref, index ==> ..., value */ - var_to_reg_int(s1, src->prev, REG_ITMP1); - var_to_reg_int(s2, src, REG_ITMP2); - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1); - if (iptr->op1 == 0) { + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP1); + if (INSTRUCTION_MUST_CHECK(iptr)) { gen_nullptr_check(s1); gen_bound_check; } - i386_mov_memindex_reg(cd, OFFSET(java_intarray, data[0]), s1, s2, 2, d); - store_reg_to_var_int(iptr->dst, d); + emit_movswl_memindex_reg(cd, OFFSET(java_shortarray, data[0]), s1, s2, 1, d); + emit_store_dst(jd, iptr, d); break; - case ICMD_FALOAD: /* ..., arrayref, index ==> ..., value */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/ + case ICMD_IALOAD: /* ..., arrayref, index ==> ..., value */ - var_to_reg_int(s1, src->prev, REG_ITMP1); - var_to_reg_int(s2, src, REG_ITMP2); - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP1); - if (iptr->op1 == 0) { + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP1); + if (INSTRUCTION_MUST_CHECK(iptr)) { gen_nullptr_check(s1); gen_bound_check; } - i386_flds_memindex(cd, OFFSET(java_floatarray, data[0]), s1, s2, 2); - fpu_st_offset++; - store_reg_to_var_flt(iptr->dst, d); + emit_mov_memindex_reg(cd, OFFSET(java_intarray, data[0]), s1, s2, 2, d); + emit_store_dst(jd, iptr, d); break; - case ICMD_DALOAD: /* ..., arrayref, index ==> ..., value */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/ + case ICMD_LALOAD: /* ..., arrayref, index ==> ..., value */ - var_to_reg_int(s1, src->prev, REG_ITMP1); - var_to_reg_int(s2, src, REG_ITMP2); - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP3); - if (iptr->op1 == 0) { + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP3); + if (INSTRUCTION_MUST_CHECK(iptr)) { gen_nullptr_check(s1); gen_bound_check; } - i386_fldl_memindex(cd, OFFSET(java_doublearray, data[0]), s1, s2, 3); - fpu_st_offset++; - store_reg_to_var_flt(iptr->dst, d); + assert(IS_INMEMORY(iptr->dst.var->flags)); + emit_mov_memindex_reg(cd, OFFSET(java_longarray, data[0]), s1, s2, 3, REG_ITMP3); + emit_mov_reg_membase(cd, REG_ITMP3, REG_SP, iptr->dst.var->regoff * 4); + emit_mov_memindex_reg(cd, OFFSET(java_longarray, data[0]) + 4, s1, s2, 3, REG_ITMP3); + emit_mov_reg_membase(cd, REG_ITMP3, REG_SP, iptr->dst.var->regoff * 4 + 4); break; - case ICMD_CALOAD: /* ..., arrayref, index ==> ..., value */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/ + case ICMD_FALOAD: /* ..., arrayref, index ==> ..., value */ - var_to_reg_int(s1, src->prev, REG_ITMP1); - var_to_reg_int(s2, src, REG_ITMP2); - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1); - if (iptr->op1 == 0) { + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + d = codegen_reg_of_dst(jd, iptr, REG_FTMP1); + if (INSTRUCTION_MUST_CHECK(iptr)) { gen_nullptr_check(s1); gen_bound_check; } - i386_movzwl_memindex_reg(cd, OFFSET(java_chararray, data[0]), s1, s2, 1, d); - store_reg_to_var_int(iptr->dst, d); - break; + emit_flds_memindex(cd, OFFSET(java_floatarray, data[0]), s1, s2, 2); + emit_store_dst(jd, iptr, d); + break; - case ICMD_SALOAD: /* ..., arrayref, index ==> ..., value */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/ + case ICMD_DALOAD: /* ..., arrayref, index ==> ..., value */ - var_to_reg_int(s1, src->prev, REG_ITMP1); - var_to_reg_int(s2, src, REG_ITMP2); - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1); - if (iptr->op1 == 0) { + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + d = codegen_reg_of_dst(jd, iptr, REG_FTMP3); + if (INSTRUCTION_MUST_CHECK(iptr)) { gen_nullptr_check(s1); gen_bound_check; } - i386_movswl_memindex_reg(cd, OFFSET(java_shortarray, data[0]), s1, s2, 1, d); - store_reg_to_var_int(iptr->dst, d); + emit_fldl_memindex(cd, OFFSET(java_doublearray, data[0]), s1, s2, 3); + emit_store_dst(jd, iptr, d); break; - case ICMD_BALOAD: /* ..., arrayref, index ==> ..., value */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/ + case ICMD_AALOAD: /* ..., arrayref, index ==> ..., value */ - var_to_reg_int(s1, src->prev, REG_ITMP1); - var_to_reg_int(s2, src, REG_ITMP2); - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1); - if (iptr->op1 == 0) { + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP1); + if (INSTRUCTION_MUST_CHECK(iptr)) { gen_nullptr_check(s1); gen_bound_check; } - i386_movsbl_memindex_reg(cd, OFFSET(java_bytearray, data[0]), s1, s2, 0, d); - store_reg_to_var_int(iptr->dst, d); + emit_mov_memindex_reg(cd, OFFSET(java_objectarray, data[0]), s1, s2, 2, d); + emit_store_dst(jd, iptr, d); break; - case ICMD_LASTORE: /* ..., arrayref, index, value ==> ... */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL */ + case ICMD_BASTORE: /* ..., arrayref, index, value ==> ... */ - var_to_reg_int(s1, src->prev->prev, REG_ITMP1); - var_to_reg_int(s2, src->prev, REG_ITMP2); - if (iptr->op1 == 0) { + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + if (INSTRUCTION_MUST_CHECK(iptr)) { gen_nullptr_check(s1); gen_bound_check; } - - if (src->flags & INMEMORY) { - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP3); - i386_mov_reg_memindex(cd, REG_ITMP3, OFFSET(java_longarray, data[0]), s1, s2, 3); - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP3); - i386_mov_reg_memindex(cd, REG_ITMP3, OFFSET(java_longarray, data[0]) + 4, s1, s2, 3); + s3 = emit_load_s3(jd, iptr, REG_ITMP3); + if (s3 >= EBP) { /* because EBP, ESI, EDI have no xH and xL nibbles */ + M_INTMOVE(s3, REG_ITMP3); + s3 = REG_ITMP3; } + emit_movb_reg_memindex(cd, s3, OFFSET(java_bytearray, data[0]), s1, s2, 0); break; - case ICMD_IASTORE: /* ..., arrayref, index, value ==> ... */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL*/ + case ICMD_CASTORE: /* ..., arrayref, index, value ==> ... */ - var_to_reg_int(s1, src->prev->prev, REG_ITMP1); - var_to_reg_int(s2, src->prev, REG_ITMP2); - if (iptr->op1 == 0) { + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + if (INSTRUCTION_MUST_CHECK(iptr)) { gen_nullptr_check(s1); gen_bound_check; } - var_to_reg_int(s3, src, REG_ITMP3); - i386_mov_reg_memindex(cd, s3, OFFSET(java_intarray, data[0]), s1, s2, 2); + s3 = emit_load_s3(jd, iptr, REG_ITMP3); + emit_movw_reg_memindex(cd, s3, OFFSET(java_chararray, data[0]), s1, s2, 1); break; - case ICMD_FASTORE: /* ..., arrayref, index, value ==> ... */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/ + case ICMD_SASTORE: /* ..., arrayref, index, value ==> ... */ - var_to_reg_int(s1, src->prev->prev, REG_ITMP1); - var_to_reg_int(s2, src->prev, REG_ITMP2); - if (iptr->op1 == 0) { + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + if (INSTRUCTION_MUST_CHECK(iptr)) { gen_nullptr_check(s1); gen_bound_check; } - var_to_reg_flt(s3, src, REG_FTMP1); - i386_fstps_memindex(cd, OFFSET(java_floatarray, data[0]), s1, s2, 2); - fpu_st_offset--; + s3 = emit_load_s3(jd, iptr, REG_ITMP3); + emit_movw_reg_memindex(cd, s3, OFFSET(java_shortarray, data[0]), s1, s2, 1); break; - case ICMD_DASTORE: /* ..., arrayref, index, value ==> ... */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/ + case ICMD_IASTORE: /* ..., arrayref, index, value ==> ... */ - var_to_reg_int(s1, src->prev->prev, REG_ITMP1); - var_to_reg_int(s2, src->prev, REG_ITMP2); - if (iptr->op1 == 0) { + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + if (INSTRUCTION_MUST_CHECK(iptr)) { gen_nullptr_check(s1); gen_bound_check; } - var_to_reg_flt(s3, src, REG_FTMP1); - i386_fstpl_memindex(cd, OFFSET(java_doublearray, data[0]), s1, s2, 3); - fpu_st_offset--; + s3 = emit_load_s3(jd, iptr, REG_ITMP3); + emit_mov_reg_memindex(cd, s3, OFFSET(java_intarray, data[0]), s1, s2, 2); break; - case ICMD_CASTORE: /* ..., arrayref, index, value ==> ... */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL*/ + case ICMD_LASTORE: /* ..., arrayref, index, value ==> ... */ - var_to_reg_int(s1, src->prev->prev, REG_ITMP1); - var_to_reg_int(s2, src->prev, REG_ITMP2); - if (iptr->op1 == 0) { + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + if (INSTRUCTION_MUST_CHECK(iptr)) { gen_nullptr_check(s1); gen_bound_check; } - var_to_reg_int(s3, src, REG_ITMP3); - i386_movw_reg_memindex(cd, s3, OFFSET(java_chararray, data[0]), s1, s2, 1); + assert(IS_INMEMORY(iptr->sx.s23.s3.var->flags)); + emit_mov_membase_reg(cd, REG_SP, iptr->sx.s23.s3.var->regoff * 4, REG_ITMP3); + emit_mov_reg_memindex(cd, REG_ITMP3, OFFSET(java_longarray, data[0]), s1, s2, 3); + emit_mov_membase_reg(cd, REG_SP, iptr->sx.s23.s3.var->regoff * 4 + 4, REG_ITMP3); + emit_mov_reg_memindex(cd, REG_ITMP3, OFFSET(java_longarray, data[0]) + 4, s1, s2, 3); break; - case ICMD_SASTORE: /* ..., arrayref, index, value ==> ... */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL*/ + case ICMD_FASTORE: /* ..., arrayref, index, value ==> ... */ - var_to_reg_int(s1, src->prev->prev, REG_ITMP1); - var_to_reg_int(s2, src->prev, REG_ITMP2); - if (iptr->op1 == 0) { + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + if (INSTRUCTION_MUST_CHECK(iptr)) { gen_nullptr_check(s1); gen_bound_check; } - var_to_reg_int(s3, src, REG_ITMP3); - i386_movw_reg_memindex(cd, s3, OFFSET(java_shortarray, data[0]), s1, s2, 1); + s3 = emit_load_s3(jd, iptr, REG_FTMP1); + emit_fstps_memindex(cd, OFFSET(java_floatarray, data[0]), s1, s2, 2); break; - case ICMD_BASTORE: /* ..., arrayref, index, value ==> ... */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL*/ + case ICMD_DASTORE: /* ..., arrayref, index, value ==> ... */ - var_to_reg_int(s1, src->prev->prev, REG_ITMP1); - var_to_reg_int(s2, src->prev, REG_ITMP2); - if (iptr->op1 == 0) { + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + if (INSTRUCTION_MUST_CHECK(iptr)) { gen_nullptr_check(s1); gen_bound_check; } - var_to_reg_int(s3, src, REG_ITMP3); - if (s3 >= EBP) { /* because EBP, ESI, EDI have no xH and xL nibbles */ - M_INTMOVE(s3, REG_ITMP3); - s3 = REG_ITMP3; - } - i386_movb_reg_memindex(cd, s3, OFFSET(java_bytearray, data[0]), s1, s2, 0); + s3 = emit_load_s3(jd, iptr, REG_FTMP1); + emit_fstpl_memindex(cd, OFFSET(java_doublearray, data[0]), s1, s2, 3); break; case ICMD_AASTORE: /* ..., arrayref, index, value ==> ... */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL */ - - var_to_reg_int(s1, src->prev->prev, REG_ITMP1); - var_to_reg_int(s2, src->prev, REG_ITMP2); - if (iptr->op1 == 0) { + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + if (INSTRUCTION_MUST_CHECK(iptr)) { gen_nullptr_check(s1); gen_bound_check; } - var_to_reg_int(s3, src, REG_ITMP3); + s3 = emit_load_s3(jd, iptr, REG_ITMP3); M_AST(s1, REG_SP, 0 * 4); M_AST(s3, REG_SP, 1 * 4); @@ -3126,104 +2484,91 @@ bool codegen(jitdata *jd) M_CALL(REG_ITMP1); M_TEST(REG_RESULT); M_BEQ(0); - codegen_add_arraystoreexception_ref(cd, cd->mcodeptr); + codegen_add_arraystoreexception_ref(cd); - var_to_reg_int(s1, src->prev->prev, REG_ITMP1); - var_to_reg_int(s2, src->prev, REG_ITMP2); - var_to_reg_int(s3, src, REG_ITMP3); - i386_mov_reg_memindex(cd, s3, OFFSET(java_objectarray, data[0]), s1, s2, 2); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + s3 = emit_load_s3(jd, iptr, REG_ITMP3); + emit_mov_reg_memindex(cd, s3, OFFSET(java_objectarray, data[0]), s1, s2, 2); break; - case ICMD_IASTORECONST: /* ..., arrayref, index ==> ... */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/ + case ICMD_BASTORECONST: /* ..., arrayref, index ==> ... */ - var_to_reg_int(s1, src->prev, REG_ITMP1); - var_to_reg_int(s2, src, REG_ITMP2); - if (iptr->op1 == 0) { + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + if (INSTRUCTION_MUST_CHECK(iptr)) { gen_nullptr_check(s1); gen_bound_check; } - i386_mov_imm_memindex(cd, iptr->val.i, OFFSET(java_intarray, data[0]), s1, s2, 2); + emit_movb_imm_memindex(cd, iptr->sx.s23.s3.constval, OFFSET(java_bytearray, data[0]), s1, s2, 0); break; - case ICMD_LASTORECONST: /* ..., arrayref, index ==> ... */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/ + case ICMD_CASTORECONST: /* ..., arrayref, index ==> ... */ - var_to_reg_int(s1, src->prev, REG_ITMP1); - var_to_reg_int(s2, src, REG_ITMP2); - if (iptr->op1 == 0) { + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + if (INSTRUCTION_MUST_CHECK(iptr)) { gen_nullptr_check(s1); gen_bound_check; } - - i386_mov_imm_memindex(cd, (u4) (iptr->val.l & 0x00000000ffffffff), OFFSET(java_longarray, data[0]), s1, s2, 3); - i386_mov_imm_memindex(cd, (u4) (iptr->val.l >> 32), OFFSET(java_longarray, data[0]) + 4, s1, s2, 3); + emit_movw_imm_memindex(cd, iptr->sx.s23.s3.constval, OFFSET(java_chararray, data[0]), s1, s2, 1); break; - case ICMD_AASTORECONST: /* ..., arrayref, index ==> ... */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/ + case ICMD_SASTORECONST: /* ..., arrayref, index ==> ... */ - var_to_reg_int(s1, src->prev, REG_ITMP1); - var_to_reg_int(s2, src, REG_ITMP2); - if (iptr->op1 == 0) { + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + if (INSTRUCTION_MUST_CHECK(iptr)) { gen_nullptr_check(s1); gen_bound_check; } - i386_mov_imm_memindex(cd, 0, OFFSET(java_objectarray, data[0]), s1, s2, 2); + emit_movw_imm_memindex(cd, iptr->sx.s23.s3.constval, OFFSET(java_shortarray, data[0]), s1, s2, 1); break; - case ICMD_BASTORECONST: /* ..., arrayref, index ==> ... */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/ + case ICMD_IASTORECONST: /* ..., arrayref, index ==> ... */ - var_to_reg_int(s1, src->prev, REG_ITMP1); - var_to_reg_int(s2, src, REG_ITMP2); - if (iptr->op1 == 0) { + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + if (INSTRUCTION_MUST_CHECK(iptr)) { gen_nullptr_check(s1); gen_bound_check; } - i386_movb_imm_memindex(cd, iptr->val.i, OFFSET(java_bytearray, data[0]), s1, s2, 0); + emit_mov_imm_memindex(cd, iptr->sx.s23.s3.constval, OFFSET(java_intarray, data[0]), s1, s2, 2); break; - case ICMD_CASTORECONST: /* ..., arrayref, index ==> ... */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/ + case ICMD_LASTORECONST: /* ..., arrayref, index ==> ... */ - var_to_reg_int(s1, src->prev, REG_ITMP1); - var_to_reg_int(s2, src, REG_ITMP2); - if (iptr->op1 == 0) { + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + if (INSTRUCTION_MUST_CHECK(iptr)) { gen_nullptr_check(s1); gen_bound_check; } - i386_movw_imm_memindex(cd, iptr->val.i, OFFSET(java_chararray, data[0]), s1, s2, 1); + emit_mov_imm_memindex(cd, (u4) (iptr->sx.s23.s3.constval & 0x00000000ffffffff), OFFSET(java_longarray, data[0]), s1, s2, 3); + emit_mov_imm_memindex(cd, ((s4)iptr->sx.s23.s3.constval) >> 31, OFFSET(java_longarray, data[0]) + 4, s1, s2, 3); break; - case ICMD_SASTORECONST: /* ..., arrayref, index ==> ... */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: S|YES EDX: NO OUTPUT: REG_NULL*/ + case ICMD_AASTORECONST: /* ..., arrayref, index ==> ... */ - var_to_reg_int(s1, src->prev, REG_ITMP1); - var_to_reg_int(s2, src, REG_ITMP2); - if (iptr->op1 == 0) { + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + if (INSTRUCTION_MUST_CHECK(iptr)) { gen_nullptr_check(s1); gen_bound_check; } - i386_movw_imm_memindex(cd, iptr->val.i, OFFSET(java_shortarray, data[0]), s1, s2, 1); + emit_mov_imm_memindex(cd, 0, OFFSET(java_objectarray, data[0]), s1, s2, 2); break; case ICMD_GETSTATIC: /* ... ==> ..., value */ - /* op1 = type, val.a = field address */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: EAX*/ - if (iptr->val.a == NULL) { - codegen_addpatchref(cd, cd->mcodeptr, - PATCHER_get_putstatic, - (unresolved_field *) iptr->target, 0); + if (INSTRUCTION_IS_UNRESOLVED(iptr)) { + unresolved_field *uf = iptr->sx.s23.s3.uf; + + fieldtype = uf->fieldref->parseddesc.fd->type; + + codegen_addpatchref(cd, PATCHER_get_putstatic, + iptr->sx.s23.s3.uf, 0); if (opt_showdisassemble) { M_NOP; M_NOP; M_NOP; M_NOP; M_NOP; @@ -3231,12 +2576,14 @@ bool codegen(jitdata *jd) disp = 0; - } else { - fieldinfo *fi = iptr->val.a; + } + else { + fieldinfo *fi = iptr->sx.s23.s3.fmiref->p.field; + + fieldtype = fi->type; if (!CLASS_IS_OR_ALMOST_INITIALIZED(fi->class)) { - codegen_addpatchref(cd, cd->mcodeptr, - PATCHER_clinit, fi->class, 0); + codegen_addpatchref(cd, PATCHER_clinit, fi->class, 0); if (opt_showdisassemble) { M_NOP; M_NOP; M_NOP; M_NOP; M_NOP; @@ -3247,51 +2594,37 @@ bool codegen(jitdata *jd) } M_MOV_IMM(disp, REG_ITMP1); - switch (iptr->op1) { + switch (fieldtype) { case TYPE_INT: case TYPE_ADR: - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP2); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP2); M_ILD(d, REG_ITMP1, 0); - store_reg_to_var_int(iptr->dst, d); - break; - case TYPE_LNG: - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - if (iptr->dst->flags & INMEMORY) { - /* Using both REG_ITMP2 and REG_ITMP3 is faster - than only using REG_ITMP2 alternating. */ - i386_mov_membase_reg(cd, REG_ITMP1, 0, REG_ITMP2); - i386_mov_membase_reg(cd, REG_ITMP1, 4, REG_ITMP3); - i386_mov_reg_membase(cd, REG_ITMP2, REG_SP, iptr->dst->regoff * 4); - i386_mov_reg_membase(cd, REG_ITMP3, REG_SP, iptr->dst->regoff * 4 + 4); - } else { - log_text("GETSTATIC: longs have to be in memory"); - assert(0); - } + break; + case TYPE_LNG: + d = codegen_reg_of_dst(jd, iptr, REG_ITMP23_PACKED); + M_LLD(d, REG_ITMP1, 0); break; case TYPE_FLT: - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP1); - i386_flds_membase(cd, REG_ITMP1, 0); - fpu_st_offset++; - store_reg_to_var_flt(iptr->dst, d); + d = codegen_reg_of_dst(jd, iptr, REG_FTMP1); + M_FLD(d, REG_ITMP1, 0); break; case TYPE_DBL: - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP1); - i386_fldl_membase(cd, REG_ITMP1, 0); - fpu_st_offset++; - store_reg_to_var_flt(iptr->dst, d); + d = codegen_reg_of_dst(jd, iptr, REG_FTMP1); + M_DLD(d, REG_ITMP1, 0); break; } + emit_store_dst(jd, iptr, d); break; case ICMD_PUTSTATIC: /* ..., value ==> ... */ - /* op1 = type, val.a = field address */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL*/ - if (iptr->val.a == NULL) { - codegen_addpatchref(cd, cd->mcodeptr, - PATCHER_get_putstatic, - (unresolved_field *) iptr->target, 0); + if (INSTRUCTION_IS_UNRESOLVED(iptr)) { + unresolved_field *uf = iptr->sx.s23.s3.uf; + + fieldtype = uf->fieldref->parseddesc.fd->type; + + codegen_addpatchref(cd, PATCHER_get_putstatic, + iptr->sx.s23.s3.uf, 0); if (opt_showdisassemble) { M_NOP; M_NOP; M_NOP; M_NOP; M_NOP; @@ -3299,12 +2632,14 @@ bool codegen(jitdata *jd) disp = 0; - } else { - fieldinfo *fi = iptr->val.a; + } + else { + fieldinfo *fi = iptr->sx.s23.s3.fmiref->p.field; + + fieldtype = fi->type; if (!CLASS_IS_OR_ALMOST_INITIALIZED(fi->class)) { - codegen_addpatchref(cd, cd->mcodeptr, - PATCHER_clinit, fi->class, 0); + codegen_addpatchref(cd, PATCHER_clinit, fi->class, 0); if (opt_showdisassemble) { M_NOP; M_NOP; M_NOP; M_NOP; M_NOP; @@ -3315,51 +2650,38 @@ bool codegen(jitdata *jd) } M_MOV_IMM(disp, REG_ITMP1); - switch (iptr->op1) { + switch (fieldtype) { case TYPE_INT: case TYPE_ADR: - var_to_reg_int(s2, src, REG_ITMP2); - M_IST(s2, REG_ITMP1, 0); + s1 = emit_load_s1(jd, iptr, REG_ITMP2); + M_IST(s1, REG_ITMP1, 0); break; case TYPE_LNG: - if (src->flags & INMEMORY) { - /* Using both REG_ITMP2 and REG_ITMP3 is faster - than only using REG_ITMP2 alternating. */ - s2 = src->regoff; - - i386_mov_membase_reg(cd, REG_SP, s2 * 4, REG_ITMP2); - i386_mov_membase_reg(cd, REG_SP, s2 * 4 + 4, REG_ITMP3); - i386_mov_reg_membase(cd, REG_ITMP2, REG_ITMP1, 0); - i386_mov_reg_membase(cd, REG_ITMP3, REG_ITMP1, 4); - } else { - log_text("PUTSTATIC: longs have to be in memory"); - assert(0); - } + s1 = emit_load_s1(jd, iptr, REG_ITMP23_PACKED); + M_LST(s1, REG_ITMP1, 0); break; case TYPE_FLT: - var_to_reg_flt(s2, src, REG_FTMP1); - i386_fstps_membase(cd, REG_ITMP1, 0); - fpu_st_offset--; + s1 = emit_load_s1(jd, iptr, REG_FTMP1); + emit_fstps_membase(cd, REG_ITMP1, 0); break; case TYPE_DBL: - var_to_reg_flt(s2, src, REG_FTMP1); - i386_fstpl_membase(cd, REG_ITMP1, 0); - fpu_st_offset--; + s1 = emit_load_s1(jd, iptr, REG_FTMP1); + emit_fstpl_membase(cd, REG_ITMP1, 0); break; } break; case ICMD_PUTSTATICCONST: /* ... ==> ... */ /* val = value (in current instruction) */ - /* op1 = type, val.a = field address (in */ /* following NOP) */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL*/ - if (iptr[1].val.a == NULL) { - codegen_addpatchref(cd, cd->mcodeptr, - PATCHER_get_putstatic, - (unresolved_field *) iptr[1].target, 0); + if (INSTRUCTION_IS_UNRESOLVED(iptr)) { + unresolved_field *uf = iptr->sx.s23.s3.uf; + + fieldtype = uf->fieldref->parseddesc.fd->type; + + codegen_addpatchref(cd, PATCHER_get_putstatic, + uf, 0); if (opt_showdisassemble) { M_NOP; M_NOP; M_NOP; M_NOP; M_NOP; @@ -3367,12 +2689,14 @@ bool codegen(jitdata *jd) disp = 0; - } else { - fieldinfo *fi = iptr[1].val.a; + } + else { + fieldinfo *fi = iptr->sx.s23.s3.fmiref->p.field; + + fieldtype = fi->type; if (!CLASS_IS_OR_ALMOST_INITIALIZED(fi->class)) { - codegen_addpatchref(cd, cd->mcodeptr, - PATCHER_clinit, fi->class, 0); + codegen_addpatchref(cd, PATCHER_clinit, fi->class, 0); if (opt_showdisassemble) { M_NOP; M_NOP; M_NOP; M_NOP; M_NOP; @@ -3383,32 +2707,32 @@ bool codegen(jitdata *jd) } M_MOV_IMM(disp, REG_ITMP1); - switch (iptr[1].op1) { + switch (fieldtype) { case TYPE_INT: - case TYPE_FLT: case TYPE_ADR: - i386_mov_imm_membase(cd, iptr->val.i, REG_ITMP1, 0); + M_IST_IMM(iptr->sx.s23.s2.constval, REG_ITMP1, 0); break; case TYPE_LNG: - case TYPE_DBL: - i386_mov_imm_membase(cd, iptr->val.l, REG_ITMP1, 0); - i386_mov_imm_membase(cd, iptr->val.l >> 32, REG_ITMP1, 4); + M_IST_IMM(iptr->sx.s23.s2.constval & 0xffffffff, REG_ITMP1, 0); + M_IST_IMM(((s4)iptr->sx.s23.s2.constval) >> 31, REG_ITMP1, 4); break; + default: + assert(0); } break; case ICMD_GETFIELD: /* .., objectref. ==> ..., value */ - /* op1 = type, val.i = field offset */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL */ - var_to_reg_int(s1, src, REG_ITMP1); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); gen_nullptr_check(s1); - if (iptr->val.a == NULL) { - codegen_addpatchref(cd, cd->mcodeptr, - PATCHER_getfield, - (unresolved_field *) iptr->target, 0); + if (INSTRUCTION_IS_UNRESOLVED(iptr)) { + unresolved_field *uf = iptr->sx.s23.s3.uf; + + fieldtype = uf->fieldref->parseddesc.fd->type; + + codegen_addpatchref(cd, PATCHER_getfield, + iptr->sx.s23.s3.uf, 0); if (opt_showdisassemble) { M_NOP; M_NOP; M_NOP; M_NOP; M_NOP; @@ -3416,59 +2740,67 @@ bool codegen(jitdata *jd) disp = 0; - } else { - disp = ((fieldinfo *) (iptr->val.a))->offset; + } + else { + fieldinfo *fi = iptr->sx.s23.s3.fmiref->p.field; + + fieldtype = fi->type; + disp = fi->offset; } - switch (iptr->op1) { + switch (fieldtype) { case TYPE_INT: case TYPE_ADR: - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP2); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP2); M_ILD32(d, s1, disp); - store_reg_to_var_int(iptr->dst, d); break; case TYPE_LNG: - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, PACK_REGS(REG_ITMP2, REG_ITMP3)); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP23_PACKED); M_LLD32(d, s1, disp); - store_reg_to_var_lng(iptr->dst, d); break; case TYPE_FLT: - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP1); - i386_flds_membase32(cd, s1, disp); - fpu_st_offset++; - store_reg_to_var_flt(iptr->dst, d); + d = codegen_reg_of_dst(jd, iptr, REG_FTMP1); + M_FLD32(d, s1, disp); break; case TYPE_DBL: - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP1); - i386_fldl_membase32(cd, s1, disp); - fpu_st_offset++; - store_reg_to_var_flt(iptr->dst, d); + d = codegen_reg_of_dst(jd, iptr, REG_FTMP1); + M_DLD32(d, s1, disp); break; } + emit_store_dst(jd, iptr, d); break; case ICMD_PUTFIELD: /* ..., objectref, value ==> ... */ - /* op1 = type, val.a = field address */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL*/ - var_to_reg_int(s1, src->prev, REG_ITMP1); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); gen_nullptr_check(s1); /* must be done here because of code patching */ - if (!IS_FLT_DBL_TYPE(iptr->op1)) { - if (IS_2_WORD_TYPE(iptr->op1)) - var_to_reg_lng(s2, src, PACK_REGS(REG_ITMP2, REG_ITMP3)); + if (INSTRUCTION_IS_UNRESOLVED(iptr)) { + unresolved_field *uf = iptr->sx.s23.s3.uf; + + fieldtype = uf->fieldref->parseddesc.fd->type; + } + else { + fieldinfo *fi = iptr->sx.s23.s3.fmiref->p.field; + + fieldtype = fi->type; + } + + if (!IS_FLT_DBL_TYPE(fieldtype)) { + if (IS_2_WORD_TYPE(fieldtype)) + s2 = emit_load_s2(jd, iptr, REG_ITMP23_PACKED); else - var_to_reg_int(s2, src, REG_ITMP2); - } else - var_to_reg_flt(s2, src, REG_FTMP2); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + } + else + s2 = emit_load_s2(jd, iptr, REG_FTMP2); + + if (INSTRUCTION_IS_UNRESOLVED(iptr)) { + unresolved_field *uf = iptr->sx.s23.s3.uf; - if (iptr->val.a == NULL) { - codegen_addpatchref(cd, cd->mcodeptr, - PATCHER_putfield, - (unresolved_field *) iptr->target, 0); + codegen_addpatchref(cd, PATCHER_putfield, uf, 0); if (opt_showdisassemble) { M_NOP; M_NOP; M_NOP; M_NOP; M_NOP; @@ -3476,11 +2808,14 @@ bool codegen(jitdata *jd) disp = 0; - } else { - disp = ((fieldinfo *) (iptr->val.a))->offset; + } + else { + fieldinfo *fi = iptr->sx.s23.s3.fmiref->p.field; + + disp = fi->offset; } - switch (iptr->op1) { + switch (fieldtype) { case TYPE_INT: case TYPE_ADR: M_IST32(s2, s1, disp); @@ -3489,30 +2824,28 @@ bool codegen(jitdata *jd) M_LST32(s2, s1, disp); break; case TYPE_FLT: - i386_fstps_membase32(cd, s1, disp); - fpu_st_offset--; + emit_fstps_membase32(cd, s1, disp); break; case TYPE_DBL: - i386_fstpl_membase32(cd, s1, disp); - fpu_st_offset--; + emit_fstpl_membase32(cd, s1, disp); break; } break; case ICMD_PUTFIELDCONST: /* ..., objectref ==> ... */ /* val = value (in current instruction) */ - /* op1 = type, val.a = field address (in */ /* following NOP) */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: S|YES EDX: S|YES OUTPUT: REG_NULL*/ - var_to_reg_int(s1, src, REG_ITMP1); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); gen_nullptr_check(s1); - if (iptr[1].val.a == NULL) { - codegen_addpatchref(cd, cd->mcodeptr, - PATCHER_putfieldconst, - (unresolved_field *) iptr[1].target, 0); + if (INSTRUCTION_IS_UNRESOLVED(iptr)) { + unresolved_field *uf = iptr->sx.s23.s3.uf; + + fieldtype = uf->fieldref->parseddesc.fd->type; + + codegen_addpatchref(cd, PATCHER_putfieldconst, + uf, 0); if (opt_showdisassemble) { M_NOP; M_NOP; M_NOP; M_NOP; M_NOP; @@ -3520,20 +2853,27 @@ bool codegen(jitdata *jd) disp = 0; - } else { - disp = ((fieldinfo *) (iptr[1].val.a))->offset; } + else + { + fieldinfo *fi = iptr->sx.s23.s3.fmiref->p.field; + + fieldtype = fi->type; + disp = fi->offset; + } + - switch (iptr[1].op1) { + switch (fieldtype) { case TYPE_INT: - case TYPE_FLT: case TYPE_ADR: - M_IST32_IMM(iptr->val.i, s1, disp); + M_IST32_IMM(iptr->sx.s23.s2.constval, s1, disp); break; case TYPE_LNG: - case TYPE_DBL: - M_LST32_IMM(iptr->val.l, s1, disp); + M_IST32_IMM(iptr->sx.s23.s2.constval & 0xffffffff, s1, disp); + M_IST32_IMM(((s4)iptr->sx.s23.s2.constval) >> 31, s1, disp + 4); break; + default: + assert(0); } break; @@ -3541,17 +2881,14 @@ bool codegen(jitdata *jd) /* branch operations **************************************************/ case ICMD_ATHROW: /* ..., objectref ==> ... (, objectref) */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL */ - var_to_reg_int(s1, src, REG_ITMP1); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); M_INTMOVE(s1, REG_ITMP1_XPTR); #ifdef ENABLE_VERIFIER - if (iptr->val.a) { - codegen_addpatchref(cd, cd->mcodeptr, - PATCHER_athrow_areturn, - (unresolved_class *) iptr->val.a, 0); + if (INSTRUCTION_IS_UNRESOLVED(iptr)) { + codegen_addpatchref(cd, PATCHER_athrow_areturn, + iptr->sx.s23.s2.uc, 0); if (opt_showdisassemble) { M_NOP; M_NOP; M_NOP; M_NOP; M_NOP; @@ -3567,651 +2904,376 @@ bool codegen(jitdata *jd) break; case ICMD_INLINE_GOTO: - - M_COPY(src,iptr->dst); +#if 0 + M_COPY(src, iptr->dst.var); +#endif /* FALLTHROUGH! */ case ICMD_GOTO: /* ... ==> ... */ - /* op1 = target JavaVM pc */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ +#if defined(ENABLE_SSA) + if ( ls != NULL ) { + last_cmd_was_goto = true; + /* In case of a Goto phimoves have to be inserted before the */ + /* jump */ + codegen_insert_phi_moves(cd, rd, ls, bptr); + } +#endif M_JMP_IMM(0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); + codegen_addreference(cd, iptr->dst.block); ALIGNCODENOP; break; case ICMD_JSR: /* ... ==> ... */ - /* op1 = target JavaVM pc */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ M_CALL_IMM(0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); + codegen_addreference(cd, iptr->sx.s23.s3.jsrtarget.block); break; case ICMD_RET: /* ... ==> ... */ - /* op1 = local variable */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ + /* s1.localindex = local variable */ - var = &(rd->locals[iptr->op1][TYPE_ADR]); - var_to_reg_int(s1, var, REG_ITMP1); - i386_jmp_reg(cd, s1); + var = &(rd->locals[iptr->s1.localindex][TYPE_ADR]); + if (IS_INMEMORY(var->flags)) { + M_ALD(REG_ITMP1, REG_SP, var->regoff * 4); + M_JMP(REG_ITMP1); + } + else + M_JMP(var->regoff); break; case ICMD_IFNULL: /* ..., value ==> ... */ - /* op1 = target JavaVM pc */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ - if (src->flags & INMEMORY) { - i386_alu_imm_membase(cd, ALU_CMP, 0, REG_SP, src->regoff * 4); - - } else { - i386_test_reg_reg(cd, src->regoff, src->regoff); - } - i386_jcc(cd, I386_CC_E, 0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + M_TEST(s1); + M_BEQ(0); + codegen_addreference(cd, iptr->dst.block); break; case ICMD_IFNONNULL: /* ..., value ==> ... */ - /* op1 = target JavaVM pc */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ - if (src->flags & INMEMORY) { - i386_alu_imm_membase(cd, ALU_CMP, 0, REG_SP, src->regoff * 4); - - } else { - i386_test_reg_reg(cd, src->regoff, src->regoff); - } - i386_jcc(cd, I386_CC_NE, 0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + M_TEST(s1); + M_BNE(0); + codegen_addreference(cd, iptr->dst.block); break; case ICMD_IFEQ: /* ..., value ==> ... */ - /* op1 = target JavaVM pc, val.i = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ - - if (src->flags & INMEMORY) { - i386_alu_imm_membase(cd, ALU_CMP, iptr->val.i, REG_SP, src->regoff * 4); - } else { - i386_alu_imm_reg(cd, ALU_CMP, iptr->val.i, src->regoff); - } - i386_jcc(cd, I386_CC_E, 0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + M_CMP_IMM(iptr->sx.val.i, s1); + M_BEQ(0); + codegen_addreference(cd, iptr->dst.block); break; case ICMD_IFLT: /* ..., value ==> ... */ - /* op1 = target JavaVM pc, val.i = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ - - if (src->flags & INMEMORY) { - i386_alu_imm_membase(cd, ALU_CMP, iptr->val.i, REG_SP, src->regoff * 4); - } else { - i386_alu_imm_reg(cd, ALU_CMP, iptr->val.i, src->regoff); - } - i386_jcc(cd, I386_CC_L, 0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + M_CMP_IMM(iptr->sx.val.i, s1); + M_BLT(0); + codegen_addreference(cd, iptr->dst.block); break; case ICMD_IFLE: /* ..., value ==> ... */ - /* op1 = target JavaVM pc, val.i = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ - if (src->flags & INMEMORY) { - i386_alu_imm_membase(cd, ALU_CMP, iptr->val.i, REG_SP, src->regoff * 4); - - } else { - i386_alu_imm_reg(cd, ALU_CMP, iptr->val.i, src->regoff); - } - i386_jcc(cd, I386_CC_LE, 0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + M_CMP_IMM(iptr->sx.val.i, s1); + M_BLE(0); + codegen_addreference(cd, iptr->dst.block); break; case ICMD_IFNE: /* ..., value ==> ... */ - /* op1 = target JavaVM pc, val.i = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ - if (src->flags & INMEMORY) { - i386_alu_imm_membase(cd, ALU_CMP, iptr->val.i, REG_SP, src->regoff * 4); - - } else { - i386_alu_imm_reg(cd, ALU_CMP, iptr->val.i, src->regoff); - } - i386_jcc(cd, I386_CC_NE, 0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + M_CMP_IMM(iptr->sx.val.i, s1); + M_BNE(0); + codegen_addreference(cd, iptr->dst.block); break; case ICMD_IFGT: /* ..., value ==> ... */ - /* op1 = target JavaVM pc, val.i = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ - - if (src->flags & INMEMORY) { - i386_alu_imm_membase(cd, ALU_CMP, iptr->val.i, REG_SP, src->regoff * 4); - } else { - i386_alu_imm_reg(cd, ALU_CMP, iptr->val.i, src->regoff); - } - i386_jcc(cd, I386_CC_G, 0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + M_CMP_IMM(iptr->sx.val.i, s1); + M_BGT(0); + codegen_addreference(cd, iptr->dst.block); break; case ICMD_IFGE: /* ..., value ==> ... */ - /* op1 = target JavaVM pc, val.i = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ - - if (src->flags & INMEMORY) { - i386_alu_imm_membase(cd, ALU_CMP, iptr->val.i, REG_SP, src->regoff * 4); - } else { - i386_alu_imm_reg(cd, ALU_CMP, iptr->val.i, src->regoff); - } - i386_jcc(cd, I386_CC_GE, 0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + M_CMP_IMM(iptr->sx.val.i, s1); + M_BGE(0); + codegen_addreference(cd, iptr->dst.block); break; case ICMD_IF_LEQ: /* ..., value ==> ... */ - /* op1 = target JavaVM pc, val.l = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ - - if (src->flags & INMEMORY) { - if (iptr->val.l == 0) { - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1); - i386_alu_membase_reg(cd, ALU_OR, REG_SP, src->regoff * 4 + 4, REG_ITMP1); - } else { - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_ITMP2); - i386_alu_imm_reg(cd, ALU_XOR, iptr->val.l >> 32, REG_ITMP2); - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1); - i386_alu_imm_reg(cd, ALU_XOR, iptr->val.l, REG_ITMP1); - i386_alu_reg_reg(cd, ALU_OR, REG_ITMP2, REG_ITMP1); - } + s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED); + if (iptr->sx.val.l == 0) { + M_INTMOVE(GET_LOW_REG(s1), REG_ITMP1); + M_OR(GET_HIGH_REG(s1), REG_ITMP1); + } + else { + M_LNGMOVE(s1, REG_ITMP12_PACKED); + M_XOR_IMM(iptr->sx.val.l, REG_ITMP1); + M_XOR_IMM(iptr->sx.val.l >> 32, REG_ITMP2); + M_OR(REG_ITMP2, REG_ITMP1); } - i386_test_reg_reg(cd, REG_ITMP1, REG_ITMP1); - i386_jcc(cd, I386_CC_E, 0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); + M_BEQ(0); + codegen_addreference(cd, iptr->dst.block); break; case ICMD_IF_LLT: /* ..., value ==> ... */ - /* op1 = target JavaVM pc, val.l = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ - - if (src->flags & INMEMORY) { - i386_alu_imm_membase(cd, ALU_CMP, iptr->val.l >> 32, REG_SP, src->regoff * 4 + 4); - i386_jcc(cd, I386_CC_L, 0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); - - disp = 3 + 6; - CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4); - CALCIMMEDIATEBYTES(disp, iptr->val.l); - - i386_jcc(cd, I386_CC_G, disp); - i386_alu_imm_membase(cd, ALU_CMP, iptr->val.l, REG_SP, src->regoff * 4); - i386_jcc(cd, I386_CC_B, 0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); + if (iptr->sx.val.l == 0) { + /* If high 32-bit are less than zero, then the 64-bits + are too. */ + s1 = emit_load_s1_high(jd, iptr, REG_ITMP2); + M_CMP_IMM(0, s1); + M_BLT(0); + } + else { + s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED); + M_CMP_IMM(iptr->sx.val.l >> 32, GET_HIGH_REG(s1)); + M_BLT(0); + codegen_addreference(cd, iptr->dst.block); + M_BGT(6 + 6); + M_CMP_IMM32(iptr->sx.val.l, GET_LOW_REG(s1)); + M_BB(0); } + codegen_addreference(cd, iptr->dst.block); break; case ICMD_IF_LLE: /* ..., value ==> ... */ - /* op1 = target JavaVM pc, val.l = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ - - if (src->flags & INMEMORY) { - i386_alu_imm_membase(cd, ALU_CMP, iptr->val.l >> 32, REG_SP, src->regoff * 4 + 4); - i386_jcc(cd, I386_CC_L, 0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); - - disp = 3 + 6; - CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4); - CALCIMMEDIATEBYTES(disp, iptr->val.l); - - i386_jcc(cd, I386_CC_G, disp); - i386_alu_imm_membase(cd, ALU_CMP, iptr->val.l, REG_SP, src->regoff * 4); - i386_jcc(cd, I386_CC_BE, 0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); - } + s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED); + M_CMP_IMM(iptr->sx.val.l >> 32, GET_HIGH_REG(s1)); + M_BLT(0); + codegen_addreference(cd, iptr->dst.block); + M_BGT(6 + 6); + M_CMP_IMM32(iptr->sx.val.l, GET_LOW_REG(s1)); + M_BBE(0); + codegen_addreference(cd, iptr->dst.block); break; case ICMD_IF_LNE: /* ..., value ==> ... */ - /* op1 = target JavaVM pc, val.l = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ - if (src->flags & INMEMORY) { - if (iptr->val.l == 0) { - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1); - i386_alu_membase_reg(cd, ALU_OR, REG_SP, src->regoff * 4 + 4, REG_ITMP1); - - } else { - i386_mov_imm_reg(cd, iptr->val.l, REG_ITMP1); - i386_alu_membase_reg(cd, ALU_XOR, REG_SP, src->regoff * 4, REG_ITMP1); - i386_mov_imm_reg(cd, iptr->val.l >> 32, REG_ITMP2); - i386_alu_membase_reg(cd, ALU_XOR, REG_SP, src->regoff * 4 + 4, REG_ITMP2); - i386_alu_reg_reg(cd, ALU_OR, REG_ITMP2, REG_ITMP1); - } + s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED); + if (iptr->sx.val.l == 0) { + M_INTMOVE(GET_LOW_REG(s1), REG_ITMP1); + M_OR(GET_HIGH_REG(s1), REG_ITMP1); + } + else { + M_LNGMOVE(s1, REG_ITMP12_PACKED); + M_XOR_IMM(iptr->sx.val.l, REG_ITMP1); + M_XOR_IMM(iptr->sx.val.l >> 32, REG_ITMP2); + M_OR(REG_ITMP2, REG_ITMP1); } - i386_test_reg_reg(cd, REG_ITMP1, REG_ITMP1); - i386_jcc(cd, I386_CC_NE, 0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); + M_BNE(0); + codegen_addreference(cd, iptr->dst.block); break; case ICMD_IF_LGT: /* ..., value ==> ... */ - /* op1 = target JavaVM pc, val.l = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ - - if (src->flags & INMEMORY) { - i386_alu_imm_membase(cd, ALU_CMP, iptr->val.l >> 32, REG_SP, src->regoff * 4 + 4); - i386_jcc(cd, I386_CC_G, 0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); - disp = 3 + 6; - CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4); - CALCIMMEDIATEBYTES(disp, iptr->val.l); - - i386_jcc(cd, I386_CC_L, disp); - - i386_alu_imm_membase(cd, ALU_CMP, iptr->val.l, REG_SP, src->regoff * 4); - i386_jcc(cd, I386_CC_A, 0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); - } + s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED); + M_CMP_IMM(iptr->sx.val.l >> 32, GET_HIGH_REG(s1)); + M_BGT(0); + codegen_addreference(cd, iptr->dst.block); + M_BLT(6 + 6); + M_CMP_IMM32(iptr->sx.val.l, GET_LOW_REG(s1)); + M_BA(0); + codegen_addreference(cd, iptr->dst.block); break; case ICMD_IF_LGE: /* ..., value ==> ... */ - /* op1 = target JavaVM pc, val.l = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ - if (src->flags & INMEMORY) { - i386_alu_imm_membase(cd, ALU_CMP, iptr->val.l >> 32, REG_SP, src->regoff * 4 + 4); - i386_jcc(cd, I386_CC_G, 0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); - - disp = 3 + 6; - CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4); - CALCIMMEDIATEBYTES(disp, iptr->val.l); - - i386_jcc(cd, I386_CC_L, disp); - - i386_alu_imm_membase(cd, ALU_CMP, iptr->val.l, REG_SP, src->regoff * 4); - i386_jcc(cd, I386_CC_AE, 0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); - } + if (iptr->sx.val.l == 0) { + /* If high 32-bit are greater equal zero, then the + 64-bits are too. */ + s1 = emit_load_s1_high(jd, iptr, REG_ITMP2); + M_CMP_IMM(0, s1); + M_BGE(0); + } + else { + s1 = emit_load_s1(jd, iptr, REG_ITMP12_PACKED); + M_CMP_IMM(iptr->sx.val.l >> 32, GET_HIGH_REG(s1)); + M_BGT(0); + codegen_addreference(cd, iptr->dst.block); + M_BLT(6 + 6); + M_CMP_IMM32(iptr->sx.val.l, GET_LOW_REG(s1)); + M_BAE(0); + } + codegen_addreference(cd, iptr->dst.block); break; case ICMD_IF_ICMPEQ: /* ..., value, value ==> ... */ case ICMD_IF_ACMPEQ: /* op1 = target JavaVM pc */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ - - if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) { - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1); - i386_alu_reg_membase(cd, ALU_CMP, REG_ITMP1, REG_SP, src->prev->regoff * 4); - - } else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) { - i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4, src->prev->regoff); - - } else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) { - i386_alu_reg_membase(cd, ALU_CMP, src->regoff, REG_SP, src->prev->regoff * 4); - } else { - i386_alu_reg_reg(cd, ALU_CMP, src->regoff, src->prev->regoff); - } - i386_jcc(cd, I386_CC_E, 0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + M_CMP(s2, s1); + M_BEQ(0); + codegen_addreference(cd, iptr->dst.block); break; case ICMD_IF_LCMPEQ: /* ..., value, value ==> ... */ - /* op1 = target JavaVM pc */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ - - if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) { - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1); - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP2); - i386_alu_membase_reg(cd, ALU_XOR, REG_SP, src->regoff * 4, REG_ITMP1); - i386_alu_membase_reg(cd, ALU_XOR, REG_SP, src->regoff * 4 + 4, REG_ITMP2); - i386_alu_reg_reg(cd, ALU_OR, REG_ITMP2, REG_ITMP1); - i386_test_reg_reg(cd, REG_ITMP1, REG_ITMP1); - } - i386_jcc(cd, I386_CC_E, 0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); + + s1 = emit_load_s1_low(jd, iptr, REG_ITMP1); + s2 = emit_load_s2_low(jd, iptr, REG_ITMP2); + M_INTMOVE(s1, REG_ITMP1); + M_XOR(s2, REG_ITMP1); + s1 = emit_load_s1_high(jd, iptr, REG_ITMP2); + s2 = emit_load_s2_high(jd, iptr, REG_ITMP3); + M_INTMOVE(s1, REG_ITMP2); + M_XOR(s2, REG_ITMP2); + M_OR(REG_ITMP1, REG_ITMP2); + M_BEQ(0); + codegen_addreference(cd, iptr->dst.block); break; case ICMD_IF_ICMPNE: /* ..., value, value ==> ... */ case ICMD_IF_ACMPNE: /* op1 = target JavaVM pc */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ - - if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) { - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1); - i386_alu_reg_membase(cd, ALU_CMP, REG_ITMP1, REG_SP, src->prev->regoff * 4); - - } else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) { - i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4, src->prev->regoff); - } else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) { - i386_alu_reg_membase(cd, ALU_CMP, src->regoff, REG_SP, src->prev->regoff * 4); - - } else { - i386_alu_reg_reg(cd, ALU_CMP, src->regoff, src->prev->regoff); - } - i386_jcc(cd, I386_CC_NE, 0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + M_CMP(s2, s1); + M_BNE(0); + codegen_addreference(cd, iptr->dst.block); break; case ICMD_IF_LCMPNE: /* ..., value, value ==> ... */ - /* op1 = target JavaVM pc */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ - - if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) { - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1); - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP2); - i386_alu_membase_reg(cd, ALU_XOR, REG_SP, src->regoff * 4, REG_ITMP1); - i386_alu_membase_reg(cd, ALU_XOR, REG_SP, src->regoff * 4 + 4, REG_ITMP2); - i386_alu_reg_reg(cd, ALU_OR, REG_ITMP2, REG_ITMP1); - i386_test_reg_reg(cd, REG_ITMP1, REG_ITMP1); - } - i386_jcc(cd, I386_CC_NE, 0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); + + s1 = emit_load_s1_low(jd, iptr, REG_ITMP1); + s2 = emit_load_s2_low(jd, iptr, REG_ITMP2); + M_INTMOVE(s1, REG_ITMP1); + M_XOR(s2, REG_ITMP1); + s1 = emit_load_s1_high(jd, iptr, REG_ITMP2); + s2 = emit_load_s2_high(jd, iptr, REG_ITMP3); + M_INTMOVE(s1, REG_ITMP2); + M_XOR(s2, REG_ITMP2); + M_OR(REG_ITMP1, REG_ITMP2); + M_BNE(0); + codegen_addreference(cd, iptr->dst.block); break; case ICMD_IF_ICMPLT: /* ..., value, value ==> ... */ - /* op1 = target JavaVM pc */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ - - if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) { - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1); - i386_alu_reg_membase(cd, ALU_CMP, REG_ITMP1, REG_SP, src->prev->regoff * 4); - - } else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) { - i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4, src->prev->regoff); - - } else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) { - i386_alu_reg_membase(cd, ALU_CMP, src->regoff, REG_SP, src->prev->regoff * 4); - } else { - i386_alu_reg_reg(cd, ALU_CMP, src->regoff, src->prev->regoff); - } - i386_jcc(cd, I386_CC_L, 0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + M_CMP(s2, s1); + M_BLT(0); + codegen_addreference(cd, iptr->dst.block); break; case ICMD_IF_LCMPLT: /* ..., value, value ==> ... */ - /* op1 = target JavaVM pc */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ - - if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) { - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP1); - i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4 + 4, REG_ITMP1); - M_BLT(0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); - disp = 3 + 3 + 6; - CALCOFFSETBYTES(disp, REG_SP, src->prev->regoff * 4); - CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4); - - M_BGT(disp); - - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1); - i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4, REG_ITMP1); - i386_jcc(cd, I386_CC_B, 0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); - } + s1 = emit_load_s1_high(jd, iptr, REG_ITMP1); + s2 = emit_load_s2_high(jd, iptr, REG_ITMP2); + M_CMP(s2, s1); + M_BLT(0); + codegen_addreference(cd, iptr->dst.block); + s1 = emit_load_s1_low(jd, iptr, REG_ITMP1); + s2 = emit_load_s2_low(jd, iptr, REG_ITMP2); + M_BGT(2 + 6); + M_CMP(s2, s1); + M_BB(0); + codegen_addreference(cd, iptr->dst.block); break; case ICMD_IF_ICMPGT: /* ..., value, value ==> ... */ - /* op1 = target JavaVM pc */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ - - if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) { - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1); - i386_alu_reg_membase(cd, ALU_CMP, REG_ITMP1, REG_SP, src->prev->regoff * 4); - } else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) { - i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4, src->prev->regoff); - - } else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) { - i386_alu_reg_membase(cd, ALU_CMP, src->regoff, REG_SP, src->prev->regoff * 4); - - } else { - i386_alu_reg_reg(cd, ALU_CMP, src->regoff, src->prev->regoff); - } + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + M_CMP(s2, s1); M_BGT(0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); + codegen_addreference(cd, iptr->dst.block); break; case ICMD_IF_LCMPGT: /* ..., value, value ==> ... */ - /* op1 = target JavaVM pc */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ - if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) { - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP1); - i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4 + 4, REG_ITMP1); - M_BGT(0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); - - disp = 3 + 3 + 6; - CALCOFFSETBYTES(disp, REG_SP, src->prev->regoff * 4); - CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4); - - M_BLT(disp); - - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1); - i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4, REG_ITMP1); - i386_jcc(cd, I386_CC_A, 0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); - } + s1 = emit_load_s1_high(jd, iptr, REG_ITMP1); + s2 = emit_load_s2_high(jd, iptr, REG_ITMP2); + M_CMP(s2, s1); + M_BGT(0); + codegen_addreference(cd, iptr->dst.block); + s1 = emit_load_s1_low(jd, iptr, REG_ITMP1); + s2 = emit_load_s2_low(jd, iptr, REG_ITMP2); + M_BLT(2 + 6); + M_CMP(s2, s1); + M_BA(0); + codegen_addreference(cd, iptr->dst.block); break; case ICMD_IF_ICMPLE: /* ..., value, value ==> ... */ - /* op1 = target JavaVM pc */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ - - if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) { - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1); - i386_alu_reg_membase(cd, ALU_CMP, REG_ITMP1, REG_SP, src->prev->regoff * 4); - - } else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) { - i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4, src->prev->regoff); - } else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) { - i386_alu_reg_membase(cd, ALU_CMP, src->regoff, REG_SP, src->prev->regoff * 4); - - } else { - i386_alu_reg_reg(cd, ALU_CMP, src->regoff, src->prev->regoff); - } + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + M_CMP(s2, s1); M_BLE(0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); + codegen_addreference(cd, iptr->dst.block); break; case ICMD_IF_LCMPLE: /* ..., value, value ==> ... */ - /* op1 = target JavaVM pc */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ - - if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) { - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP1); - i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4 + 4, REG_ITMP1); - M_BLT(0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); - - disp = 3 + 3 + 6; - CALCOFFSETBYTES(disp, REG_SP, src->prev->regoff * 4); - CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4); - M_BGT(disp); - - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1); - i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4, REG_ITMP1); - M_BBE(0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); - } + s1 = emit_load_s1_high(jd, iptr, REG_ITMP1); + s2 = emit_load_s2_high(jd, iptr, REG_ITMP2); + M_CMP(s2, s1); + M_BLT(0); + codegen_addreference(cd, iptr->dst.block); + s1 = emit_load_s1_low(jd, iptr, REG_ITMP1); + s2 = emit_load_s2_low(jd, iptr, REG_ITMP2); + M_BGT(2 + 6); + M_CMP(s2, s1); + M_BBE(0); + codegen_addreference(cd, iptr->dst.block); break; case ICMD_IF_ICMPGE: /* ..., value, value ==> ... */ - /* op1 = target JavaVM pc */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ - if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) { - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_ITMP1); - i386_alu_reg_membase(cd, ALU_CMP, REG_ITMP1, REG_SP, src->prev->regoff * 4); - - } else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) { - i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4, src->prev->regoff); - - } else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) { - i386_alu_reg_membase(cd, ALU_CMP, src->regoff, REG_SP, src->prev->regoff * 4); - - } else { - i386_alu_reg_reg(cd, ALU_CMP, src->regoff, src->prev->regoff); - } + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + s2 = emit_load_s2(jd, iptr, REG_ITMP2); + M_CMP(s2, s1); M_BGE(0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); + codegen_addreference(cd, iptr->dst.block); break; case ICMD_IF_LCMPGE: /* ..., value, value ==> ... */ - /* op1 = target JavaVM pc */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ - - if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) { - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4 + 4, REG_ITMP1); - i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4 + 4, REG_ITMP1); - M_BGT(0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); - - disp = 3 + 3 + 6; - CALCOFFSETBYTES(disp, REG_SP, src->prev->regoff * 4); - CALCOFFSETBYTES(disp, REG_SP, src->regoff * 4); - - M_BLT(disp); - - i386_mov_membase_reg(cd, REG_SP, src->prev->regoff * 4, REG_ITMP1); - i386_alu_membase_reg(cd, ALU_CMP, REG_SP, src->regoff * 4, REG_ITMP1); - M_BAE(0); - codegen_addreference(cd, (basicblock *) iptr->target, cd->mcodeptr); - } - break; - - /* (value xx 0) ? IFxx_ICONST : ELSE_ICONST */ - - case ICMD_ELSE_ICONST: /* handled by IFxx_ICONST */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ - break; - - case ICMD_IFEQ_ICONST: /* ..., value ==> ..., constant */ - /* val.i = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ - - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - i386_emit_ifcc_iconst(cd, I386_CC_NE, src, iptr); - break; - - case ICMD_IFNE_ICONST: /* ..., value ==> ..., constant */ - /* val.i = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ - - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - i386_emit_ifcc_iconst(cd, I386_CC_E, src, iptr); - break; - - case ICMD_IFLT_ICONST: /* ..., value ==> ..., constant */ - /* val.i = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ - - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - i386_emit_ifcc_iconst(cd, I386_CC_GE, src, iptr); - break; - - case ICMD_IFGE_ICONST: /* ..., value ==> ..., constant */ - /* val.i = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ - - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - i386_emit_ifcc_iconst(cd, I386_CC_L, src, iptr); - break; - - case ICMD_IFGT_ICONST: /* ..., value ==> ..., constant */ - /* val.i = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ - - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - i386_emit_ifcc_iconst(cd, I386_CC_LE, src, iptr); - break; - - case ICMD_IFLE_ICONST: /* ..., value ==> ..., constant */ - /* val.i = constant */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - i386_emit_ifcc_iconst(cd, I386_CC_G, src, iptr); + s1 = emit_load_s1_high(jd, iptr, REG_ITMP1); + s2 = emit_load_s2_high(jd, iptr, REG_ITMP2); + M_CMP(s2, s1); + M_BGT(0); + codegen_addreference(cd, iptr->dst.block); + s1 = emit_load_s1_low(jd, iptr, REG_ITMP1); + s2 = emit_load_s2_low(jd, iptr, REG_ITMP2); + M_BLT(2 + 6); + M_CMP(s2, s1); + M_BAE(0); + codegen_addreference(cd, iptr->dst.block); break; case ICMD_IRETURN: /* ..., retvalue ==> ... */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL */ - var_to_reg_int(s1, src, REG_RESULT); + s1 = emit_load_s1(jd, iptr, REG_RESULT); M_INTMOVE(s1, REG_RESULT); goto nowperformreturn; case ICMD_LRETURN: /* ..., retvalue ==> ... */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ - - if (src->flags & INMEMORY) { - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4, REG_RESULT); - i386_mov_membase_reg(cd, REG_SP, src->regoff * 4 + 4, REG_RESULT2); - } else { - log_text("LRETURN: longs have to be in memory"); - assert(0); - } + s1 = emit_load_s1(jd, iptr, REG_RESULT_PACKED); + M_LNGMOVE(s1, REG_RESULT_PACKED); goto nowperformreturn; case ICMD_ARETURN: /* ..., retvalue ==> ... */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL */ - var_to_reg_int(s1, src, REG_RESULT); + s1 = emit_load_s1(jd, iptr, REG_RESULT); M_INTMOVE(s1, REG_RESULT); #ifdef ENABLE_VERIFIER - if (iptr->val.a) { - codegen_addpatchref(cd, cd->mcodeptr, - PATCHER_athrow_areturn, - (unresolved_class *) iptr->val.a, 0); + if (INSTRUCTION_IS_UNRESOLVED(iptr)) { + codegen_addpatchref(cd, PATCHER_athrow_areturn, + iptr->sx.s23.s2.uc, 0); if (opt_showdisassemble) { M_NOP; M_NOP; M_NOP; M_NOP; M_NOP; @@ -4222,49 +3284,24 @@ bool codegen(jitdata *jd) case ICMD_FRETURN: /* ..., retvalue ==> ... */ case ICMD_DRETURN: - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL */ - var_to_reg_flt(s1, src, REG_FRESULT); - /* this may be an early return -- keep the offset correct for the - remaining code */ - fpu_st_offset--; + s1 = emit_load_s1(jd, iptr, REG_FRESULT); goto nowperformreturn; case ICMD_RETURN: /* ... ==> ... */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ nowperformreturn: { s4 i, p; - p = stackframesize; + p = cd->stackframesize; #if !defined(NDEBUG) - /* call trace function */ - if (opt_verbosecall) { - i386_alu_imm_reg(cd, ALU_SUB, 4 + 8 + 8 + 4, REG_SP); - - i386_mov_imm_membase(cd, (s4) m, REG_SP, 0); - - i386_mov_reg_membase(cd, REG_RESULT, REG_SP, 4); - i386_mov_reg_membase(cd, REG_RESULT2, REG_SP, 4 + 4); - - i386_fstl_membase(cd, REG_SP, 4 + 8); - i386_fsts_membase(cd, REG_SP, 4 + 8 + 8); - - i386_mov_imm_reg(cd, (s4) builtin_displaymethodstop, REG_ITMP1); - i386_call_reg(cd, REG_ITMP1); - - i386_mov_membase_reg(cd, REG_SP, 4, REG_RESULT); - i386_mov_membase_reg(cd, REG_SP, 4 + 4, REG_RESULT2); - - i386_alu_imm_reg(cd, ALU_ADD, 4 + 8 + 8 + 4, REG_SP); - } -#endif /* !defined(NDEBUG) */ + if (JITDATA_HAS_FLAG_VERBOSECALL(jd)) + emit_verbosecall_exit(jd); +#endif -#if defined(USE_THREADS) +#if defined(ENABLE_THREADS) if (checksync && (m->flags & ACC_SYNCHRONIZED)) { M_ALD(REG_ITMP2, REG_SP, rd->memuse * 4); @@ -4276,22 +3313,21 @@ nowperformreturn: break; case ICMD_LRETURN: - M_IST(REG_RESULT, REG_SP, rd->memuse * 4); - M_IST(REG_RESULT2, REG_SP, rd->memuse * 4 + 4); + M_LST(REG_RESULT_PACKED, REG_SP, rd->memuse * 4); break; case ICMD_FRETURN: - i386_fstps_membase(cd, REG_SP, rd->memuse * 4); + emit_fstps_membase(cd, REG_SP, rd->memuse * 4); break; case ICMD_DRETURN: - i386_fstpl_membase(cd, REG_SP, rd->memuse * 4); + emit_fstpl_membase(cd, REG_SP, rd->memuse * 4); break; } M_AST(REG_ITMP2, REG_SP, 0); - M_MOV_IMM(BUILTIN_monitorexit, REG_ITMP1); - M_CALL(REG_ITMP1); + M_MOV_IMM(LOCK_monitor_exit, REG_ITMP3); + M_CALL(REG_ITMP3); /* and now restore the proper return value */ switch (iptr->opc) { @@ -4301,16 +3337,15 @@ nowperformreturn: break; case ICMD_LRETURN: - M_ILD(REG_RESULT, REG_SP, rd->memuse * 4); - M_ILD(REG_RESULT2, REG_SP, rd->memuse * 4 + 4); + M_LLD(REG_RESULT_PACKED, REG_SP, rd->memuse * 4); break; case ICMD_FRETURN: - i386_flds_membase(cd, REG_SP, rd->memuse * 4); + emit_flds_membase(cd, REG_SP, rd->memuse * 4); break; case ICMD_DRETURN: - i386_fldl_membase(cd, REG_SP, rd->memuse * 4); + emit_fldl_membase(cd, REG_SP, rd->memuse * 4); break; } } @@ -4324,129 +3359,115 @@ nowperformreturn: for (i = FLT_SAV_CNT - 1; i >= rd->savfltreguse; i--) { p--; - i386_fldl_membase(cd, REG_SP, p * 4); - fpu_st_offset++; + emit_fldl_membase(cd, REG_SP, p * 4); if (iptr->opc == ICMD_FRETURN || iptr->opc == ICMD_DRETURN) { - i386_fstp_reg(cd, rd->savfltregs[i] + fpu_st_offset + 1); + assert(0); +/* emit_fstp_reg(cd, rd->savfltregs[i] + fpu_st_offset + 1); */ } else { - i386_fstp_reg(cd, rd->savfltregs[i] + fpu_st_offset); + assert(0); +/* emit_fstp_reg(cd, rd->savfltregs[i] + fpu_st_offset); */ } - fpu_st_offset--; } /* deallocate stack */ - if (stackframesize) - M_AADD_IMM(stackframesize * 4, REG_SP); + if (cd->stackframesize) + M_AADD_IMM(cd->stackframesize * 4, REG_SP); - i386_ret(cd); + emit_ret(cd); } break; case ICMD_TABLESWITCH: /* ..., index ==> ... */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ { - s4 i, l, *s4ptr; - void **tptr; + s4 i, l; + branch_target_t *table; - tptr = (void **) iptr->target; + table = iptr->dst.table; - s4ptr = iptr->val.a; - l = s4ptr[1]; /* low */ - i = s4ptr[2]; /* high */ + l = iptr->sx.s23.s2.tablelow; + i = iptr->sx.s23.s3.tablehigh; - var_to_reg_int(s1, src, REG_ITMP1); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); M_INTMOVE(s1, REG_ITMP1); - if (l != 0) { - i386_alu_imm_reg(cd, ALU_SUB, l, REG_ITMP1); - } + + if (l != 0) + M_ISUB_IMM(l, REG_ITMP1); + i = i - l + 1; /* range check */ + M_CMP_IMM(i - 1, REG_ITMP1); + M_BA(0); - i386_alu_imm_reg(cd, ALU_CMP, i - 1, REG_ITMP1); - i386_jcc(cd, I386_CC_A, 0); - - codegen_addreference(cd, (basicblock *) tptr[0], cd->mcodeptr); + codegen_addreference(cd, table[0].block); /* default target */ /* build jump table top down and use address of lowest entry */ - tptr += i; + table += i; while (--i >= 0) { - dseg_addtarget(cd, (basicblock *) tptr[0]); - --tptr; + dseg_addtarget(cd, table->block); + --table; } - /* length of dataseg after last dseg_addtarget is used by load */ + /* length of dataseg after last dseg_addtarget is used + by load */ - i386_mov_imm_reg(cd, 0, REG_ITMP2); - dseg_adddata(cd, cd->mcodeptr); - i386_mov_memindex_reg(cd, -(cd->dseglen), REG_ITMP2, REG_ITMP1, 2, REG_ITMP1); - i386_jmp_reg(cd, REG_ITMP1); + M_MOV_IMM(0, REG_ITMP2); + dseg_adddata(cd); + emit_mov_memindex_reg(cd, -(cd->dseglen), REG_ITMP2, REG_ITMP1, 2, REG_ITMP1); + M_JMP(REG_ITMP1); } break; case ICMD_LOOKUPSWITCH: /* ..., key ==> ... */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: YES EDX: YES OUTPUT: REG_NULL*/ { - s4 i, l, val, *s4ptr; - void **tptr; + s4 i; + lookup_target_t *lookup; - tptr = (void **) iptr->target; + lookup = iptr->dst.lookup; - s4ptr = iptr->val.a; - l = s4ptr[0]; /* default */ - i = s4ptr[1]; /* count */ + i = iptr->sx.s23.s2.lookupcount; MCODECHECK((i<<2)+8); - var_to_reg_int(s1, src, REG_ITMP1); /* reg compare should always be faster */ - while (--i >= 0) { - s4ptr += 2; - ++tptr; + s1 = emit_load_s1(jd, iptr, REG_ITMP1); - val = s4ptr[0]; - i386_alu_imm_reg(cd, ALU_CMP, val, s1); - i386_jcc(cd, I386_CC_E, 0); - codegen_addreference(cd, (basicblock *) tptr[0], cd->mcodeptr); + while (--i >= 0) { + M_CMP_IMM(lookup->value, s1); + M_BEQ(0); + codegen_addreference(cd, lookup->target.block); + lookup++; } - i386_jmp_imm(cd, 0); + M_JMP_IMM(0); - tptr = (void **) iptr->target; - codegen_addreference(cd, (basicblock *) tptr[0], cd->mcodeptr); + codegen_addreference(cd, iptr->sx.s23.s3.lookupdefault.block); } break; case ICMD_BUILTIN: /* ..., [arg1, [arg2 ...]] ==> ... */ - /* op1 = arg count val.a = builtintable entry */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: YES EDX: YES OUTPUT: EAX*/ - bte = iptr->val.a; - md = bte->md; + bte = iptr->sx.s23.s3.bte; + md = bte->md; goto gen_method; case ICMD_INVOKESTATIC: /* ..., [arg1, [arg2 ...]] ==> ... */ - /* op1 = arg count, val.a = method pointer */ case ICMD_INVOKESPECIAL:/* ..., objectref, [arg1, [arg2 ...]] ==> ... */ case ICMD_INVOKEVIRTUAL:/* op1 = arg count, val.a = method pointer */ case ICMD_INVOKEINTERFACE: - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: YES EDX: YES OUTPUT: EAX */ - - lm = iptr->val.a; - - if (lm == NULL) { - unresolved_method *um = iptr->target; + if (INSTRUCTION_IS_UNRESOLVED(iptr)) { + lm = NULL; + um = iptr->sx.s23.s3.um; md = um->methodref->parseddesc.md; - } else { + } + else { + lm = iptr->sx.s23.s3.fmiref->p.method; + um = NULL; md = lm->parseddesc; } @@ -4457,99 +3478,77 @@ gen_method: /* copy arguments to registers or stack location */ - for (s3 = s3 - 1; s3 >= 0; s3--, src = src->prev) { + for (s3 = s3 - 1; s3 >= 0; s3--) { + src = iptr->sx.s23.s2.args[s3]; + if (src->varkind == ARGVAR) continue; + if (IS_INT_LNG_TYPE(src->type)) { if (!md->params[s3].inmemory) { log_text("No integer argument registers available!"); assert(0); - } else { - if (!IS_2_WORD_TYPE(src->type)) { - if (src->flags & INMEMORY) { - i386_mov_membase_reg( - cd, REG_SP, src->regoff * 4, REG_ITMP1); - i386_mov_reg_membase( - cd, REG_ITMP1, REG_SP, - md->params[s3].regoff * 4); - } else { - i386_mov_reg_membase( - cd, src->regoff, REG_SP, - md->params[s3].regoff * 4); - } - - } else { - if (src->flags & INMEMORY) { - M_LNGMEMMOVE( - src->regoff, md->params[s3].regoff); - } else { - log_text("copy arguments: longs have to be in memory"); - assert(0); - } + } + else { + if (IS_2_WORD_TYPE(src->type)) { + d = emit_load(jd, iptr, src, REG_ITMP12_PACKED); + M_LST(d, REG_SP, md->params[s3].regoff * 4); + } + else { + d = emit_load(jd, iptr, src, REG_ITMP1); + M_IST(d, REG_SP, md->params[s3].regoff * 4); } } - } else { + } + else { if (!md->params[s3].inmemory) { - log_text("No float argument registers available!"); - assert(0); - } else { - var_to_reg_flt(d, src, REG_FTMP1); - if (src->type == TYPE_FLT) { - i386_fstps_membase( - cd, REG_SP, md->params[s3].regoff * 4); - - } else { - i386_fstpl_membase( - cd, REG_SP, md->params[s3].regoff * 4); - } + s1 = rd->argfltregs[md->params[s3].regoff]; + d = emit_load(jd, iptr, src, s1); + M_FLTMOVE(d, s1); + } + else { + d = emit_load(jd, iptr, src, REG_FTMP1); + if (IS_2_WORD_TYPE(src->type)) + M_DST(d, REG_SP, md->params[s3].regoff * 4); + else + M_FST(d, REG_SP, md->params[s3].regoff * 4); } } - } /* end of for */ + } switch (iptr->opc) { case ICMD_BUILTIN: - disp = (ptrint) bte->fp; - d = md->returntype.type; - - M_MOV_IMM(disp, REG_ITMP1); + M_MOV_IMM(bte->fp, REG_ITMP1); M_CALL(REG_ITMP1); - /* if op1 == true, we need to check for an exception */ - - if (iptr->op1 == true) { + if (INSTRUCTION_MUST_CHECK(iptr)) { M_TEST(REG_RESULT); M_BEQ(0); - codegen_add_fillinstacktrace_ref(cd, cd->mcodeptr); + codegen_add_fillinstacktrace_ref(cd); } break; case ICMD_INVOKESPECIAL: - i386_mov_membase_reg(cd, REG_SP, 0, REG_ITMP1); - gen_nullptr_check(REG_ITMP1); - - /* access memory for hardware nullptr */ - i386_mov_membase_reg(cd, REG_ITMP1, 0, REG_ITMP1); + M_ALD(REG_ITMP1, REG_SP, 0); + M_TEST(REG_ITMP1); + M_BEQ(0); + codegen_add_nullpointerexception_ref(cd); /* fall through */ case ICMD_INVOKESTATIC: if (lm == NULL) { - unresolved_method *um = iptr->target; - - codegen_addpatchref(cd, cd->mcodeptr, - PATCHER_invokestatic_special, um, 0); + codegen_addpatchref(cd, PATCHER_invokestatic_special, + um, 0); if (opt_showdisassemble) { M_NOP; M_NOP; M_NOP; M_NOP; M_NOP; } disp = 0; - d = md->returntype.type; - - } else { - disp = (ptrint) lm->stubroutine; - d = lm->parseddesc->returntype.type; } + else + disp = (ptrint) lm->stubroutine; M_MOV_IMM(disp, REG_ITMP2); M_CALL(REG_ITMP2); @@ -4560,27 +3559,22 @@ gen_method: gen_nullptr_check(REG_ITMP1); if (lm == NULL) { - unresolved_method *um = iptr->target; - - codegen_addpatchref(cd, cd->mcodeptr, - PATCHER_invokevirtual, um, 0); + codegen_addpatchref(cd, PATCHER_invokevirtual, um, 0); if (opt_showdisassemble) { M_NOP; M_NOP; M_NOP; M_NOP; M_NOP; } s1 = 0; - d = md->returntype.type; - - } else { + } + else s1 = OFFSET(vftbl_t, table[0]) + sizeof(methodptr) * lm->vftblindex; - d = md->returntype.type; - } - M_ALD(REG_ITMP2, REG_ITMP1, OFFSET(java_objectheader, vftbl)); - i386_mov_membase32_reg(cd, REG_ITMP2, s1, REG_ITMP1); - M_CALL(REG_ITMP1); + M_ALD(REG_METHODPTR, REG_ITMP1, + OFFSET(java_objectheader, vftbl)); + M_ALD32(REG_ITMP3, REG_METHODPTR, s1); + M_CALL(REG_ITMP3); break; case ICMD_INVOKEINTERFACE: @@ -4588,10 +3582,7 @@ gen_method: gen_nullptr_check(REG_ITMP1); if (lm == NULL) { - unresolved_method *um = iptr->target; - - codegen_addpatchref(cd, cd->mcodeptr, - PATCHER_invokeinterface, um, 0); + codegen_addpatchref(cd, PATCHER_invokeinterface, um, 0); if (opt_showdisassemble) { M_NOP; M_NOP; M_NOP; M_NOP; M_NOP; @@ -4599,67 +3590,55 @@ gen_method: s1 = 0; s2 = 0; - d = md->returntype.type; - - } else { + } + else { s1 = OFFSET(vftbl_t, interfacetable[0]) - sizeof(methodptr) * lm->class->index; s2 = sizeof(methodptr) * (lm - lm->class->methods); - - d = md->returntype.type; } - M_ALD(REG_ITMP1, REG_ITMP1, OFFSET(java_objectheader, vftbl)); - i386_mov_membase32_reg(cd, REG_ITMP1, s1, REG_ITMP2); - i386_mov_membase32_reg(cd, REG_ITMP2, s2, REG_ITMP1); - M_CALL(REG_ITMP1); + M_ALD(REG_METHODPTR, REG_ITMP1, + OFFSET(java_objectheader, vftbl)); + M_ALD32(REG_METHODPTR, REG_METHODPTR, s1); + M_ALD32(REG_ITMP3, REG_METHODPTR, s2); + M_CALL(REG_ITMP3); break; } - /* d contains return type */ + /* store return value */ + + d = md->returntype.type; if (d != TYPE_VOID) { - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL); - - if (IS_INT_LNG_TYPE(iptr->dst->type)) { - if (IS_2_WORD_TYPE(iptr->dst->type)) { - if (iptr->dst->flags & INMEMORY) { - i386_mov_reg_membase( - cd, REG_RESULT, REG_SP, iptr->dst->regoff * 4); - i386_mov_reg_membase( - cd, REG_RESULT2, REG_SP, - iptr->dst->regoff * 4 + 4); - } else { - log_text("RETURN: longs have to be in memory"); - assert(0); +#if defined(ENABLE_SSA) + if ((ls == NULL) || (iptr->dst->varkind != TEMPVAR) || + (ls->lifetime[-iptr->dst->varnum-1].type != -1)) + /* a "living" stackslot */ +#endif + { + if (IS_INT_LNG_TYPE(d)) { + if (IS_2_WORD_TYPE(d)) { + s1 = codegen_reg_of_dst(jd, iptr, REG_RESULT_PACKED); + M_LNGMOVE(REG_RESULT_PACKED, s1); } - - } else { - if (iptr->dst->flags & INMEMORY) { - i386_mov_reg_membase(cd, REG_RESULT, REG_SP, iptr->dst->regoff * 4); - - } else { - M_INTMOVE(REG_RESULT, iptr->dst->regoff); + else { + s1 = codegen_reg_of_dst(jd, iptr, REG_RESULT); + M_INTMOVE(REG_RESULT, s1); } } - - } else { - /* fld from called function -- has other fpu_st_offset counter */ - fpu_st_offset++; - store_reg_to_var_flt(iptr->dst, d); + else { + s1 = codegen_reg_of_dst(jd, iptr, REG_NULL); + } + emit_store_dst(jd, iptr, s1); } } break; case ICMD_CHECKCAST: /* ..., objectref ==> ..., objectref */ - /* op1: 0 == array, 1 == class */ /* val.a: (classinfo*) superclass */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: YES ECX: I|YES EDX: I|YES OUTPUT: REG_NULL */ - /* superclass is an interface: * * OK if ((sub == NULL) || @@ -4673,28 +3652,28 @@ gen_method: * super->vftbl->diffval)); */ - if (iptr->op1 == 1) { + if (!(iptr->flags.bits & INS_FLAG_ARRAY)) { /* object type cast-check */ classinfo *super; vftbl_t *supervftbl; s4 superindex; - super = (classinfo *) iptr->val.a; - - if (!super) { + if (INSTRUCTION_IS_UNRESOLVED(iptr)) { + super = NULL; superindex = 0; supervftbl = NULL; - - } else { + } + else { + super = iptr->sx.s23.s3.c.cls; superindex = super->index; supervftbl = super->vftbl; } -#if defined(USE_THREADS) && defined(NATIVE_THREADS) +#if defined(ENABLE_THREADS) codegen_threadcritrestart(cd, cd->mcodeptr - cd->mcodebase); #endif - var_to_reg_int(s1, src, REG_ITMP1); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); /* calculate interface checkcast code size */ @@ -4735,164 +3714,149 @@ gen_method: s3 += 2 /* cmp */ + 6 /* jcc */; - if (!super) + if (super == NULL) s3 += (opt_showdisassemble ? 5 : 0); /* if class is not resolved, check which code to call */ - if (!super) { - i386_test_reg_reg(cd, s1, s1); - i386_jcc(cd, I386_CC_Z, 5 + (opt_showdisassemble ? 5 : 0) + 6 + 6 + s2 + 5 + s3); + if (super == NULL) { + M_TEST(s1); + M_BEQ(5 + (opt_showdisassemble ? 5 : 0) + 6 + 6 + s2 + 5 + s3); - codegen_addpatchref(cd, cd->mcodeptr, - PATCHER_checkcast_instanceof_flags, - (constant_classref *) iptr->target, 0); + codegen_addpatchref(cd, PATCHER_checkcast_instanceof_flags, + iptr->sx.s23.s3.c.ref, 0); if (opt_showdisassemble) { M_NOP; M_NOP; M_NOP; M_NOP; M_NOP; } - i386_mov_imm_reg(cd, 0, REG_ITMP2); /* super->flags */ - i386_alu_imm_reg(cd, ALU_AND, ACC_INTERFACE, REG_ITMP2); - i386_jcc(cd, I386_CC_Z, s2 + 5); + M_MOV_IMM(0, REG_ITMP2); /* super->flags */ + M_AND_IMM32(ACC_INTERFACE, REG_ITMP2); + M_BEQ(s2 + 5); } /* interface checkcast code */ - if (!super || (super->flags & ACC_INTERFACE)) { - if (super) { - i386_test_reg_reg(cd, s1, s1); - i386_jcc(cd, I386_CC_Z, s2); + if ((super == NULL) || (super->flags & ACC_INTERFACE)) { + if (super != NULL) { + M_TEST(s1); + M_BEQ(s2); } - i386_mov_membase_reg(cd, s1, - OFFSET(java_objectheader, vftbl), - REG_ITMP2); + M_ALD(REG_ITMP2, s1, OFFSET(java_objectheader, vftbl)); - if (!super) { - codegen_addpatchref(cd, cd->mcodeptr, + if (super == NULL) { + codegen_addpatchref(cd, PATCHER_checkcast_instanceof_interface, - (constant_classref *) iptr->target, 0); + iptr->sx.s23.s3.c.ref, + 0); if (opt_showdisassemble) { M_NOP; M_NOP; M_NOP; M_NOP; M_NOP; } } - i386_mov_membase32_reg(cd, REG_ITMP2, - OFFSET(vftbl_t, interfacetablelength), - REG_ITMP3); - i386_alu_imm32_reg(cd, ALU_SUB, superindex, REG_ITMP3); - i386_test_reg_reg(cd, REG_ITMP3, REG_ITMP3); - i386_jcc(cd, I386_CC_LE, 0); - codegen_add_classcastexception_ref(cd, cd->mcodeptr); - i386_mov_membase32_reg(cd, REG_ITMP2, - OFFSET(vftbl_t, interfacetable[0]) - - superindex * sizeof(methodptr*), - REG_ITMP3); - i386_test_reg_reg(cd, REG_ITMP3, REG_ITMP3); - i386_jcc(cd, I386_CC_E, 0); - codegen_add_classcastexception_ref(cd, cd->mcodeptr); - - if (!super) - i386_jmp_imm(cd, s3); + M_ILD32(REG_ITMP3, + REG_ITMP2, OFFSET(vftbl_t, interfacetablelength)); + M_ISUB_IMM32(superindex, REG_ITMP3); + M_TEST(REG_ITMP3); + M_BLE(0); + codegen_add_classcastexception_ref(cd, s1); + M_ALD32(REG_ITMP3, REG_ITMP2, + OFFSET(vftbl_t, interfacetable[0]) - + superindex * sizeof(methodptr*)); + M_TEST(REG_ITMP3); + M_BEQ(0); + codegen_add_classcastexception_ref(cd, s1); + + if (super == NULL) + M_JMP_IMM(s3); } /* class checkcast code */ - if (!super || !(super->flags & ACC_INTERFACE)) { - if (super) { - i386_test_reg_reg(cd, s1, s1); - i386_jcc(cd, I386_CC_Z, s3); + if ((super == NULL) || !(super->flags & ACC_INTERFACE)) { + if (super != NULL) { + M_TEST(s1); + M_BEQ(s3); } - i386_mov_membase_reg(cd, s1, - OFFSET(java_objectheader, vftbl), - REG_ITMP2); + M_ALD(REG_ITMP2, s1, OFFSET(java_objectheader, vftbl)); - if (!super) { - codegen_addpatchref(cd, cd->mcodeptr, - PATCHER_checkcast_class, - (constant_classref *) iptr->target, 0); + if (super == NULL) { + codegen_addpatchref(cd, PATCHER_checkcast_class, + iptr->sx.s23.s3.c.ref, + 0); if (opt_showdisassemble) { M_NOP; M_NOP; M_NOP; M_NOP; M_NOP; } } - i386_mov_imm_reg(cd, (ptrint) supervftbl, REG_ITMP3); -#if defined(USE_THREADS) && defined(NATIVE_THREADS) + M_MOV_IMM(supervftbl, REG_ITMP3); +#if defined(ENABLE_THREADS) codegen_threadcritstart(cd, cd->mcodeptr - cd->mcodebase); #endif - i386_mov_membase32_reg(cd, REG_ITMP2, - OFFSET(vftbl_t, baseval), - REG_ITMP2); + M_ILD32(REG_ITMP2, REG_ITMP2, OFFSET(vftbl_t, baseval)); /* if (s1 != REG_ITMP1) { */ - /* i386_mov_membase_reg(cd, REG_ITMP3, OFFSET(vftbl_t, baseval), REG_ITMP1); */ - /* i386_mov_membase_reg(cd, REG_ITMP3, OFFSET(vftbl_t, diffval), REG_ITMP3); */ - /* #if defined(USE_THREADS) && defined(NATIVE_THREADS) */ + /* emit_mov_membase_reg(cd, REG_ITMP3, OFFSET(vftbl_t, baseval), REG_ITMP1); */ + /* emit_mov_membase_reg(cd, REG_ITMP3, OFFSET(vftbl_t, diffval), REG_ITMP3); */ + /* #if defined(ENABLE_THREADS) */ /* codegen_threadcritstop(cd, cd->mcodeptr - cd->mcodebase); */ /* #endif */ - /* i386_alu_reg_reg(cd, ALU_SUB, REG_ITMP1, REG_ITMP2); */ + /* emit_alu_reg_reg(cd, ALU_SUB, REG_ITMP1, REG_ITMP2); */ /* } else { */ - i386_mov_membase32_reg(cd, REG_ITMP3, - OFFSET(vftbl_t, baseval), - REG_ITMP3); - i386_alu_reg_reg(cd, ALU_SUB, REG_ITMP3, REG_ITMP2); - i386_mov_imm_reg(cd, (ptrint) supervftbl, REG_ITMP3); - i386_mov_membase_reg(cd, REG_ITMP3, - OFFSET(vftbl_t, diffval), - REG_ITMP3); -#if defined(USE_THREADS) && defined(NATIVE_THREADS) + M_ILD32(REG_ITMP3, REG_ITMP3, OFFSET(vftbl_t, baseval)); + M_ISUB(REG_ITMP3, REG_ITMP2); + M_MOV_IMM(supervftbl, REG_ITMP3); + M_ILD(REG_ITMP3, REG_ITMP3, OFFSET(vftbl_t, diffval)); +#if defined(ENABLE_THREADS) codegen_threadcritstop(cd, cd->mcodeptr - cd->mcodebase); #endif /* } */ - i386_alu_reg_reg(cd, ALU_CMP, REG_ITMP3, REG_ITMP2); - i386_jcc(cd, I386_CC_A, 0); /* (u) REG_ITMP2 > (u) REG_ITMP3 -> jump */ - codegen_add_classcastexception_ref(cd, cd->mcodeptr); + M_CMP(REG_ITMP3, REG_ITMP2); + M_BA(0); /* (u) REG_ITMP2 > (u) REG_ITMP3 -> jump */ + codegen_add_classcastexception_ref(cd, s1); } - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP3); - } else { + d = codegen_reg_of_dst(jd, iptr, REG_ITMP3); + } + else { /* array type cast-check */ - var_to_reg_int(s1, src, REG_ITMP1); + s1 = emit_load_s1(jd, iptr, REG_ITMP2); M_AST(s1, REG_SP, 0 * 4); - if (iptr->val.a == NULL) { - codegen_addpatchref(cd, cd->mcodeptr, - PATCHER_builtin_arraycheckcast, - iptr->target, 0); + if (INSTRUCTION_IS_UNRESOLVED(iptr)) { + codegen_addpatchref(cd, PATCHER_builtin_arraycheckcast, + iptr->sx.s23.s3.c.ref, 0); if (opt_showdisassemble) { M_NOP; M_NOP; M_NOP; M_NOP; M_NOP; } } - M_AST_IMM(iptr->val.a, REG_SP, 1 * 4); + M_AST_IMM(iptr->sx.s23.s3.c.cls, REG_SP, 1 * 4); M_MOV_IMM(BUILTIN_arraycheckcast, REG_ITMP3); M_CALL(REG_ITMP3); + + s1 = emit_load_s1(jd, iptr, REG_ITMP2); M_TEST(REG_RESULT); M_BEQ(0); - codegen_add_classcastexception_ref(cd, cd->mcodeptr); + codegen_add_classcastexception_ref(cd, s1); - var_to_reg_int(s1, src, REG_ITMP1); - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, s1); + d = codegen_reg_of_dst(jd, iptr, s1); } + M_INTMOVE(s1, d); - store_reg_to_var_int(iptr->dst, d); + emit_store_dst(jd, iptr, d); break; case ICMD_INSTANCEOF: /* ..., objectref ==> ..., intresult */ - - /* op1: 0 == array, 1 == class */ /* val.a: (classinfo*) superclass */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|D|YES ECX: YES S|D|EDX: S|D|YES OUTPUT: REG_NULL*/ - /* ????? Really necessary to block all ????? */ /* superclass is an interface: * @@ -4912,23 +3876,23 @@ gen_method: vftbl_t *supervftbl; s4 superindex; - super = (classinfo *) iptr->val.a; - - if (!super) { + if (INSTRUCTION_IS_UNRESOLVED(iptr)) { + super = NULL; superindex = 0; supervftbl = NULL; } else { + super = iptr->sx.s23.s3.c.cls; superindex = super->index; supervftbl = super->vftbl; } -#if defined(USE_THREADS) && defined(NATIVE_THREADS) +#if defined(ENABLE_THREADS) codegen_threadcritrestart(cd, cd->mcodeptr - cd->mcodebase); #endif - var_to_reg_int(s1, src, REG_ITMP1); - d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP2); + s1 = emit_load_s1(jd, iptr, REG_ITMP1); + d = codegen_reg_of_dst(jd, iptr, REG_ITMP2); if (s1 == d) { M_INTMOVE(s1, REG_ITMP1); s1 = REG_ITMP1; @@ -4964,25 +3928,24 @@ gen_method: if (!super) s3 += (opt_showdisassemble ? 5 : 0); - i386_alu_reg_reg(cd, ALU_XOR, d, d); + M_CLR(d); /* if class is not resolved, check which code to call */ if (!super) { - i386_test_reg_reg(cd, s1, s1); - i386_jcc(cd, I386_CC_Z, 5 + (opt_showdisassemble ? 5 : 0) + 6 + 6 + s2 + 5 + s3); + M_TEST(s1); + M_BEQ(5 + (opt_showdisassemble ? 5 : 0) + 6 + 6 + s2 + 5 + s3); - codegen_addpatchref(cd, cd->mcodeptr, - PATCHER_checkcast_instanceof_flags, - (constant_classref *) iptr->target, 0); + codegen_addpatchref(cd, PATCHER_checkcast_instanceof_flags, + iptr->sx.s23.s3.c.ref, 0); if (opt_showdisassemble) { M_NOP; M_NOP; M_NOP; M_NOP; M_NOP; } - i386_mov_imm_reg(cd, 0, REG_ITMP3); /* super->flags */ - i386_alu_imm32_reg(cd, ALU_AND, ACC_INTERFACE, REG_ITMP3); - i386_jcc(cd, I386_CC_Z, s2 + 5); + M_MOV_IMM(0, REG_ITMP3); /* super->flags */ + M_AND_IMM32(ACC_INTERFACE, REG_ITMP3); + M_BEQ(s2 + 5); } /* interface instanceof code */ @@ -4993,37 +3956,33 @@ gen_method: M_BEQ(s2); } - i386_mov_membase_reg(cd, s1, - OFFSET(java_objectheader, vftbl), - REG_ITMP1); + M_ALD(REG_ITMP1, s1, OFFSET(java_objectheader, vftbl)); if (!super) { - codegen_addpatchref(cd, cd->mcodeptr, + codegen_addpatchref(cd, PATCHER_checkcast_instanceof_interface, - (constant_classref *) iptr->target, 0); + iptr->sx.s23.s3.c.ref, 0); if (opt_showdisassemble) { M_NOP; M_NOP; M_NOP; M_NOP; M_NOP; } } - i386_mov_membase32_reg(cd, REG_ITMP1, - OFFSET(vftbl_t, interfacetablelength), - REG_ITMP3); - i386_alu_imm32_reg(cd, ALU_SUB, superindex, REG_ITMP3); - i386_test_reg_reg(cd, REG_ITMP3, REG_ITMP3); + M_ILD32(REG_ITMP3, + REG_ITMP1, OFFSET(vftbl_t, interfacetablelength)); + M_ISUB_IMM32(superindex, REG_ITMP3); + M_TEST(REG_ITMP3); disp = (2 + 4 /* mov_membase32_reg */ + 2 /* test */ + 6 /* jcc */ + 5 /* mov_imm_reg */); M_BLE(disp); - i386_mov_membase32_reg(cd, REG_ITMP1, - OFFSET(vftbl_t, interfacetable[0]) - - superindex * sizeof(methodptr*), - REG_ITMP1); + M_ALD32(REG_ITMP1, REG_ITMP1, + OFFSET(vftbl_t, interfacetable[0]) - + superindex * sizeof(methodptr*)); M_TEST(REG_ITMP1); -/* i386_setcc_reg(cd, I386_CC_A, d); */ -/* i386_jcc(cd, I386_CC_BE, 5); */ +/* emit_setcc_reg(cd, CC_A, d); */ +/* emit_jcc(cd, CC_BE, 5); */ M_BEQ(5); M_MOV_IMM(1, d); @@ -5039,77 +3998,64 @@ gen_method: M_BEQ(s3); } - i386_mov_membase_reg(cd, s1, - OFFSET(java_objectheader, vftbl), - REG_ITMP1); + M_ALD(REG_ITMP1, s1, OFFSET(java_objectheader, vftbl)); if (!super) { - codegen_addpatchref(cd, cd->mcodeptr, - PATCHER_instanceof_class, - (constant_classref *) iptr->target, 0); + codegen_addpatchref(cd, PATCHER_instanceof_class, + iptr->sx.s23.s3.c.ref, 0); if (opt_showdisassemble) { M_NOP; M_NOP; M_NOP; M_NOP; M_NOP; } } - i386_mov_imm_reg(cd, (ptrint) supervftbl, REG_ITMP2); -#if defined(USE_THREADS) && defined(NATIVE_THREADS) + M_MOV_IMM(supervftbl, REG_ITMP2); +#if defined(ENABLE_THREADS) codegen_threadcritstart(cd, cd->mcodeptr - cd->mcodebase); #endif - i386_mov_membase_reg(cd, REG_ITMP1, - OFFSET(vftbl_t, baseval), - REG_ITMP1); - i386_mov_membase_reg(cd, REG_ITMP2, - OFFSET(vftbl_t, diffval), - REG_ITMP3); - i386_mov_membase_reg(cd, REG_ITMP2, - OFFSET(vftbl_t, baseval), - REG_ITMP2); -#if defined(USE_THREADS) && defined(NATIVE_THREADS) + M_ILD(REG_ITMP1, REG_ITMP1, OFFSET(vftbl_t, baseval)); + M_ILD(REG_ITMP3, REG_ITMP2, OFFSET(vftbl_t, diffval)); + M_ILD(REG_ITMP2, REG_ITMP2, OFFSET(vftbl_t, baseval)); +#if defined(ENABLE_THREADS) codegen_threadcritstop(cd, cd->mcodeptr - cd->mcodebase); #endif - i386_alu_reg_reg(cd, ALU_SUB, REG_ITMP2, REG_ITMP1); - i386_alu_reg_reg(cd, ALU_XOR, d, d); /* may be REG_ITMP2 */ - i386_alu_reg_reg(cd, ALU_CMP, REG_ITMP3, REG_ITMP1); - i386_jcc(cd, I386_CC_A, 5); - i386_mov_imm_reg(cd, 1, d); + M_ISUB(REG_ITMP2, REG_ITMP1); + M_CLR(d); /* may be REG_ITMP2 */ + M_CMP(REG_ITMP3, REG_ITMP1); + M_BA(5); + M_MOV_IMM(1, d); } - store_reg_to_var_int(iptr->dst, d); + emit_store_dst(jd, iptr, d); } break; break; case ICMD_MULTIANEWARRAY:/* ..., cnt1, [cnt2, ...] ==> ..., arrayref */ - /* op1 = dimension, val.a = class */ - /* REG_RES Register usage: see icmd_uses_reg_res.inc */ - /* EAX: S|YES ECX: YES EDX: YES OUTPUT: EAX */ /* check for negative sizes and copy sizes to stack if necessary */ - MCODECHECK((iptr->op1 << 1) + 64); + MCODECHECK((iptr->s1.argcount << 1) + 64); - for (s1 = iptr->op1; --s1 >= 0; src = src->prev) { + for (s1 = iptr->s1.argcount; --s1 >= 0; ) { /* copy SAVEDVAR sizes to stack */ + src = iptr->sx.s23.s2.args[s1]; if (src->varkind != ARGVAR) { - if (src->flags & INMEMORY) { + if (IS_INMEMORY(src->flags)) { M_ILD(REG_ITMP1, REG_SP, src->regoff * 4); M_IST(REG_ITMP1, REG_SP, (s1 + 3) * 4); - - } else { - M_IST(src->regoff, REG_SP, (s1 + 3) * 4); } + else + M_IST(src->regoff, REG_SP, (s1 + 3) * 4); } } /* is a patcher function set? */ - if (iptr->val.a == NULL) { - codegen_addpatchref(cd, cd->mcodeptr, - PATCHER_builtin_multianewarray, - (constant_classref *) iptr->target, 0); + if (INSTRUCTION_IS_UNRESOLVED(iptr)) { + codegen_addpatchref(cd, PATCHER_builtin_multianewarray, + iptr->sx.s23.s3.c.ref, 0); if (opt_showdisassemble) { M_NOP; M_NOP; M_NOP; M_NOP; M_NOP; @@ -5117,13 +4063,13 @@ gen_method: disp = 0; - } else { - disp = (ptrint) iptr->val.a; } + else + disp = (ptrint) iptr->sx.s23.s3.c.cls; /* a0 = dimension count */ - M_IST_IMM(iptr->op1, REG_SP, 0 * 4); + M_IST_IMM(iptr->s1.argcount, REG_SP, 0 * 4); /* a1 = arraydescriptor */ @@ -5142,11 +4088,11 @@ gen_method: M_TEST(REG_RESULT); M_BEQ(0); - codegen_add_fillinstacktrace_ref(cd, cd->mcodeptr); + codegen_add_fillinstacktrace_ref(cd); - s1 = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_RESULT); + s1 = codegen_reg_of_dst(jd, iptr, REG_RESULT); M_INTMOVE(REG_RESULT, s1); - store_reg_to_var_int(iptr->dst, s1); + emit_store_dst(jd, iptr, s1); break; default: @@ -5159,50 +4105,60 @@ gen_method: /* copy values to interface registers */ - src = bptr->outstack; len = bptr->outdepth; MCODECHECK(64+len); -#if defined(ENABLE_LSRA) +#if defined(ENABLE_LSRA) && !defined(ENABLE_SSA) if (!opt_lsra) #endif - while (src) { +#if defined(ENABLE_SSA) + if ( ls != NULL ) { + /* by edge splitting, in Blocks with phi moves there can only */ + /* be a goto as last command, no other Jump/Branch Command */ + if (!last_cmd_was_goto) + codegen_insert_phi_moves(cd, rd, ls, bptr); + } + #if !defined(NEW_VAR) + else + #endif +#endif +#if !defined(NEW_VAR) + while (len) { len--; + src = bptr->outvars[len]; if ((src->varkind != STACKVAR)) { s2 = src->type; if (IS_FLT_DBL_TYPE(s2)) { - var_to_reg_flt(s1, src, REG_FTMP1); - if (!(rd->interfaces[len][s2].flags & INMEMORY)) { + s1 = emit_load(jd, iptr, src, REG_FTMP1); + if (!IS_INMEMORY(rd->interfaces[len][s2].flags)) M_FLTMOVE(s1, rd->interfaces[len][s2].regoff); - - } else { - log_text("double store"); - assert(0); -/* M_DST(s1, REG_SP, 4 * interfaces[len][s2].regoff); */ - } - + else + M_DST(s1, REG_SP, rd->interfaces[len][s2].regoff * 4); + } else { - var_to_reg_int(s1, src, REG_ITMP1); - if (!IS_2_WORD_TYPE(rd->interfaces[len][s2].type)) { - if (!(rd->interfaces[len][s2].flags & INMEMORY)) { + if (IS_2_WORD_TYPE(s2)) + assert(0); +/* s1 = emit_load(jd, iptr, src, + PACK_REGS(REG_ITMP1, REG_ITMP2)); */ + else + s1 = emit_load(jd, iptr, src, REG_ITMP1); + + if (!IS_INMEMORY(rd->interfaces[len][s2].flags)) { + if (IS_2_WORD_TYPE(s2)) + M_LNGMOVE(s1, rd->interfaces[len][s2].regoff); + else M_INTMOVE(s1, rd->interfaces[len][s2].regoff); - - } else { - i386_mov_reg_membase(cd, s1, REG_SP, rd->interfaces[len][s2].regoff * 4); - } - + } else { - if (rd->interfaces[len][s2].flags & INMEMORY) { - M_LNGMEMMOVE(s1, rd->interfaces[len][s2].regoff); - - } else { - log_text("copy interface registers: longs have to be in memory (end)"); - assert(0); - } + if (IS_2_WORD_TYPE(s2)) + M_LST(s1, REG_SP, rd->interfaces[len][s2].regoff * 4); + else + M_IST(s1, REG_SP, rd->interfaces[len][s2].regoff * 4); } } } src = src->prev; } +#endif /* At the end of a basic block we may have to append some nops, because the patcher stub calling code might be longer than the @@ -5223,164 +4179,177 @@ gen_method: /* generate exception and patcher stubs */ - { - exceptionref *eref; - patchref *pref; - u8 mcode; - u1 *savedmcodeptr; - u1 *tmpmcodeptr; - - savedmcodeptr = NULL; - - /* generate exception stubs */ - - for (eref = cd->exceptionrefs; eref != NULL; eref = eref->next) { - gen_resolvebranch(cd->mcodebase + eref->branchpos, - eref->branchpos, - cd->mcodeptr - cd->mcodebase); - - MCODECHECK(512); - - /* Check if the exception is an - ArrayIndexOutOfBoundsException. If so, move index register - into REG_ITMP1. */ - - if (eref->reg != -1) - M_INTMOVE(eref->reg, REG_ITMP1); - - /* calcuate exception address */ - - M_MOV_IMM(0, REG_ITMP2_XPC); - dseg_adddata(cd, cd->mcodeptr); - M_AADD_IMM32(eref->branchpos - 6, REG_ITMP2_XPC); - - /* move function to call into REG_ITMP3 */ - - M_MOV_IMM(eref->function, REG_ITMP3); - - if (savedmcodeptr != NULL) { - M_JMP_IMM((savedmcodeptr - cd->mcodeptr) - 5); - - } else { - savedmcodeptr = cd->mcodeptr; - - M_ASUB_IMM(5 * 4, REG_SP); - - /* first save REG_ITMP1 so we can use it */ - - M_AST(REG_ITMP1, REG_SP, 4 * 4); /* for AIOOBE */ + emit_exception_stubs(jd); + emit_patcher_stubs(jd); +#if 0 + emit_replacement_stubs(jd); +#endif - M_AST_IMM(0, REG_SP, 0 * 4); - dseg_adddata(cd, cd->mcodeptr); - M_MOV(REG_SP, REG_ITMP1); - M_AADD_IMM(5 * 4, REG_ITMP1); - M_AST(REG_ITMP1, REG_SP, 1 * 4); - M_ALD(REG_ITMP1, REG_SP, (5 + stackframesize) * 4); - M_AST(REG_ITMP1, REG_SP, 2 * 4); - M_AST(REG_ITMP2_XPC, REG_SP, 3 * 4); + codegen_finish(jd); - M_CALL(REG_ITMP3); + /* everything's ok */ - M_ALD(REG_ITMP2_XPC, REG_SP, 3 * 4); - M_AADD_IMM(5 * 4, REG_SP); + return true; +} - M_MOV_IMM(asm_handle_exception, REG_ITMP3); - M_JMP(REG_ITMP3); - } +#if defined(ENABLE_SSA) +void codegen_insert_phi_moves(codegendata *cd, registerdata *rd, lsradata *ls, basicblock *bptr) { + /* look for phi moves */ + int t_a,s_a,i, type; + int t_lt, s_lt; /* lifetime indices of phi_moves */ + bool t_inmemory, s_inmemory; + s4 t_regoff, s_regoff, s_flags, t_flags; + MCODECHECK(512); + + /* Moves from phi functions with highest indices have to be */ + /* inserted first, since this is the order as is used for */ + /* conflict resolution */ + for(i = ls->num_phi_moves[bptr->nr] - 1; i >= 0 ; i--) { + t_a = ls->phi_moves[bptr->nr][i][0]; + s_a = ls->phi_moves[bptr->nr][i][1]; +#if defined(SSA_DEBUG_VERBOSE) + if (compileverbose) + printf("BB %3i Move %3i <- %3i ",bptr->nr,t_a,s_a); +#endif + if (t_a >= 0) { + /* local var lifetimes */ + t_lt = ls->maxlifetimes + t_a; + type = ls->lifetime[t_lt].type; + } else { + t_lt = -t_a-1; + type = ls->lifetime[t_lt].local_ss->s->type; + /* stackslot lifetime */ } - - - /* generate code patching stub call code */ - - for (pref = cd->patchrefs; pref != NULL; pref = pref->next) { - /* check code segment size */ - - MCODECHECK(512); - - /* Get machine code which is patched back in later. A - `call rel32' is 5 bytes long. */ - - savedmcodeptr = cd->mcodebase + pref->branchpos; - mcode = *((u8 *) savedmcodeptr); - - /* patch in `call rel32' to call the following code */ - - tmpmcodeptr = cd->mcodeptr; /* save current mcodeptr */ - cd->mcodeptr = savedmcodeptr; /* set mcodeptr to patch position */ - - M_CALL_IMM(tmpmcodeptr - (savedmcodeptr + PATCHER_CALL_SIZE)); - - cd->mcodeptr = tmpmcodeptr; /* restore the current mcodeptr */ - - /* save REG_ITMP3 */ - - M_PUSH(REG_ITMP3); - - /* move pointer to java_objectheader onto stack */ - -#if defined(USE_THREADS) && defined(NATIVE_THREADS) - (void) dseg_addaddress(cd, get_dummyLR()); /* monitorPtr */ - off = dseg_addaddress(cd, NULL); /* vftbl */ - - M_MOV_IMM(0, REG_ITMP3); - dseg_adddata(cd, cd->mcodeptr); - M_AADD_IMM(off, REG_ITMP3); - M_PUSH(REG_ITMP3); -#else - M_PUSH_IMM(0); + if (type == -1) { +#if defined(SSA_DEBUG_VERBOSE) + if (compileverbose) + printf("...returning - phi lifetimes where joined\n"); #endif - - /* move machine code bytes and classinfo pointer into registers */ - - M_PUSH_IMM(mcode >> 32); - M_PUSH_IMM(mcode); - M_PUSH_IMM(pref->ref); - M_PUSH_IMM(pref->patcher); - - M_MOV_IMM(asm_wrapper_patcher, REG_ITMP3); - M_JMP(REG_ITMP3); + return; } - } - - /* generate replacement-out stubs */ - - { - int i; - - replacementpoint = jd->code->rplpoints; - - for (i = 0; i < jd->code->rplpointcount; ++i, ++replacementpoint) { - /* check code segment size */ - - MCODECHECK(512); - - /* note start of stub code */ - - replacementpoint->outcode = (u1*) (ptrint)(cd->mcodeptr - cd->mcodebase); - - /* make machine code for patching */ - - disp = (ptrint)(replacementpoint->outcode - replacementpoint->pc) - 5; - replacementpoint->mcode = 0xe9 | ((u8)disp << 8); + if (s_a >= 0) { + /* local var lifetimes */ + s_lt = ls->maxlifetimes + s_a; + type = ls->lifetime[s_lt].type; + } else { + s_lt = -s_a-1; + type = ls->lifetime[s_lt].type; + /* stackslot lifetime */ + } + if (type == -1) { +#if defined(SSA_DEBUG_VERBOSE) + if (compileverbose) + printf("...returning - phi lifetimes where joined\n"); +#endif + return; + } + if (t_a >= 0) { - /* push address of `rplpoint` struct */ + t_inmemory = rd->locals[t_a][type].flags & INMEMORY; + t_flags = rd->locals[t_a][type].flags; + t_regoff = rd->locals[t_a][type].regoff; - M_PUSH_IMM(replacementpoint); + } else { + t_inmemory = ls->lifetime[t_lt].local_ss->s->flags & INMEMORY; + t_flags = ls->lifetime[t_lt].local_ss->s->flags; + t_regoff = ls->lifetime[t_lt].local_ss->s->regoff; + } - /* jump to replacement function */ + if (s_a >= 0) { + /* local var move */ + + s_inmemory = rd->locals[s_a][type].flags & INMEMORY; + s_flags = rd->locals[s_a][type].flags; + s_regoff = rd->locals[s_a][type].regoff; + } else { + /* stackslot lifetime */ + s_inmemory = ls->lifetime[s_lt].local_ss->s->flags & INMEMORY; + s_flags = ls->lifetime[s_lt].local_ss->s->flags; + s_regoff = ls->lifetime[s_lt].local_ss->s->regoff; + } + if (type == -1) { +#if defined(SSA_DEBUG_VERBOSE) + if (compileverbose) + printf("...returning - phi lifetimes where joined\n"); +#endif + return; + } - M_PUSH_IMM(asm_replacement_out); - M_RET; + cg_move(cd, type, s_regoff, s_flags, t_regoff, t_flags); + +#if defined(SSA_DEBUG_VERBOSE) + if (compileverbose) { + if ((t_inmemory) && (s_inmemory)) { + /* mem -> mem */ + printf("M%3i <- M%3i",t_regoff,s_regoff); + } else if (s_inmemory) { + /* mem -> reg */ + printf("R%3i <- M%3i",t_regoff,s_regoff); + } else if (t_inmemory) { + /* reg -> mem */ + printf("M%3i <- R%3i",t_regoff,s_regoff); + } else { + /* reg -> reg */ + printf("R%3i <- R%3i",t_regoff,s_regoff); + } + printf("\n"); } +#endif /* defined(SSA_DEBUG_VERBOSE) */ } - - codegen_finish(jd, (s4) (cd->mcodeptr - cd->mcodebase)); - - /* everything's ok */ - - return true; } +void cg_move(codegendata *cd, s4 type, s4 src_regoff, s4 src_flags, + s4 dst_regoff, s4 dst_flags) { + if ((IS_INMEMORY(dst_flags)) && (IS_INMEMORY(src_flags))) { + /* mem -> mem */ + if (dst_regoff != src_regoff) { + if (!IS_2_WORD_TYPE(type)) { + if (IS_FLT_DBL_TYPE(type)) { + emit_flds_membase(cd, REG_SP, src_regoff * 4); + emit_fstps_membase(cd, REG_SP, dst_regoff * 4); + } else{ + emit_mov_membase_reg(cd, REG_SP, src_regoff * 4, + REG_ITMP1); + emit_mov_reg_membase(cd, REG_ITMP1, REG_SP, dst_regoff * 4); + } + } else { /* LONG OR DOUBLE */ + if (IS_FLT_DBL_TYPE(type)) { + emit_fldl_membase( cd, REG_SP, src_regoff * 4); + emit_fstpl_membase(cd, REG_SP, dst_regoff * 4); + } else { + emit_mov_membase_reg(cd, REG_SP, src_regoff * 4, + REG_ITMP1); + emit_mov_reg_membase(cd, REG_ITMP1, REG_SP, dst_regoff * 4); + emit_mov_membase_reg(cd, REG_SP, src_regoff * 4 + 4, + REG_ITMP1); + emit_mov_reg_membase(cd, REG_ITMP1, REG_SP, + dst_regoff * 4 + 4); + } + } + } + } else { + if (IS_FLT_DBL_TYPE(type)) { + log_text("cg_move: flt/dbl type have to be in memory\n"); +/* assert(0); */ + } + if (IS_2_WORD_TYPE(type)) { + log_text("cg_move: longs have to be in memory\n"); +/* assert(0); */ + } + if (IS_INMEMORY(src_flags)) { + /* mem -> reg */ + emit_mov_membase_reg(cd, REG_SP, src_regoff * 4, dst_regoff); + } else if (IS_INMEMORY(dst_flags)) { + /* reg -> mem */ + emit_mov_reg_membase(cd, src_regoff, REG_SP, dst_regoff * 4); + } else { + /* reg -> reg */ + /* only ints can be in regs on i386 */ + M_INTMOVE(src_regoff,dst_regoff); + } + } +} +#endif /* defined(ENABLE_SSA) */ /* createcompilerstub ********************************************************** @@ -5388,7 +4357,7 @@ gen_method: *******************************************************************************/ -#define COMPILERSTUB_DATASIZE 2 * SIZEOF_VOID_P +#define COMPILERSTUB_DATASIZE 3 * SIZEOF_VOID_P #define COMPILERSTUB_CODESIZE 12 #define COMPILERSTUB_SIZE COMPILERSTUB_DATASIZE + COMPILERSTUB_CODESIZE @@ -5398,6 +4367,7 @@ u1 *createcompilerstub(methodinfo *m) { u1 *s; /* memory to hold the stub */ ptrint *d; + codeinfo *code; codegendata *cd; s4 dumpsize; @@ -5415,15 +4385,18 @@ u1 *createcompilerstub(methodinfo *m) cd = DNEW(codegendata); cd->mcodeptr = s; - /* Store the methodinfo* in the same place as in the methodheader - for compiled methods. */ + /* Store the codeinfo pointer in the same place as in the + methodheader for compiled methods. */ + + code = code_codeinfo_new(m); d[0] = (ptrint) asm_call_jit_compiler; d[1] = (ptrint) m; + d[2] = (ptrint) code; - M_MOV_IMM(m, REG_ITMP1); + /* code for the stub */ - /* we use REG_ITMP3 cause ECX (REG_ITMP2) is used for patching */ + M_MOV_IMM(m, REG_ITMP1); /* method info */ M_MOV_IMM(asm_call_jit_compiler, REG_ITMP3); M_JMP(REG_ITMP3); @@ -5446,29 +4419,24 @@ u1 *createcompilerstub(methodinfo *m) *******************************************************************************/ -#if defined(USE_THREADS) && defined(NATIVE_THREADS) -/* this way we can call the function directly with a memory call */ - -static java_objectheader **(*callgetexceptionptrptr)() = builtin_get_exceptionptrptr; -#endif - u1 *createnativestub(functionptr f, jitdata *jd, methoddesc *nmd) { methodinfo *m; + codeinfo *code; codegendata *cd; registerdata *rd; methoddesc *md; - s4 stackframesize; s4 nativeparams; s4 i, j; /* count variables */ s4 t; - s4 s1, s2, disp; + s4 s1, s2; /* get required compiler data */ - m = jd->m; - cd = jd->cd; - rd = jd->rd; + m = jd->m; + code = jd->code; + cd = jd->cd; + rd = jd->rd; /* set some variables */ @@ -5477,112 +4445,51 @@ u1 *createnativestub(functionptr f, jitdata *jd, methoddesc *nmd) /* calculate stackframe size */ - stackframesize = + cd->stackframesize = sizeof(stackframeinfo) / SIZEOF_VOID_P + sizeof(localref_table) / SIZEOF_VOID_P + 1 + /* function pointer */ 4 * 4 + /* 4 arguments (start_native_call) */ nmd->memuse; + /* keep stack 16-byte aligned */ + + cd->stackframesize |= 0x3; + /* create method header */ - (void) dseg_addaddress(cd, m); /* MethodPointer */ - (void) dseg_adds4(cd, stackframesize * 4); /* FrameSize */ - (void) dseg_adds4(cd, 0); /* IsSync */ - (void) dseg_adds4(cd, 0); /* IsLeaf */ - (void) dseg_adds4(cd, 0); /* IntSave */ - (void) dseg_adds4(cd, 0); /* FltSave */ + (void) dseg_addaddress(cd, code); /* CodeinfoPointer */ + (void) dseg_adds4(cd, cd->stackframesize * 4); /* FrameSize */ + (void) dseg_adds4(cd, 0); /* IsSync */ + (void) dseg_adds4(cd, 0); /* IsLeaf */ + (void) dseg_adds4(cd, 0); /* IntSave */ + (void) dseg_adds4(cd, 0); /* FltSave */ (void) dseg_addlinenumbertablesize(cd); - (void) dseg_adds4(cd, 0); /* ExTableSize */ - - /* initialize mcode variables */ - - cd->mcodeptr = (u1 *) cd->mcodebase; - cd->mcodeend = (s4 *) (cd->mcodebase + cd->mcodesize); + (void) dseg_adds4(cd, 0); /* ExTableSize */ /* generate native method profiling code */ - if (opt_prof) { + if (JITDATA_HAS_FLAG_INSTRUMENT(jd)) { /* count frequency */ - M_MOV_IMM(m, REG_ITMP1); - M_IADD_IMM_MEMBASE(1, REG_ITMP1, OFFSET(methodinfo, frequency)); + M_MOV_IMM(code, REG_ITMP1); + M_IADD_IMM_MEMBASE(1, REG_ITMP1, OFFSET(codeinfo, frequency)); } /* calculate stackframe size for native function */ - M_ASUB_IMM(stackframesize * 4, REG_SP); + M_ASUB_IMM(cd->stackframesize * 4, REG_SP); #if !defined(NDEBUG) - if (opt_verbosecall) { - s4 p, t; - - disp = stackframesize * 4; - - M_ASUB_IMM(TRACE_ARGS_NUM * 8 + 4, REG_SP); - - for (p = 0; p < md->paramcount && p < TRACE_ARGS_NUM; p++) { - t = md->paramtypes[p].type; - if (IS_INT_LNG_TYPE(t)) { - if (IS_2_WORD_TYPE(t)) { - M_ILD(REG_ITMP1, REG_SP, - 4 + TRACE_ARGS_NUM * 8 + 4 + disp); - M_ILD(REG_ITMP2, REG_SP, - 4 + TRACE_ARGS_NUM * 8 + 4 + disp + 4); - M_IST(REG_ITMP1, REG_SP, p * 8); - M_IST(REG_ITMP2, REG_SP, p * 8 + 4); - - } else if (t == TYPE_ADR) { - M_ALD(REG_ITMP1, REG_SP, - 4 + TRACE_ARGS_NUM * 8 + 4 + disp); - M_CLR(REG_ITMP2); - M_AST(REG_ITMP1, REG_SP, p * 8); - M_AST(REG_ITMP2, REG_SP, p * 8 + 4); - - } else { - M_ILD(EAX, REG_SP, 4 + TRACE_ARGS_NUM * 8 + 4 + disp); - i386_cltd(cd); - M_IST(EAX, REG_SP, p * 8); - M_IST(EDX, REG_SP, p * 8 + 4); - } - - } else { - if (!IS_2_WORD_TYPE(t)) { - i386_flds_membase(cd, REG_SP, - 4 + TRACE_ARGS_NUM * 8 + 4 + disp); - i386_fstps_membase(cd, REG_SP, p * 8); - i386_alu_reg_reg(cd, ALU_XOR, REG_ITMP2, REG_ITMP2); - M_IST(REG_ITMP2, REG_SP, p * 8 + 4); - - } else { - i386_fldl_membase(cd, REG_SP, - 4 + TRACE_ARGS_NUM * 8 + 4 + disp); - i386_fstpl_membase(cd, REG_SP, p * 8); - } - } - disp += (IS_2_WORD_TYPE(t)) ? 8 : 4; - } - - M_CLR(REG_ITMP1); - for (p = md->paramcount; p < TRACE_ARGS_NUM; p++) { - M_IST(REG_ITMP1, REG_SP, p * 8); - M_IST(REG_ITMP1, REG_SP, p * 8 + 4); - } - - M_AST_IMM(m, REG_SP, TRACE_ARGS_NUM * 8); - - M_MOV_IMM(builtin_trace_args, REG_ITMP1); - M_CALL(REG_ITMP1); - - M_AADD_IMM(TRACE_ARGS_NUM * 8 + 4, REG_SP); - } -#endif /* !defined(NDEBUG) */ + if (JITDATA_HAS_FLAG_VERBOSECALL(jd)) + emit_verbosecall_enter(jd); +#endif /* get function address (this must happen before the stackframeinfo) */ #if !defined(WITH_STATIC_CLASSPATH) if (f == NULL) { - codegen_addpatchref(cd, cd->mcodeptr, PATCHER_resolve_native, m, 0); + codegen_addpatchref(cd, PATCHER_resolve_native, m, 0); if (opt_showdisassemble) { M_NOP; M_NOP; M_NOP; M_NOP; M_NOP; @@ -5595,29 +4502,29 @@ u1 *createnativestub(functionptr f, jitdata *jd, methoddesc *nmd) /* Mark the whole fpu stack as free for native functions (only for saved */ /* register count == 0). */ - i386_ffree_reg(cd, 0); - i386_ffree_reg(cd, 1); - i386_ffree_reg(cd, 2); - i386_ffree_reg(cd, 3); - i386_ffree_reg(cd, 4); - i386_ffree_reg(cd, 5); - i386_ffree_reg(cd, 6); - i386_ffree_reg(cd, 7); + emit_ffree_reg(cd, 0); + emit_ffree_reg(cd, 1); + emit_ffree_reg(cd, 2); + emit_ffree_reg(cd, 3); + emit_ffree_reg(cd, 4); + emit_ffree_reg(cd, 5); + emit_ffree_reg(cd, 6); + emit_ffree_reg(cd, 7); /* prepare data structures for native function call */ M_MOV(REG_SP, REG_ITMP1); - M_AADD_IMM(stackframesize * 4, REG_ITMP1); + M_AADD_IMM(cd->stackframesize * 4, REG_ITMP1); M_AST(REG_ITMP1, REG_SP, 0 * 4); M_IST_IMM(0, REG_SP, 1 * 4); - dseg_adddata(cd, cd->mcodeptr); + dseg_adddata(cd); M_MOV(REG_SP, REG_ITMP2); - M_AADD_IMM(stackframesize * 4 + SIZEOF_VOID_P, REG_ITMP2); + M_AADD_IMM(cd->stackframesize * 4 + SIZEOF_VOID_P, REG_ITMP2); M_AST(REG_ITMP2, REG_SP, 2 * 4); - M_ALD(REG_ITMP3, REG_SP, stackframesize * 4); + M_ALD(REG_ITMP3, REG_SP, cd->stackframesize * 4); M_AST(REG_ITMP3, REG_SP, 3 * 4); M_MOV_IMM(codegen_start_native_call, REG_ITMP1); M_CALL(REG_ITMP1); @@ -5632,7 +4539,7 @@ u1 *createnativestub(functionptr f, jitdata *jd, methoddesc *nmd) if (!md->params[i].inmemory) { /* no integer argument registers */ } else { /* float/double in memory can be copied like int/longs */ - s1 = (md->params[i].regoff + stackframesize + 1) * 4; + s1 = (md->params[i].regoff + cd->stackframesize + 1) * 4; s2 = nmd->params[j].regoff * 4; M_ILD(REG_ITMP1, REG_SP, s1); @@ -5647,11 +4554,11 @@ u1 *createnativestub(functionptr f, jitdata *jd, methoddesc *nmd) /* if function is static, put class into second argument */ if (m->flags & ACC_STATIC) - M_AST_IMM((ptrint) m->class, REG_SP, 1 * 4); + M_AST_IMM(m->class, REG_SP, 1 * 4); /* put env into first argument */ - M_AST_IMM((ptrint) _Jv_env, REG_SP, 0 * 4); + M_AST_IMM(_Jv_env, REG_SP, 0 * 4); /* call the native function */ @@ -5659,87 +4566,55 @@ u1 *createnativestub(functionptr f, jitdata *jd, methoddesc *nmd) /* save return value */ - if (IS_INT_LNG_TYPE(md->returntype.type)) { - if (IS_2_WORD_TYPE(md->returntype.type)) - M_IST(REG_RESULT2, REG_SP, 2 * 4); - M_IST(REG_RESULT, REG_SP, 1 * 4); - - } else { - if (IS_2_WORD_TYPE(md->returntype.type)) - i386_fstl_membase(cd, REG_SP, 1 * 4); - else - i386_fsts_membase(cd, REG_SP, 1 * 4); + if (md->returntype.type != TYPE_VOID) { + if (IS_INT_LNG_TYPE(md->returntype.type)) { + if (IS_2_WORD_TYPE(md->returntype.type)) + M_IST(REG_RESULT2, REG_SP, 2 * 4); + M_IST(REG_RESULT, REG_SP, 1 * 4); + } + else { + if (IS_2_WORD_TYPE(md->returntype.type)) + emit_fstl_membase(cd, REG_SP, 1 * 4); + else + emit_fsts_membase(cd, REG_SP, 1 * 4); + } } - /* remove data structures for native function call */ +#if !defined(NDEBUG) + if (JITDATA_HAS_FLAG_VERBOSECALL(jd)) + emit_verbosecall_exit(jd); +#endif + + /* remove native stackframe info */ M_MOV(REG_SP, REG_ITMP1); - M_AADD_IMM(stackframesize * 4, REG_ITMP1); + M_AADD_IMM(cd->stackframesize * 4, REG_ITMP1); M_AST(REG_ITMP1, REG_SP, 0 * 4); M_MOV_IMM(codegen_finish_native_call, REG_ITMP1); M_CALL(REG_ITMP1); + M_MOV(REG_RESULT, REG_ITMP2); /* REG_ITMP3 == REG_RESULT2 */ -#if !defined(NDEBUG) - if (opt_verbosecall) { - /* restore return value */ + /* restore return value */ + if (md->returntype.type != TYPE_VOID) { if (IS_INT_LNG_TYPE(md->returntype.type)) { if (IS_2_WORD_TYPE(md->returntype.type)) M_ILD(REG_RESULT2, REG_SP, 2 * 4); M_ILD(REG_RESULT, REG_SP, 1 * 4); - - } else { + } + else { if (IS_2_WORD_TYPE(md->returntype.type)) - i386_fldl_membase(cd, REG_SP, 1 * 4); + emit_fldl_membase(cd, REG_SP, 1 * 4); else - i386_flds_membase(cd, REG_SP, 1 * 4); + emit_flds_membase(cd, REG_SP, 1 * 4); } + } - M_ASUB_IMM(4 + 8 + 8 + 4, REG_SP); - - M_AST_IMM((ptrint) m, REG_SP, 0); - - M_IST(REG_RESULT, REG_SP, 4); - M_IST(REG_RESULT2, REG_SP, 4 + 4); - - i386_fstl_membase(cd, REG_SP, 4 + 8); - i386_fsts_membase(cd, REG_SP, 4 + 8 + 8); - - M_MOV_IMM(builtin_displaymethodstop, REG_ITMP1); - M_CALL(REG_ITMP1); - - M_AADD_IMM(4 + 8 + 8 + 4, REG_SP); - } -#endif /* !defined(NDEBUG) */ + M_AADD_IMM(cd->stackframesize * 4, REG_SP); /* check for exception */ -#if defined(USE_THREADS) && defined(NATIVE_THREADS) -/* i386_call_mem(cd, (ptrint) builtin_get_exceptionptrptr); */ - i386_call_mem(cd, (ptrint) &callgetexceptionptrptr); -#else - M_MOV_IMM(&_no_threads_exceptionptr, REG_RESULT); -#endif - /* we can't use REG_ITMP3 == REG_RESULT2 */ - M_ALD(REG_ITMP2, REG_RESULT, 0); - - /* restore return value */ - - if (IS_INT_LNG_TYPE(md->returntype.type)) { - if (IS_2_WORD_TYPE(md->returntype.type)) - M_ILD(REG_RESULT2, REG_SP, 2 * 4); - M_ILD(REG_RESULT, REG_SP, 1 * 4); - - } else { - if (IS_2_WORD_TYPE(md->returntype.type)) - i386_fldl_membase(cd, REG_SP, 1 * 4); - else - i386_flds_membase(cd, REG_SP, 1 * 4); - } - - M_AADD_IMM(stackframesize * 4, REG_SP); - M_TEST(REG_ITMP2); M_BNE(1); @@ -5747,17 +4622,7 @@ u1 *createnativestub(functionptr f, jitdata *jd, methoddesc *nmd) /* handle exception */ -#if defined(USE_THREADS) && defined(NATIVE_THREADS) - i386_push_reg(cd, REG_ITMP2); -/* i386_call_mem(cd, (ptrint) builtin_get_exceptionptrptr); */ - i386_call_mem(cd, (ptrint) &callgetexceptionptrptr); - i386_mov_imm_membase(cd, 0, REG_RESULT, 0); - i386_pop_reg(cd, REG_ITMP1_XPTR); -#else M_MOV(REG_ITMP2, REG_ITMP1_XPTR); - M_MOV_IMM(&_no_threads_exceptionptr, REG_ITMP2); - i386_mov_imm_membase(cd, 0, REG_ITMP2, 0); -#endif M_ALD(REG_ITMP2_XPC, REG_SP, 0); M_ASUB_IMM(2, REG_ITMP2_XPC); @@ -5765,65 +4630,13 @@ u1 *createnativestub(functionptr f, jitdata *jd, methoddesc *nmd) M_JMP(REG_ITMP3); - /* process patcher calls **************************************************/ - - { - u1 *xcodeptr; - patchref *pref; - u8 mcode; - u1 *tmpmcodeptr; - - for (pref = cd->patchrefs; pref != NULL; pref = pref->next) { - /* Get machine code which is patched back in later. A - `call rel32' is 5 bytes long. */ - - xcodeptr = cd->mcodebase + pref->branchpos; - mcode = *((u8 *) xcodeptr); - - /* patch in `call rel32' to call the following code */ + /* generate patcher stubs */ - tmpmcodeptr = cd->mcodeptr; /* save current mcodeptr */ - cd->mcodeptr = xcodeptr; /* set mcodeptr to patch position */ - - M_CALL_IMM(tmpmcodeptr - (xcodeptr + PATCHER_CALL_SIZE)); - - cd->mcodeptr = tmpmcodeptr; /* restore the current mcodeptr */ - - /* save REG_ITMP3 */ - - M_PUSH(REG_ITMP3); - - /* move pointer to java_objectheader onto stack */ - -#if defined(USE_THREADS) && defined(NATIVE_THREADS) - /* create a virtual java_objectheader */ - - (void) dseg_addaddress(cd, get_dummyLR()); /* monitorPtr */ - disp = dseg_addaddress(cd, NULL); /* vftbl */ - - M_MOV_IMM(0, REG_ITMP3); - dseg_adddata(cd, cd->mcodeptr); - M_AADD_IMM(disp, REG_ITMP3); - M_PUSH(REG_ITMP3); -#else - M_PUSH_IMM(0); -#endif - - /* move machine code bytes and classinfo pointer onto stack */ - - M_PUSH_IMM((mcode >> 32)); - M_PUSH_IMM(mcode); - M_PUSH_IMM(pref->ref); - M_PUSH_IMM(pref->patcher); - - M_MOV_IMM(asm_wrapper_patcher, REG_ITMP3); - M_JMP(REG_ITMP3); - } - } + emit_patcher_stubs(jd); - codegen_finish(jd, (s4) (cd->mcodeptr - cd->mcodebase)); + codegen_finish(jd); - return jd->code->entrypoint; + return code->entrypoint; }