X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fvm%2Fjit%2Fi386%2Farch.h;h=d5d71e803b16127c5de2c7b5e152dedb7c7b0073;hb=976ff9a651cac48e31d37dc91e82f2e488c45ea3;hp=75ee54e589474866a04dbbd197868d10a57fa468;hpb=ea49d6d92011168cb805868676ac4316b79e4903;p=cacao.git diff --git a/src/vm/jit/i386/arch.h b/src/vm/jit/i386/arch.h index 75ee54e58..d5d71e803 100644 --- a/src/vm/jit/i386/arch.h +++ b/src/vm/jit/i386/arch.h @@ -1,9 +1,9 @@ -/* vm/jit/i386/arch.h - architecture defines for i386 +/* src/vm/jit/i386/arch.h - architecture defines for i386 - Copyright (C) 1996-2005 R. Grafl, A. Krall, C. Kruegel, C. Oates, - R. Obermaisser, M. Platter, M. Probst, S. Ring, E. Steiner, - C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich, J. Wenninger, - Institut f. Computersprachen - TU Wien + Copyright (C) 1996-2005, 2006, 2007 R. Grafl, A. Krall, C. Kruegel, + C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring, + E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich, + J. Wenninger, Institut f. Computersprachen - TU Wien This file is part of CACAO. @@ -19,14 +19,8 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA - 02111-1307, USA. - - Contact: cacao@complang.tuwien.ac.at - - Authors: Christian Thalinger - - $Id: arch.h 1887 2005-01-27 11:29:56Z twisti $ + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + 02110-1301, USA. */ @@ -34,6 +28,10 @@ #ifndef _ARCH_H #define _ARCH_H +#define JIT_COMPILER_VIA_SIGNAL + +#include "config.h" + /* define x86 register numbers ************************************************/ @@ -46,80 +44,83 @@ #define ESI 6 #define EDI 7 +/* define architecture features ***********************************************/ + +#define SUPPORT_DIVISION 1 +#define SUPPORT_LONG 1 -/* preallocated registers *****************************************************/ +#define SUPPORT_I2F 1 +#define SUPPORT_I2D 1 +#define SUPPORT_L2F 1 +#define SUPPORT_L2D 1 -/* integer registers */ - -#define REG_RESULT EAX /* to deliver method results */ -#define REG_RESULT2 EDX /* to deliver long method results */ +/* ATTENTION: i386 architectures support these conversions, but we + need the builtin functions in corner cases */ +#define SUPPORT_F2I 0 +#define SUPPORT_F2L 0 +#define SUPPORT_D2I 0 +#define SUPPORT_D2L 0 -#define REG_ITMP1 EAX /* temporary register */ -#define REG_ITMP2 ECX /* temporary register */ -#define REG_ITMP3 EDX /* temporary register */ +#define SUPPORT_LONG_ADD 1 +#define SUPPORT_LONG_CMP 1 +#define SUPPORT_LONG_CMP_CONST 1 +#define SUPPORT_LONG_LOGICAL 1 +#define SUPPORT_LONG_SHIFT 1 +#define SUPPORT_LONG_MUL 1 +#define SUPPORT_LONG_DIV 0 -#define REG_NULL -1 /* used for reg_of_var where d is not needed */ +#define SUPPORT_LONG_DIV_POW2 1 +#define SUPPORT_LONG_REM_POW2 0 -#define REG_ITMP1_XPTR EAX /* exception pointer = temporary register 1 */ -#define REG_ITMP2_XPC ECX /* exception pc = temporary register 2 */ +#define SUPPORT_CONST_LOGICAL 1 /* AND, OR, XOR with immediates */ +#define SUPPORT_CONST_MUL 1 /* mutiply with immediate */ -#define REG_SP ESP /* stack pointer */ +#define SUPPORT_CONST_STORE 1 /* do we support const stores */ +#define SUPPORT_CONST_STORE_ZERO_ONLY 0 /* on some risc machines we can */ + /* only store REG_ZERO */ -/* floating point registers */ -#define REG_FRESULT 0 /* to deliver floating point method results */ -#define REG_FTMP1 6 /* temporary floating point register */ -#define REG_FTMP2 7 /* temporary floating point register */ -#define REG_FTMP3 7 /* temporary floating point register */ +/* float **********************************************************************/ +#define SUPPORT_FLOAT 1 -#define INT_SAV_CNT 3 /* number of int callee saved registers */ -#define INT_ARG_CNT 0 /* number of int argument registers */ +#if defined(ENABLE_SOFT_FLOAT_CMP) +# define SUPPORT_FLOAT_CMP 0 +#else +# define SUPPORT_FLOAT_CMP 1 +#endif -#define FLT_SAV_CNT 0 /* number of flt callee saved registers */ -#define FLT_ARG_CNT 0 /* number of flt argument registers */ -#define TRACE_ARGS_NUM 8 +/* double *********************************************************************/ +#define SUPPORT_DOUBLE 1 -/* define architecture features ***********************************************/ +#if defined(ENABLE_SOFT_FLOAT_CMP) +# define SUPPORT_DOUBLE_CMP 0 +#else +# define SUPPORT_DOUBLE_CMP 1 +#endif -#define POINTERSIZE 4 -#define WORDS_BIGENDIAN 0 -#define U8_AVAILABLE 1 +/* define SUPPORT_COMBINE_INTEGER_REGISTERS */ -#define USE_CODEMMAP 1 -#define SUPPORT_DIVISION 1 -#define SUPPORT_LONG 1 -#define SUPPORT_FLOAT 1 -#define SUPPORT_DOUBLE 1 +/* branches *******************************************************************/ -#define SUPPORT_IFCVT 1 -#define SUPPORT_FICVT 1 +#define SUPPORT_BRANCH_CONDITIONAL_CONDITION_REGISTER 1 +#define SUPPORT_BRANCH_CONDITIONAL_ONE_INTEGER_REGISTER 0 +#define SUPPORT_BRANCH_CONDITIONAL_TWO_INTEGER_REGISTERS 0 +#define SUPPORT_BRANCH_CONDITIONAL_UNSIGNED_CONDITIONS 1 -#define SUPPORT_LONG_ADD 1 -#define SUPPORT_LONG_CMP 1 -#define SUPPORT_LONG_LOG 1 -#define SUPPORT_LONG_SHIFT 1 -#define SUPPORT_LONG_MUL 1 -#define SUPPORT_LONG_DIV 0 -#define SUPPORT_LONG_ICVT 1 -#define SUPPORT_LONG_FCVT 1 -#define SUPPORT_LOGICAL_CONST 1 /* AND, OR, XOR with immediates */ +/* exceptions *****************************************************************/ -#define SUPPORT_CONST_ASTORE 1 /* do we support const astores */ -#define SUPPORT_ONLY_ZERO_ASTORE 0 /* on risc machines we can only store */ - /* REG_ZERO */ +#define SUPPORT_HARDWARE_DIVIDE_BY_ZERO 1 -#define USEBUILTINTABLE -#define CONDITIONAL_LOADCONST +/* replacement ****************************************************************/ -/* #define CONSECUTIVE_INTARGS */ -/* #define CONSECUTIVE_FLOATARGS */ +#define REPLACEMENT_PATCH_SIZE 2 /* bytes */ #endif /* _ARCH_H */