X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fvm%2Fjit%2Fi386%2Farch.h;h=a092680b855e5386dfa90c09a1da41f5d77d5e55;hb=f1bcc1f443ffa393025fa158d4bf6487a7316c4d;hp=48345fb0e65b7e5fe2c24291a632226597f96a7d;hpb=36fc3b5717690b88aa4ef9c8e28a0e3ab142ad48;p=cacao.git

diff --git a/src/vm/jit/i386/arch.h b/src/vm/jit/i386/arch.h
index 48345fb0e..a092680b8 100644
--- a/src/vm/jit/i386/arch.h
+++ b/src/vm/jit/i386/arch.h
@@ -1,9 +1,7 @@
 /* src/vm/jit/i386/arch.h - architecture defines for i386
 
-   Copyright (C) 1996-2005 R. Grafl, A. Krall, C. Kruegel, C. Oates,
-   R. Obermaisser, M. Platter, M. Probst, S. Ring, E. Steiner,
-   C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich, J. Wenninger,
-   Institut f. Computersprachen - TU Wien
+   Copyright (C) 1996-2010
+   CACAOVM - Verein zur Foerderung der freien virtuellen Maschine CACAO
 
    This file is part of CACAO.
 
@@ -19,16 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
-   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.
-
-   Contact: cacao@complang.tuwien.ac.at
-
-   Authors: Christian Thalinger
-
-   Changes:
-
-   $Id: arch.h 4133 2006-01-10 22:18:29Z twisti $
+   Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+   02110-1301, USA.
 
 */
 
@@ -36,9 +26,28 @@
 #ifndef _ARCH_H
 #define _ARCH_H
 
+#define JIT_COMPILER_VIA_SIGNAL
+
+#include "config.h"
+
 
 /* define x86 register numbers ************************************************/
 
+#if !defined(__SOLARIS__) || !defined(SKIP_REG_DEFS)
+
+#if defined(__SOLARIS__)
+
+#undef EAX
+#undef ECX
+#undef EDX
+#undef EBX
+#undef ESP
+#undef EBP
+#undef ESI
+#undef EDI
+
+#endif
+
 #define EAX    0
 #define ECX    1
 #define EDX    2
@@ -48,16 +57,12 @@
 #define ESI    6
 #define EDI    7
 
-/* define architecture features ***********************************************/
-
-#define U8_AVAILABLE                     1
+#endif
 
-#define USEBUILTINTABLE
+/* define architecture features ***********************************************/
 
 #define SUPPORT_DIVISION                 1
 #define SUPPORT_LONG                     1
-#define SUPPORT_FLOAT                    1
-#define SUPPORT_DOUBLE                   1
 
 #define SUPPORT_I2F                      1
 #define SUPPORT_I2D                      1
@@ -72,13 +77,16 @@
 #define SUPPORT_D2L                      0
 
 #define SUPPORT_LONG_ADD                 1
-#define SUPPORT_LONG_CMP                 1
+#define SUPPORT_LONG_CMP                 0
 #define SUPPORT_LONG_CMP_CONST           1
 #define SUPPORT_LONG_LOGICAL             1
 #define SUPPORT_LONG_SHIFT               1
 #define SUPPORT_LONG_MUL                 1
 #define SUPPORT_LONG_DIV                 0
 
+#define SUPPORT_LONG_DIV_POW2            1
+#define SUPPORT_LONG_REM_POW2            0
+
 #define SUPPORT_CONST_LOGICAL            1  /* AND, OR, XOR with immediates   */
 #define SUPPORT_CONST_MUL                1  /* mutiply with immediate         */
 
@@ -86,11 +94,66 @@
 #define SUPPORT_CONST_STORE_ZERO_ONLY    0  /* on some risc machines we can   */
                                             /* only store REG_ZERO            */
 
-#define CONDITIONAL_LOADCONST            1
-	 
-#define HAS_4BYTE_STACKSLOT
+
+/* float **********************************************************************/
+
+#define SUPPORT_FLOAT                    1
+
+#if defined(ENABLE_SOFT_FLOAT_CMP)
+# define SUPPORT_FLOAT_CMP               0
+#else
+# define SUPPORT_FLOAT_CMP               1
+#endif
+
+
+/* double *********************************************************************/
+
+#define SUPPORT_DOUBLE                   1
+
+#if defined(ENABLE_SOFT_FLOAT_CMP)
+# define SUPPORT_DOUBLE_CMP              0
+#else
+# define SUPPORT_DOUBLE_CMP              1
+#endif
+
+
 /* define SUPPORT_COMBINE_INTEGER_REGISTERS */
 
+
+/* branches *******************************************************************/
+
+#define SUPPORT_BRANCH_CONDITIONAL_CONDITION_REGISTER       1
+#define SUPPORT_BRANCH_CONDITIONAL_ONE_INTEGER_REGISTER     0
+#define SUPPORT_BRANCH_CONDITIONAL_TWO_INTEGER_REGISTERS    0
+#define SUPPORT_BRANCH_CONDITIONAL_UNSIGNED_CONDITIONS      1
+
+
+/* exceptions *****************************************************************/
+
+#define SUPPORT_HARDWARE_DIVIDE_BY_ZERO  1
+
+
+/* stackframe *****************************************************************/
+
+#define STACKFRMAE_RA_BETWEEN_FRAMES              1
+#define STACKFRAME_RA_TOP_OF_FRAME                0
+#define STACKFRAME_RA_LINKAGE_AREA                0
+#define STACKFRAME_LEAFMETHODS_RA_REGISTER        0
+#define STACKFRAME_SYNC_NEEDS_TWO_SLOTS           0
+
+
+/* replacement ****************************************************************/
+
+#define REPLACEMENT_PATCH_SIZE           2       /* bytes */
+
+/* subtype ********************************************************************/
+
+#define USES_NEW_SUBTYPE                 1
+
+/* memory barriers ************************************************************/
+
+#define CAS_PROVIDES_FULL_BARRIER        1
+
 #endif /* _ARCH_H */