X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fvm%2Fjit%2Fcodegen-common.cpp;h=5536ba819c29871a28a64885a8905814e161f586;hb=735bdda890a385d1fa9cc532faadbbc96f2d1218;hp=9920715b1c8d52b982c87f1cebc4db25c39afada;hpb=ba550ed57d3abaf63a64f70308d6a4164ee18835;p=cacao.git

diff --git a/src/vm/jit/codegen-common.cpp b/src/vm/jit/codegen-common.cpp
index 9920715b1..5536ba819 100644
--- a/src/vm/jit/codegen-common.cpp
+++ b/src/vm/jit/codegen-common.cpp
@@ -1250,6 +1250,13 @@ bool codegen_emit(jitdata *jd)
 				emit_nullpointer_check(cd, iptr, s1);
 				break;
 
+			case ICMD_BREAKPOINT: /* ...  ==> ...                             */
+			                      /* sx.val.anyptr = Breakpoint               */
+
+				patcher_add_patch_ref(jd, PATCHER_breakpoint, iptr->sx.val.anyptr, 0);
+				PATCHER_NOPS;
+	 			break;
+
 #if defined(ENABLE_SSA)
 			case ICMD_GETEXCEPTION:
 
@@ -1349,9 +1356,13 @@ bool codegen_emit(jitdata *jd)
 			case ICMD_IMUL:       /* ..., val1, val2  ==> ..., val1 * val2    */
 			case ICMD_IMULCONST:  /* ..., value  ==> ..., value * constant    */
 			                      /* sx.val.i = constant                      */
+			case ICMD_IMULPOW2:   /* ..., value  ==> ..., value * (2 ^ constant) */
+			                      /* sx.val.i = constant                      */
 			case ICMD_LMUL:       /* ..., val1, val2  ==> ..., val1 * val2    */
 			case ICMD_LMULCONST:  /* ..., value  ==> ..., value * constant    */
 			                      /* sx.val.l = constant                      */
+			case ICMD_LMULPOW2:   /* ..., value  ==> ..., value * (2 ^ constant) */
+			                      /* sx.val.l = constant                      */
 			case ICMD_IDIV:       /* ..., val1, val2  ==> ..., val1 / val2    */
 			case ICMD_IREM:       /* ..., val1, val2  ==> ..., val1 % val2    */
 			case ICMD_IDIVPOW2:   /* ..., value  ==> ..., value >> constant   */
@@ -1496,16 +1507,20 @@ bool codegen_emit(jitdata *jd)
 #if defined(__I386__)
 				// Generate architecture specific instructions.
 				codegen_emit_instruction(jd, iptr);
+				break;
 #else
+			{
+				fieldinfo* fi;
+				patchref_t* pr;
 				if (INSTRUCTION_IS_UNRESOLVED(iptr)) {
 					unresolved_field* uf = iptr->sx.s23.s3.uf;
 					fieldtype = uf->fieldref->parseddesc.fd->type;
 					disp      = dseg_add_unique_address(cd, 0);
 
-					patcher_add_patch_ref(jd, PATCHER_get_putstatic, uf, disp);
+					pr = patcher_add_patch_ref(jd, PATCHER_get_putstatic, uf, disp);
 				}
 				else {
-					fieldinfo* fi = iptr->sx.s23.s3.fmiref->p.field;
+					fi        = iptr->sx.s23.s3.fmiref->p.field;
 					fieldtype = fi->type;
 					disp      = dseg_add_address(cd, fi->value);
 
@@ -1516,11 +1531,14 @@ bool codegen_emit(jitdata *jd)
 					}
 				}
 
+#if defined(USES_PATCHABLE_MEMORY_BARRIER)
+				codegen_emit_patchable_barrier(iptr, cd, pr, fi);
+#endif
+
 				// XXX X86_64: Here We had this:
 				/* This approach is much faster than moving the field
 				   address inline into a register. */
 
-				// XXX ARM: M_DSEG_LOAD(REG_ITMP3, disp);
 				M_ALD_DSEG(REG_ITMP1, disp);
 
 				switch (fieldtype) {
@@ -1546,24 +1564,30 @@ bool codegen_emit(jitdata *jd)
 					break;
 				}
 				emit_store_dst(jd, iptr, d);
-#endif
 				break;
+			}
+#endif
 
 			case ICMD_PUTSTATIC:  /* ..., value  ==> ...                      */
 
 #if defined(__I386__)
 				// Generate architecture specific instructions.
 				codegen_emit_instruction(jd, iptr);
+				break;
 #else
+			{
+				fieldinfo* fi;
+				patchref_t* pr;
+
 				if (INSTRUCTION_IS_UNRESOLVED(iptr)) {
 					unresolved_field* uf = iptr->sx.s23.s3.uf;
 					fieldtype = uf->fieldref->parseddesc.fd->type;
 					disp      = dseg_add_unique_address(cd, 0);
 
-					patcher_add_patch_ref(jd, PATCHER_get_putstatic, uf, disp);
+					pr = patcher_add_patch_ref(jd, PATCHER_get_putstatic, uf, disp);
 				}
 				else {
-					fieldinfo* fi = iptr->sx.s23.s3.fmiref->p.field;
+					fi = iptr->sx.s23.s3.fmiref->p.field;
 					fieldtype = fi->type;
 					disp      = dseg_add_address(cd, fi->value);
 
@@ -1578,7 +1602,6 @@ bool codegen_emit(jitdata *jd)
 				/* This approach is much faster than moving the field
 				   address inline into a register. */
 
-				// XXX ARM: M_DSEG_LOAD(REG_ITMP3, disp);
 				M_ALD_DSEG(REG_ITMP1, disp);
 
 				switch (fieldtype) {
@@ -1603,8 +1626,12 @@ bool codegen_emit(jitdata *jd)
 					M_DST(s1, REG_ITMP1, 0);
 					break;
 				}
+#if defined(USES_PATCHABLE_MEMORY_BARRIER)
+				codegen_emit_patchable_barrier(iptr, cd, pr, fi);
 #endif
 				break;
+			}
+#endif
 
 			/* branch operations **********************************************/
 
@@ -1832,16 +1859,22 @@ bool codegen_emit(jitdata *jd)
 
 				REPLACEMENT_POINT_RETURN(cd, iptr);
 				s1 = emit_load_s1(jd, iptr, REG_FRESULT);
-				// XXX ARM: Here this was M_CAST_F2I(s1, REG_RESULT);
+#if !defined(SUPPORT_PASS_FLOATARGS_IN_INTREGS)
 				emit_fmove(cd, s1, REG_FRESULT);
+#else
+				M_CAST_F2I(s1, REG_RESULT);
+#endif
 				goto nowperformreturn;
 
 			case ICMD_DRETURN:    /* ..., retvalue ==> ...                    */
 
 				REPLACEMENT_POINT_RETURN(cd, iptr);
 				s1 = emit_load_s1(jd, iptr, REG_FRESULT);
-				// XXX ARM: Here this was M_CAST_D2L(s1, REG_RESULT_PACKED);
+#if !defined(SUPPORT_PASS_FLOATARGS_IN_INTREGS)
 				emit_dmove(cd, s1, REG_FRESULT);
+#else
+				M_CAST_D2L(s1, REG_LRESULT);
+#endif
 				goto nowperformreturn;
 
 nowperformreturn:
@@ -1947,36 +1980,36 @@ gen_method:
 						continue;
 
 					if (!md->params[i].inmemory) {
-						assert(ARG_CNT > 0);
-						s1 = emit_load(jd, iptr, var, d);
-
 						switch (var->type) {
 						case TYPE_ADR:
 						case TYPE_INT:
-							assert(INT_ARG_CNT > 0);
+							s1 = emit_load(jd, iptr, var, d);
 							emit_imove(cd, s1, d);
 							break;
 
-#if 0 //XXX For ARM:
-if (!md->params[s3].inmemory) {
-	s1 = emit_load(jd, iptr, var, REG_FTMP1);
-	if (IS_2_WORD_TYPE(var->type))
-		M_CAST_D2L(s1, d);
-	else
-		M_CAST_F2I(s1, d);
-}
-#endif //XXX End of ARM!
-
 						case TYPE_LNG:
+							s1 = emit_load(jd, iptr, var, d);
 							emit_lmove(cd, s1, d);
 							break;
 
 						case TYPE_FLT:
+#if !defined(SUPPORT_PASS_FLOATARGS_IN_INTREGS)
+							s1 = emit_load(jd, iptr, var, d);
 							emit_fmove(cd, s1, d);
+#else
+							s1 = emit_load(jd, iptr, var, REG_FTMP1);
+							M_CAST_F2I(s1, d);
+#endif
 							break;
 
 						case TYPE_DBL:
+#if !defined(SUPPORT_PASS_FLOATARGS_IN_INTREGS)
+							s1 = emit_load(jd, iptr, var, d);
 							emit_dmove(cd, s1, d);
+#else
+							s1 = emit_load(jd, iptr, var, REG_FTMP1);
+							M_CAST_D2L(s1, d);
+#endif
 							break;
 						}
 					}
@@ -2064,27 +2097,25 @@ if (!md->params[s3].inmemory) {
 					emit_store_dst(jd, iptr, s1);
 					break;
 
-#if 0 //XXX For ARM!!!
-#if !defined(ENABLE_SOFTFLOAT)
-				} else {
-					s1 = codegen_reg_of_dst(jd, iptr, REG_FTMP1);
-					if (IS_2_WORD_TYPE(d))
-						M_CAST_L2D(REG_RESULT_PACKED, s1);
-					else
-						M_CAST_I2F(REG_RESULT, s1);
-				}
-#endif /* !defined(ENABLE_SOFTFLOAT) */
-#endif //XXX End of ARM
-
 				case TYPE_FLT:
+#if !defined(SUPPORT_PASS_FLOATARGS_IN_INTREGS)
 					s1 = codegen_reg_of_dst(jd, iptr, REG_FRESULT);
 					emit_fmove(cd, REG_FRESULT, s1);
+#else
+					s1 = codegen_reg_of_dst(jd, iptr, REG_FTMP1);
+					M_CAST_I2F(REG_RESULT, s1);
+#endif
 					emit_store_dst(jd, iptr, s1);
 					break;
 
 				case TYPE_DBL:
+#if !defined(SUPPORT_PASS_FLOATARGS_IN_INTREGS)
 					s1 = codegen_reg_of_dst(jd, iptr, REG_FRESULT);
 					emit_dmove(cd, REG_FRESULT, s1);
+#else
+					s1 = codegen_reg_of_dst(jd, iptr, REG_FTMP1);
+					M_CAST_L2D(REG_LRESULT, s1);
+#endif
 					emit_store_dst(jd, iptr, s1);
 					break;