X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Ftextmode_vga%2Ftextmode_vga_v_sm.vhd;fp=src%2Ftextmode_vga%2Ftextmode_vga_v_sm.vhd;h=694d95fb676262d6e58a5ab79b4d9618bffefcd3;hb=c277013ff527af6b7951add2934084bb5e4e3a25;hp=0000000000000000000000000000000000000000;hpb=38ff39be4ca9a16fe08b3652ce616d150b3e139c;p=hwmod.git

diff --git a/src/textmode_vga/textmode_vga_v_sm.vhd b/src/textmode_vga/textmode_vga_v_sm.vhd
new file mode 100644
index 0000000..694d95f
--- /dev/null
+++ b/src/textmode_vga/textmode_vga_v_sm.vhd
@@ -0,0 +1,30 @@
+-------------------------------------------------------------------------
+--
+-- Filename: textmode_vga_v_sm.vhd
+-- =========
+--
+-- Short Description:
+-- ==================
+--   Entity declaration of the vertical VGA timing finite state machine
+--
+-------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.math_pkg.all;
+use work.textmode_vga_pkg.all;
+use work.font_pkg.all;
+
+entity textmode_vga_v_sm is
+  port
+  (
+    sys_clk, sys_res_n : in std_logic;
+       
+    is_data_line : out std_logic;
+    char_line_cnt : out std_logic_vector(log2c(LINE_COUNT) - 1 downto 0);
+    char_height_pixel : out std_logic_vector(log2c(CHAR_HEIGHT) - 1 downto 0);
+    is_eol : in std_logic;
+    
+    vsync_n : out std_logic
+  );
+end entity textmode_vga_v_sm;