X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fsuperio%2Fite%2Fit8718f%2Fit8718f_early_serial.c;h=76f9b0daf6e3214d3dee5ce5e6200c52d9000c4e;hb=5c6bae213ea55e1436e010706560d86120b0b286;hp=212f964604187642a0fdd684577fedf4aa07fe21;hpb=1549f2a557058000d65d913ffb8b60487bdc09ab;p=coreboot.git

diff --git a/src/superio/ite/it8718f/it8718f_early_serial.c b/src/superio/ite/it8718f/it8718f_early_serial.c
index 212f96460..76f9b0daf 100644
--- a/src/superio/ite/it8718f/it8718f_early_serial.c
+++ b/src/superio/ite/it8718f/it8718f_early_serial.c
@@ -1,5 +1,5 @@
 /*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
  *
  * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
  *
@@ -24,7 +24,7 @@
 /* The base address is 0x2e or 0x4e, depending on config bytes. */
 #define SIO_BASE                     0x2e
 #define SIO_INDEX                    SIO_BASE
-#define SIO_DATA                     SIO_BASE+1
+#define SIO_DATA                     (SIO_BASE + 1)
 
 /* Global configuration registers. */
 #define IT8718F_CONFIG_REG_CC        0x02 /* Configure Control (write-only). */
@@ -33,11 +33,7 @@
 #define IT8718F_CONFIG_REG_CLOCKSEL  0x23 /* Clock Selection. */
 #define IT8718F_CONFIG_REG_SWSUSP    0x24 /* Software Suspend, Flash I/F. */
 
-#define IT8718F_CONFIGURATION_PORT   0x2e /* Write-only. */
-
-/* The content of IT8718F_CONFIG_REG_LDN (index 0x07) must be set to the
-   LDN the register belongs to, before you can access the register. */
-static void it8718f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
+static void it8718f_sio_write(u8 ldn, u8 index, u8 value)
 {
 	outb(IT8718F_CONFIG_REG_LDN, SIO_BASE);
 	outb(ldn, SIO_DATA);
@@ -45,43 +41,64 @@ static void it8718f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
 	outb(value, SIO_DATA);
 }
 
-/* Enable the peripheral devices on the IT8718F Super I/O chip. */
-static void it8718f_enable_serial(device_t dev, unsigned iobase)
+static void it8718f_enter_conf(void)
 {
-	/* (1) Enter the configuration state (MB PnP mode). */
+	u16 port = 0x2e; /* TODO: Don't hardcode! */
+
+	outb(0x87, port);
+	outb(0x01, port);
+	outb(0x55, port);
+	outb((port == 0x4e) ? 0xaa : 0x55, port);
+}
+
+static void it8718f_exit_conf(void)
+{
+	it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CC, 0x02);
+}
+
+/* Select 24MHz CLKIN (48MHz default). */
+void it8718f_24mhz_clkin(void)
+{
+	it8718f_enter_conf();
+	it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CLOCKSEL, 0x1);
+	it8718f_exit_conf();
+}
 
-	/* Perform MB PnP setup to put the SIO chip at 0x2e. */
-	/* Base address 0x2e: 0x87 0x01 0x55 0x55. */
-	/* Base address 0x4e: 0x87 0x01 0x55 0xaa. */
-	outb(0x87, IT8718F_CONFIGURATION_PORT);
-	outb(0x01, IT8718F_CONFIGURATION_PORT);
-	outb(0x55, IT8718F_CONFIGURATION_PORT);
-	outb(0x55, IT8718F_CONFIGURATION_PORT);
+/*
+ * GIGABYTE uses a special Super I/O register to protect its Dual BIOS
+ * mechanism. It lives in the GPIO LDN. However, register 0xEF is not
+ * mentioned in the IT8718F datasheet so just hardcode it to 0x7E for now.
+ */
+void it8718f_disable_reboot(void)
+{
+	it8718f_enter_conf();
+	it8718f_sio_write(IT8718F_GPIO, 0xEF, 0x7E);
+	it8718f_exit_conf();
+}
+
+/* Enable the serial port(s). */
+void it8718f_enable_serial(device_t dev, u16 iobase)
+{
+	/* (1) Enter the configuration state (MB PnP mode). */
+	it8718f_enter_conf();
 
 	/* (2) Modify the data of configuration registers. */
 
-	/* Select the chip to configure (if there's more than one).
-           Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
-           If this register is not written, both chips are configured. */
-	/* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CONFIGSEL, 0x00); */
+	/*
+	 * Select the chip to configure (if there's more than one).
+	 * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
+	 * If this register is not written, both chips are configured.
+	 */
 
-	/* Enable all devices. */
-	it8718f_sio_write(IT8718F_FDC,  0x30, 0x1); /* Floppy */
-	it8718f_sio_write(IT8718F_SP1,  0x30, 0x1); /* Serial port 1 */
-	it8718f_sio_write(IT8718F_SP2,  0x30, 0x1); /* Serial port 2 */
-	it8718f_sio_write(IT8718F_PP,   0x30, 0x1); /* Parallel port */
-	it8718f_sio_write(IT8718F_EC,   0x30, 0x1); /* Environment controller */
-	it8718f_sio_write(IT8718F_KBCK, 0x30, 0x1); /* Keyboard */
-	it8718f_sio_write(IT8718F_KBCM, 0x30, 0x1); /* Mouse */
-	it8718f_sio_write(IT8718F_IR,   0x30, 0x1); /* Consumer IR */
+	/* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CONFIGSEL, 0x00); */
 
-	/* Select 24MHz/48MHz CLKIN (set/clear bit 0). TODO: Needed? */
-	/* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CLOCKSEL, 0x01); */
+	/* Enable serial port(s). */
+	it8718f_sio_write(IT8718F_SP1, 0x30, 0x1); /* Serial port 1 */
+	it8718f_sio_write(IT8718F_SP2, 0x30, 0x1); /* Serial port 2 */
 
 	/* Clear software suspend mode (clear bit 0). TODO: Needed? */
 	/* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_SWSUSP, 0x00); */
 
 	/* (3) Exit the configuration state (MB PnP mode). */
-	it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CC, 0x02);
+	it8718f_exit_conf();
 }
-