X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fsouthbridge%2Fnvidia%2Fck804%2Fusb.c;h=8aba68ce9c196225cfe460e423da8d709e6f79a5;hb=7e2fbd5dd3a9271edaf4c0b3fcc2301e10a83f8f;hp=45ee734eb14161128bb9f2cbea1435b054bfa6f5;hpb=ecab12a09e9d38e8e6f6ce5079fbf740d2cde1a5;p=coreboot.git

diff --git a/src/southbridge/nvidia/ck804/usb.c b/src/southbridge/nvidia/ck804/usb.c
index 45ee734eb..8aba68ce9 100644
--- a/src/southbridge/nvidia/ck804/usb.c
+++ b/src/southbridge/nvidia/ck804/usb.c
@@ -28,20 +28,22 @@
 static void usb1_init(struct device *dev)
 {
 	struct southbridge_nvidia_ck804_config const *conf = dev->chip_info;
-	if (conf->usb1_hc_reset) {
-		/*
-		 * Somehow the warm reset does not really reset the USB
-		 * controller. Later, during boot, when the Bus Master bit is
-		 * set, the USB controller trashes the memory, causing weird
-		 * misbehavior. Was detected on Sun Ultra40, where mptable
-		 * was damaged.
-		 */
-		uint32_t bar0 = pci_read_config32(dev, 0x10);
-		uint32_t *regs = (uint32_t *) (bar0 & ~0xfff);
 
-		/* OHCI USB HCCommandStatus Register, HostControllerReset bit */
-		regs[2] |= 1;
-	}
+	if (!conf->usb1_hc_reset)
+		return;
+
+	/*
+	 * Somehow the warm reset does not really reset the USB
+	 * controller. Later, during boot, when the Bus Master bit is
+	 * set, the USB controller trashes the memory, causing weird
+	 * misbehavior. Was detected on Sun Ultra40, where mptable
+	 * was damaged.
+	 */
+	u32 bar0 = pci_read_config32(dev, 0x10);
+	u32 *regs = (u32 *) (bar0 & ~0xfff);
+
+	/* OHCI USB HCCommandStatus Register, HostControllerReset bit */
+	regs[2] |= 1;
 }
 
 static struct device_operations usb_ops = {