X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fsouthbridge%2Fintel%2Fi82801gx%2Fi82801gx_lpc.c;h=f486c1ebf849cfe60727dc06f317a306a6c47753;hb=74d1a6e8a166cd477f667a6fcb1e96b8a0cbdac1;hp=29546348b1d737477d13f818c8e13f07b6652a55;hpb=9ceae905f10a555835db0af072c3adfff98b3a7b;p=coreboot.git diff --git a/src/southbridge/intel/i82801gx/i82801gx_lpc.c b/src/southbridge/intel/i82801gx/i82801gx_lpc.c index 29546348b..f486c1ebf 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_lpc.c +++ b/src/southbridge/intel/i82801gx/i82801gx_lpc.c @@ -26,59 +26,26 @@ #include #include #include +#include #include "i82801gx.h" -#include "../../../northbridge/intel/i945/ich7.h" +#define NMI_OFF 0 -#define MAINBOARD_POWER_OFF 0 -#define MAINBOARD_POWER_ON 1 - -#ifndef MAINBOARD_POWER_ON_AFTER_FAIL -#define MAINBOARD_POWER_ON_AFTER_FAIL MAINBOARD_POWER_ON -#endif - -#define NMI_OFF 0 +#define ENABLE_ACPI_MODE_IN_COREBOOT 0 +#define TEST_SMM_FLASH_LOCKDOWN 0 typedef struct southbridge_intel_i82801gx_config config_t; -/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control - * 0x00 - 0000 = Reserved - * 0x01 - 0001 = Reserved - * 0x02 - 0010 = Reserved - * 0x03 - 0011 = IRQ3 - * 0x04 - 0100 = IRQ4 - * 0x05 - 0101 = IRQ5 - * 0x06 - 0110 = IRQ6 - * 0x07 - 0111 = IRQ7 - * 0x08 - 1000 = Reserved - * 0x09 - 1001 = IRQ9 - * 0x0A - 1010 = IRQ10 - * 0x0B - 1011 = IRQ11 - * 0x0C - 1100 = IRQ12 - * 0x0D - 1101 = Reserved - * 0x0E - 1110 = IRQ14 - * 0x0F - 1111 = IRQ15 - * PIRQ[n]_ROUT[7] - PIRQ Routing Control - * 0x80 - The PIRQ is not routed. - */ - -#define PIRQA 0x03 -#define PIRQB 0x05 -#define PIRQC 0x06 -#define PIRQD 0x07 -#define PIRQE 0x09 -#define PIRQF 0x0A -#define PIRQG 0x0B -#define PIRQH 0x0C - static void i82801gx_enable_apic(struct device *dev) { int i; u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)0xfec00000; - volatile u32 *ioapic_data = (volatile u32 *)0xfec00010; + volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); + volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - /* Enable ACPI I/O and power management. */ + /* Enable ACPI I/O and power management. + * Set SCI IRQ to IRQ9 + */ pci_write_config8(dev, ACPI_CNTL, 0x80); *ioapic_index = 0; @@ -86,16 +53,16 @@ static void i82801gx_enable_apic(struct device *dev) *ioapic_index = 0; reg32 = *ioapic_data; - printk_debug("Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); + printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); if (reg32 != (1 << 25)) die("APIC Error\n"); - printk_spew("Dumping IOAPIC registers\n"); + printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); for (i=0; i<3; i++) { *ioapic_index = i; - printk_spew(" reg 0x%04x:", i); + printk(BIOS_SPEW, " reg 0x%04x:", i); reg32 = *ioapic_data; - printk_spew(" 0x%08x\n", reg32); + printk(BIOS_SPEW, " 0x%08x\n", reg32); } *ioapic_index = 3; /* Select Boot Configuration register. */ @@ -109,6 +76,27 @@ static void i82801gx_enable_serial_irqs(struct device *dev) (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); } +/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control + * 0x00 - 0000 = Reserved + * 0x01 - 0001 = Reserved + * 0x02 - 0010 = Reserved + * 0x03 - 0011 = IRQ3 + * 0x04 - 0100 = IRQ4 + * 0x05 - 0101 = IRQ5 + * 0x06 - 0110 = IRQ6 + * 0x07 - 0111 = IRQ7 + * 0x08 - 1000 = Reserved + * 0x09 - 1001 = IRQ9 + * 0x0A - 1010 = IRQ10 + * 0x0B - 1011 = IRQ11 + * 0x0C - 1100 = IRQ12 + * 0x0D - 1101 = Reserved + * 0x0E - 1110 = IRQ14 + * 0x0F - 1111 = IRQ15 + * PIRQ[n]_ROUT[7] - PIRQ Routing Control + * 0x80 - The PIRQ is not routed. + */ + static void i82801gx_pirq_init(device_t dev) { device_t irq_dev; @@ -180,31 +168,53 @@ static void i82801gx_gpi_routing(device_t dev) pci_write_config32(dev, 0xb8, reg32); } +extern u8 acpi_slp_type; + static void i82801gx_power_options(device_t dev) { u8 reg8; - u16 reg16; + u16 reg16, pmbase; + u32 reg32; + const char *state; + /* Get the chip configuration */ + config_t *config = dev->chip_info; - uint32_t pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - uint32_t nmi_option; + int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int nmi_option; /* Which state do we want to goto after g3 (power restored)? * 0 == S0 Full On * 1 == S5 Soft Off + * + * If the option is not existent (Laptops), use MAINBOARD_POWER_ON. */ - get_option("power_on_after_fail", &pwr_on); + if (get_option(&pwr_on, "power_on_after_fail") < 0) + pwr_on = MAINBOARD_POWER_ON; + reg8 = pci_read_config8(dev, GEN_PMCON_3); reg8 &= 0xfe; - if (pwr_on) { - reg8 &= ~1; - } else { + switch (pwr_on) { + case MAINBOARD_POWER_OFF: reg8 |= 1; + state = "off"; + break; + case MAINBOARD_POWER_ON: + reg8 &= ~1; + state = "on"; + break; + case MAINBOARD_POWER_KEEP: + reg8 &= ~1; + state = "state keep"; + break; + default: + state = "undefined"; } + reg8 |= (3 << 4); /* avoid #S4 assertions */ reg8 &= ~(1 << 3); /* minimum asssertion is 1 to 2 RTCCLK */ pci_write_config8(dev, GEN_PMCON_3, reg8); - printk_info("Set power %s after power failure.\n", pwr_on ? "on" : "off"); + printk(BIOS_INFO, "Set power %s after power failure.\n", state); /* Set up NMI on errors. */ reg8 = inb(0x61); @@ -216,31 +226,54 @@ static void i82801gx_power_options(device_t dev) reg8 = inb(0x70); nmi_option = NMI_OFF; - get_option("nmi", &nmi_option); + get_option(&nmi_option, "nmi"); if (nmi_option) { - printk_info ("NMI sources enabled.\n"); + printk(BIOS_INFO, "NMI sources enabled.\n"); reg8 &= ~(1 << 7); /* Set NMI. */ } else { - printk_info ("NMI sources disabled.\n"); + printk(BIOS_INFO, "NMI sources disabled.\n"); reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ } outb(reg8, 0x70); - // Enable CPU_SLP# and Intel Speedstep, set SMI# rate down + /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */ reg16 = pci_read_config16(dev, GEN_PMCON_1); - reg16 &= ~((3 << 0) | (1 << 10)); - reg16 |= (1 << 3) | (1 << 5); - reg16 |= (1 << 2); // CLKRUN_EN + reg16 &= ~(3 << 0); // SMI# rate 1 minute + reg16 |= (1 << 2); // CLKRUN_EN - Mobile/Ultra only + reg16 |= (1 << 3); // Speedstep Enable - Mobile/Ultra only + reg16 |= (1 << 5); // CPUSLP_EN Desktop only + // another laptop wants this? + // reg16 &= ~(1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only + reg16 |= (1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only +#if DEBUG_PERIODIC_SMIS + /* Set DEBUG_PERIODIC_SMIS in i82801gx.h to debug using + * periodic SMIs. + */ + reg16 |= (3 << 0); // Periodic SMI every 8s +#endif pci_write_config16(dev, GEN_PMCON_1, reg16); // Set the board's GPI routing. i82801gx_gpi_routing(dev); + + pmbase = pci_read_config16(dev, 0x40) & 0xfffe; + + outl(config->gpe0_en, pmbase + GPE0_EN); + outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN); + + /* Set up power management block and determine sleep mode */ + reg32 = inl(pmbase + 0x04); // PM1_CNT + + reg32 &= ~(7 << 10); // SLP_TYP + reg32 |= (1 << 1); // enable C3->C0 transition on bus master + reg32 |= (1 << 0); // SCI_EN + outl(reg32, pmbase + 0x04); } static void i82801gx_configure_cstates(device_t dev) { u8 reg8; - + reg8 = pci_read_config8(dev, 0xa9); // Cx state configuration reg8 |= (1 << 4) | (1 << 3) | (1 << 2); // Enable Popup & Popdown pci_write_config8(dev, 0xa9, reg8); @@ -264,7 +297,7 @@ static void i82801gx_rtc_init(struct device *dev) reg8 &= ~RTC_BATTERY_DEAD; pci_write_config8(dev, GEN_PMCON_3, reg8); } - printk_debug("rtc_failed = 0x%x\n", rtc_failed); + printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); rtc_init(rtc_failed); } @@ -272,31 +305,34 @@ static void i82801gx_rtc_init(struct device *dev) static void enable_hpet(void) { u32 reg32; - - /* Leave HPET at default address, but enable it */ - reg32 = RCBA32(0x3404); + + /* Move HPET to default address 0xfed00000 and enable it */ + reg32 = RCBA32(HPTC); reg32 |= (1 << 7); // HPET Address Enable - RCBA32(0x3404) = reg32; + reg32 &= ~(3 << 0); + RCBA32(HPTC) = reg32; } static void enable_clock_gating(void) { u32 reg32; - + /* Enable Clock Gating for most devices */ - reg32 = RCBA32(0x341c); + reg32 = RCBA32(CG); reg32 |= (1 << 31); // LPC clock gating reg32 |= (1 << 30); // PATA clock gating // SATA clock gating reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24); reg32 |= (1 << 23); // AC97 clock gating - reg32 |= (1 << 20) | (1 << 19); // USB EHCI clock gating + reg32 |= (1 << 19); // USB EHCI clock gating reg32 |= (1 << 3) | (1 << 1); // DMI clock gating reg32 |= (1 << 2); // PCIe clock gating; - RCBA32(0x341c) = reg32; + reg32 &= ~(1 << 20); // No static clock gating for USB + reg32 &= ~( (1 << 29) | (1 << 28) ); // Disable UHCI clock gating + RCBA32(CG) = reg32; } -#if HAVE_SMI_HANDLER +#if CONFIG_HAVE_SMI_HANDLER static void i82801gx_lock_smm(struct device *dev) { void smm_lock(void); @@ -305,44 +341,44 @@ static void i82801gx_lock_smm(struct device *dev) #endif #if ENABLE_ACPI_MODE_IN_COREBOOT - printk_debug("Enabling ACPI via APMC:\n"); + printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); outb(0xe1, 0xb2); // Enable ACPI mode - printk_debug("done.\n"); + printk(BIOS_DEBUG, "done.\n"); #else - printk_debug("Disabling ACPI via APMC:\n"); + printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(0x1e, 0xb2); // Disable ACPI mode - printk_debug("done.\n"); + printk(BIOS_DEBUG, "done.\n"); #endif - /* Don't allow evil boot loaders, kernels, or + /* Don't allow evil boot loaders, kernels, or * userspace applications to deceive us: */ smm_lock(); #if TEST_SMM_FLASH_LOCKDOWN /* Now try this: */ - printk_debug("Locking BIOS to RO... "); + printk(BIOS_DEBUG, "Locking BIOS to RO... "); reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", + printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", (reg8&1)?"rw":"ro"); reg8 &= ~(1 << 0); /* clear BIOSWE */ pci_write_config8(dev, 0xdc, reg8); reg8 |= (1 << 1); /* set BLE */ pci_write_config8(dev, 0xdc, reg8); - printk_debug("ok.\n"); + printk(BIOS_DEBUG, "ok.\n"); reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", + printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", (reg8&1)?"rw":"ro"); - printk_debug("Writing:\n"); + printk(BIOS_DEBUG, "Writing:\n"); *(volatile u8 *)0xfff00000 = 0x00; - printk_debug("Testing:\n"); + printk(BIOS_DEBUG, "Testing:\n"); reg8 |= (1 << 0); /* set BIOSWE */ pci_write_config8(dev, 0xdc, reg8); reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", + printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", (reg8&1)?"rw":"ro"); - printk_debug("Done.\n"); + printk(BIOS_DEBUG, "Done.\n"); #endif } #endif @@ -357,15 +393,21 @@ static void i82801gx_spi_init(void) RCBA16(SPIBASE + 2) = spicontrol; } -static void i82801gx_fixups(void) +static void i82801gx_fixups(struct device *dev) { /* This needs to happen after PCI enumeration */ RCBA32(0x1d40) |= 1; + + /* USB Transient Disconnect Detect: + * Prevent a SE0 condition on the USB ports from being + * interpreted by the UHCI controller as a disconnect + */ + pci_write_config8(dev, 0xad, 0x3); } static void lpc_init(struct device *dev) { - printk_debug("i82801gx: lpc_init\n"); + printk(BIOS_DEBUG, "i82801gx: lpc_init\n"); /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); @@ -401,13 +443,17 @@ static void lpc_init(struct device *dev) setup_i8259(); -#if HAVE_SMI_HANDLER + /* The OS should do this? */ + /* Interrupt 9 should be level triggered (SCI) */ + i8259_configure_irq_trigger(9, 1); + +#if CONFIG_HAVE_SMI_HANDLER i82801gx_lock_smm(dev); #endif i82801gx_spi_init(); - i82801gx_fixups(); + i82801gx_fixups(dev); } static void i82801gx_lpc_read_resources(device_t dev) @@ -419,18 +465,21 @@ static void i82801gx_lpc_read_resources(device_t dev) /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->flags = - IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->flags = - IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -} - -static void i82801gx_lpc_enable_resources(device_t dev) -{ - pci_dev_enable_resources(dev); - enable_childrens_resources(dev); + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = IO_APIC_ADDR; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } static void set_subsystem(device_t dev, unsigned vendor, unsigned device) @@ -451,13 +500,20 @@ static struct pci_operations pci_ops = { static struct device_operations device_ops = { .read_resources = i82801gx_lpc_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = i82801gx_lpc_enable_resources, + .enable_resources = pci_dev_enable_resources, .init = lpc_init, .scan_bus = scan_static_bus, .enable = i82801gx_enable, .ops_pci = &pci_ops, }; +/* 82801GH (ICH7 DH) */ +static const struct pci_driver ich7_dh_lpc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x27b0, +}; + /* 82801GB/GR (ICH7/ICH7R) */ static const struct pci_driver ich7_ich7r_lpc __pci_driver = { .ops = &device_ops,