X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fsouthbridge%2Fintel%2Fi82801gx%2Fi82801gx_ide.c;h=84b50d6535cd694f05daa63c2184a5bc7445710e;hb=c02b4fc9db3c3c1e263027382697b566127f66bb;hp=28a1c055eaa4d05aa213b1ad0330653ff96d0c78;hpb=27852aba6787617ca5656995cbc7e8ef0a3ea22c;p=coreboot.git

diff --git a/src/southbridge/intel/i82801gx/i82801gx_ide.c b/src/southbridge/intel/i82801gx/i82801gx_ide.c
index 28a1c055e..84b50d653 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_ide.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_ide.c
@@ -35,9 +35,9 @@ static void ide_init(struct device *dev)
 	/* Get the chip configuration */
 	config_t *config = dev->chip_info;
 
-	printk_debug("i82801gx_ide: initializing... ");
+	printk(BIOS_DEBUG, "i82801gx_ide: initializing... ");
 	if (config == NULL) {
-		printk_err("\ni82801gx_ide: Not mentioned in mainboard's Config.lb!\n");
+		printk(BIOS_ERR, "\ni82801gx_ide: Not mentioned in mainboard's Config.lb!\n");
 		// Trying to set somewhat safe defaults instead of bailing out.
 		enable_primary = enable_secondary = 1;
 	} else {
@@ -61,7 +61,7 @@ static void ide_init(struct device *dev)
 		ideTimingConfig |= (3 << 8); // RCT = 1 clock
 		ideTimingConfig |= (1 << 1); // IE0
 		ideTimingConfig |= (1 << 0); // TIME0
-		printk_debug("IDE0 ");
+		printk(BIOS_DEBUG, "IDE0 ");
 	}
 	pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig);
 
@@ -75,7 +75,7 @@ static void ide_init(struct device *dev)
 		ideTimingConfig |= (3 << 8); // RCT = 1 clock
 		ideTimingConfig |= (1 << 1); // IE0
 		ideTimingConfig |= (1 << 0); // TIME0
-		printk_debug("IDE1 ");
+		printk(BIOS_DEBUG, "IDE1 ");
 	}
 	pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig);
 
@@ -92,7 +92,7 @@ static void ide_init(struct device *dev)
 	/* Interrupt Pin is set by D31IP.PIP */
 	pci_write_config32(dev, INTR_LN, 0xff); /* Int 15 */
 
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 }
 
 static void ide_set_subsystem(device_t dev, unsigned vendor, unsigned device)