X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fsouthbridge%2Fintel%2Fi82801cx%2Fi82801cx.h;h=da518a3660ad5ee6b4eeb13ca55b732fba5ab5c4;hb=b69cb5a31058c0295f2d810c852cc5b52d77225c;hp=e0d377a9cdc75cc7d1de3f567f029c72aebdd753;hpb=b907d321a5d0957f5cbb03d8f9c8d0ff0c23523b;p=coreboot.git

diff --git a/src/southbridge/intel/i82801cx/i82801cx.h b/src/southbridge/intel/i82801cx/i82801cx.h
index e0d377a9c..da518a366 100644
--- a/src/southbridge/intel/i82801cx/i82801cx.h
+++ b/src/southbridge/intel/i82801cx/i82801cx.h
@@ -32,9 +32,7 @@ void i82801cx_hard_reset(void);
 #define RTC_POWER_FAILED		(1<<1)
 #define SLEEP_AFTER_POWER_FAIL	(1<<0)
 
-/********************************************************************/
-/*							IDE Controller                          */
-/********************************************************************/
+/* IDE controller: */
 
 // PCI Configuration Space (D31:F1)
 #define IDE_TIM_PRI		0x40		// IDE timings, primary
@@ -44,9 +42,7 @@ void i82801cx_hard_reset(void);
 // IDE_TIM bits
 #define IDE_DECODE_ENABLE	(1<<15)
 
-/********************************************************************/
-/*								SMBus                               */
-/********************************************************************/
+/* SMBus: */
 
 // PCI Configuration Space (D31:F3)
 #define SMB_BASE	0x20