X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fsouthbridge%2Fintel%2Fi82801bx%2Fi82801bx_smbus.h;h=24c08cd35726b22233a826a43ec117456e75c8c5;hb=3b8db813809f3485ceaa77bf91595e64cc588d92;hp=a8739588332276dcef09e0c9dd8b23164e96b733;hpb=c3af12fb8a930b8885b1c6c6b35d2aeff155b3c3;p=coreboot.git

diff --git a/src/southbridge/intel/i82801bx/i82801bx_smbus.h b/src/southbridge/intel/i82801bx/i82801bx_smbus.h
index a87395883..24c08cd35 100644
--- a/src/southbridge/intel/i82801bx/i82801bx_smbus.h
+++ b/src/southbridge/intel/i82801bx/i82801bx_smbus.h
@@ -25,7 +25,7 @@ static void smbus_delay(void)
 	inb(0x80);
 }
 
-static int smbus_wait_until_ready(void)
+static int smbus_wait_until_ready(u16 smbus_io_base)
 {
 	unsigned loops = SMBUS_TIMEOUT;
 	unsigned char byte;
@@ -33,12 +33,12 @@ static int smbus_wait_until_ready(void)
 		smbus_delay();
 		if (--loops == 0)
 			break;
-		byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
+		byte = inb(smbus_io_base + SMBHSTSTAT);
 	} while (byte & 1);
 	return loops ? 0 : -1;
 }
 
-static int smbus_wait_until_done(void)
+static int smbus_wait_until_done(u16 smbus_io_base)
 {
 	unsigned loops = SMBUS_TIMEOUT;
 	unsigned char byte;
@@ -46,135 +46,54 @@ static int smbus_wait_until_done(void)
 		smbus_delay();
 		if (--loops == 0)
 			break;
-		byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
+		byte = inb(smbus_io_base + SMBHSTSTAT);
 	} while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0);
 	return loops ? 0 : -1;
 }
 
-#ifdef UNUNSED_CODE
-static int smbus_wait_until_blk_done(void)
-{
-	unsigned loops = SMBUS_TIMEOUT;
-	unsigned char byte;
-	do {
-		smbus_delay();
-		if (--loops == 0)
-			break;
-		byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
-	} while ((byte & (1 << 7)) == 0);
-	return loops ? 0 : -1;
-}
-#endif
-
-static int do_smbus_read_byte(unsigned device, unsigned address)
+static int do_smbus_read_byte(u16 smbus_io_base, unsigned device,
+			      unsigned address)
 {
 	unsigned char global_status_register;
 	unsigned char byte;
 
-	if (smbus_wait_until_ready() < 0) {
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
 		return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
 	}
 	/* Setup transaction */
 	/* Disable interrupts */
-	outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
+	outb(inb(smbus_io_base + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
 	/* Set the device I'm talking too */
-	outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD);
+	outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD);
 	/* Set the command/address... */
-	outb(address & 0xff, SMBUS_IO_BASE + SMBHSTCMD);
+	outb(address & 0xff, smbus_io_base + SMBHSTCMD);
 	/* Set up for a byte data read */
-	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2),
-	     (SMBUS_IO_BASE + SMBHSTCTL));
+	outb((inb(smbus_io_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
+	     (smbus_io_base + SMBHSTCTL));
 	/* Clear any lingering errors, so the transaction will run */
-	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
+	outb(inb(smbus_io_base + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
 
 	/* Clear the data byte... */
-	outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
+	outb(0, smbus_io_base + SMBHSTDAT0);
 
 	/* Start the command */
-	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40),
-	     SMBUS_IO_BASE + SMBHSTCTL);
+	outb((inb(smbus_io_base + SMBHSTCTL) | 0x40),
+	     smbus_io_base + SMBHSTCTL);
 
 	/* Poll for transaction completion */
-	if (smbus_wait_until_done() < 0) {
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
 		return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
 	}
 
-	global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT);
+	global_status_register = inb(smbus_io_base + SMBHSTSTAT);
 
 	/* Ignore the "In Use" status... */
 	global_status_register &= ~(3 << 5);
 
 	/* Read results of transaction */
-	byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
+	byte = inb(smbus_io_base + SMBHSTDAT0);
 	if (global_status_register != (1 << 1)) {
 		return SMBUS_ERROR;
 	}
 	return byte;
 }
-
-#ifdef UNUNSED_CODE
-static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd,
-				unsigned data1, unsigned data2)
-{
-	unsigned char byte;
-	unsigned char stat;
-	int i;
-
-	print_err("Untested smbus_write_block called\n");
-
-	/* Clear the PM timeout flags, SECOND_TO_STS */
-	outw(inw(PMBASE_ADDR + 0x66), PMBASE_ADDR + 0x66);
-
-	if (smbus_wait_until_ready() < 0) {
-		return -2;
-	}
-
-	/* Setup transaction */
-	/* Obtain ownership */
-	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
-	for (stat = 0; (stat & 0x40) == 0;) {
-		stat = inb(SMBUS_IO_BASE + SMBHSTSTAT);
-	}
-	/* Clear the done bit */
-	outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT);
-	/* Disable interrupts */
-	outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
-
-	/* Set the device I'm talking too */
-	outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD);
-
-	/* Set the command address */
-	outb(cmd & 0xff, SMBUS_IO_BASE + SMBHSTCMD);
-
-	/* Set the block length */
-	outb(length & 0xff, SMBUS_IO_BASE + SMBHSTDAT0);
-
-	/* Try sending out the first byte of data here */
-	byte = (data1 >> (0)) & 0x0ff;
-	outb(byte, SMBUS_IO_BASE + SMBBLKDAT);
-	/* Issue a block write command */
-	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x5 << 2) | 0x40,
-	     SMBUS_IO_BASE + SMBHSTCTL);
-
-	for (i = 0; i < length; i++) {
-		/* Poll for transaction completion */
-		if (smbus_wait_until_blk_done() < 0) {
-			return -3;
-		}
-
-		/* Load the next byte */
-		if (i > 3)
-			byte = (data2 >> (i % 4)) & 0x0ff;
-		else
-			byte = (data1 >> (i)) & 0x0ff;
-		outb(byte, SMBUS_IO_BASE + SMBBLKDAT);
-
-		/* Clear the done bit */
-		outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
-		     SMBUS_IO_BASE + SMBHSTSTAT);
-	}
-
-	print_debug("SMBUS Block complete\n");
-	return 0;
-}
-#endif