X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fsouthbridge%2Fintel%2Fi3100%2Fsata.c;fp=src%2Fsouthbridge%2Fintel%2Fi3100%2Fsata.c;h=1925f888ed560d1931f9bb891b112a8530b6b780;hb=ab46c15f61844b62ded575d5710fe2da0cae32d8;hp=af22600f90cf02a23872d223dd85ab395bbc060e;hpb=7363ca35f06f3a3ac398812812b75118aab8c6bf;p=coreboot.git

diff --git a/src/southbridge/intel/i3100/sata.c b/src/southbridge/intel/i3100/sata.c
index af22600f9..1925f888e 100644
--- a/src/southbridge/intel/i3100/sata.c
+++ b/src/southbridge/intel/i3100/sata.c
@@ -81,6 +81,24 @@ static void sata_init(struct device *dev)
 	  pci_write_config8(dev, SATA_PCS + 1, 0x0f);
 
 	}
+
+	/* secret init sequence, required */
+	pci_write_config32(dev, 0x94, 0x00400180);
+	pci_write_config32(dev, 0xa0, 0x18);
+	pci_write_config32(dev, 0xa4, 0x224);
+	pci_write_config32(dev, 0xa0, 0x42);
+	pci_write_config32(dev, 0xa4, 0x22006d);
+	pci_write_config32(dev, 0xa0, 0x84);
+	pci_write_config32(dev, 0xa4, 0x24);
+	pci_write_config32(dev, 0xa0, 0x7a);
+	pci_write_config32(dev, 0xa4, 0x220000);
+	pci_write_config32(dev, 0xa0, 0x9c);
+	pci_write_config32(dev, 0xa4, 0x24);
+	pci_write_config32(dev, 0xa0, 0x90);
+	pci_write_config32(dev, 0xa4, 0x220000);
+	pci_write_config32(dev, 0xa0, 0xa0);
+	pci_write_config32(dev, 0xa4, 0x12492aa);
+
 	printk(BIOS_DEBUG, "SATA Enabled\n");
 }