X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fsouthbridge%2Famd%2Fcs5536%2Fcs5536.c;h=f068006f75bb1dedfd75908f7c98aa298fa5c92c;hb=c02b4fc9db3c3c1e263027382697b566127f66bb;hp=3f947cf17a9f61cab7f195df14d105e580a96df0;hpb=f1cf1f7c3aba660e4a174e966c4ef366d908565c;p=coreboot.git diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c index 3f947cf17..f068006f7 100644 --- a/src/southbridge/amd/cs5536/cs5536.c +++ b/src/southbridge/amd/cs5536/cs5536.c @@ -1,5 +1,5 @@ /* - * This file is part of the LinuxBIOS project. + * This file is part of the coreboot project. * * Copyright (C) 2007 Advanced Micro Devices, Inc. * @@ -26,16 +26,16 @@ #include #include #include +#include #include #include #include +#include #include "chip.h" #include "cs5536.h" -extern void setup_i8259(void); - struct msrinit { - uint32_t msrnum; + u32 msrnum; msr_t msr; }; @@ -61,8 +61,8 @@ struct msrinit CS5536_CLOCK_GATING_TABLE[] = { }; struct acpiinit { - uint16_t ioreg; - uint32_t regdata; + u16 ioreg; + u32 regdata; }; struct acpiinit acpi_init_table[] = { @@ -93,9 +93,9 @@ struct FLASH_DEVICE FlashInitTable[] = { {FLASH_TYPE_NONE, 0, 0}, /* CS3, or Flash Device 3 */ }; -#define FlashInitTableLen (sizeof(FlashInitTable)/sizeof(FlashInitTable[0])) +#define FlashInitTableLen (ARRAY_SIZE(FlashInitTable)) -uint32_t FlashPort[] = { +u32 FlashPort[] = { MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, MDD_LBAR_FLSH2, @@ -111,8 +111,8 @@ uint32_t FlashPort[] = { /* ***************************************************************************/ static void pmChipsetInit(void) { - uint32_t val = 0; - uint16_t port; + u32 val = 0; + u16 port; port = (PMS_IO_BASE + 0x010); val = 0x0E00; /* 1ms */ @@ -155,10 +155,10 @@ static void ChipsetFlashSetup(void) int i; int numEnabled = 0; - printk_debug("ChipsetFlashSetup: Start\n"); + printk(BIOS_DEBUG, "ChipsetFlashSetup: Start\n"); for (i = 0; i < FlashInitTableLen; i++) { if (FlashInitTable[i].fType != FLASH_TYPE_NONE) { - printk_debug("Enable CS%d\n", i); + printk(BIOS_DEBUG, "Enable CS%d\n", i); /* we need to configure the memory/IO mask */ msr = rdmsr(FlashPort[i]); msr.hi = 0; /* start with the "enabled" bit clear */ @@ -171,14 +171,14 @@ static void ChipsetFlashSetup(void) else msr.hi &= ~0x00000004; msr.hi |= FlashInitTable[i].fMask; - printk_debug("MSR(0x%08X, %08X_%08X)\n", FlashPort[i], + printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n", FlashPort[i], msr.hi, msr.lo); wrmsr(FlashPort[i], msr); /* now write-enable the device */ msr = rdmsr(MDD_NORF_CNTRL); msr.lo |= (1 << i); - printk_debug("MSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL, + printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL, msr.hi, msr.lo); wrmsr(MDD_NORF_CNTRL, msr); @@ -187,7 +187,7 @@ static void ChipsetFlashSetup(void) } } - printk_debug("ChipsetFlashSetup: Finish\n"); + printk(BIOS_DEBUG, "ChipsetFlashSetup: Finish\n"); } @@ -247,38 +247,45 @@ static void lpc_init(struct southbridge_amd_cs5536_config *sb) isa_dma_init(); } + +/** + * Depending on settings in the config struct, enable COM1 or COM2 or both. + * + * If the enable is NOT set, the UARTs are explicitly disabled, which is + * required if (e.g.) there is a Super I/O attached that does COM1 or COM2. + * + * @param sb Southbridge config structure. + */ static void uarts_init(struct southbridge_amd_cs5536_config *sb) { msr_t msr; - uint16_t addr; - uint32_t gpio_addr; + u16 addr = 0; + u32 gpio_addr; device_t dev; - + dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, 0); gpio_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1); - gpio_addr &= ~1; /* clear IO bit */ - printk_debug("GPIO_ADDR: %08X\n", gpio_addr); + gpio_addr &= ~1; /* Clear I/O bit */ + printk(BIOS_DEBUG, "GPIO_ADDR: %08X\n", gpio_addr); - /* This could be extended to support IR modes */ + /* This could be extended to support IR modes. */ /* COM1 */ if (sb->com1_enable) { - /* Set the address */ + printk(BIOS_SPEW, "uarts_init: enable COM1\n"); + /* Set the address. */ switch (sb->com1_address) { case 0x3F8: addr = 7; break; - case 0x3E8: addr = 6; break; - case 0x2F8: addr = 5; break; - case 0x2E8: addr = 4; break; @@ -287,42 +294,45 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb) msr.lo |= addr << 16; wrmsr(MDD_LEG_IO, msr); - /* Set the IRQ */ + /* Set the IRQ. */ msr = rdmsr(MDD_IRQM_YHIGH); msr.lo |= sb->com1_irq << 24; wrmsr(MDD_IRQM_YHIGH, msr); /* GPIO8 - UART1_TX */ - /* Set: Output Enable (0x4) */ + /* Set: Output Enable (0x4) */ outl(GPIOL_8_SET, gpio_addr + GPIOL_OUTPUT_ENABLE); /* Set: OUTAUX1 Select (0x10) */ outl(GPIOL_8_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT); - /* GPIO8 - UART1_RX */ + /* GPIO9 - UART1_RX */ /* Set: Input Enable (0x20) */ outl(GPIOL_9_SET, gpio_addr + GPIOL_INPUT_ENABLE); - /* Set: INAUX1 Select (0x34) */ + /* Set: INAUX1 Select (0x34) */ outl(GPIOL_9_SET, gpio_addr + GPIOL_IN_AUX1_SELECT); - /* Set: GPIO 8 + 9 Pull Up (0x18) */ + /* Set: GPIO 8 + 9 Pull Up (0x18) */ outl(GPIOL_8_SET | GPIOL_9_SET, gpio_addr + GPIOL_PULLUP_ENABLE); - /* enable COM1 */ - /* Bit 1 = device enable Bit 4 = allow access to the upper banks */ + /* Enable COM1. + * + * Bit 1 = device enable + * Bit 4 = allow access to the upper banks + */ msr.lo = (1 << 4) | (1 << 1); msr.hi = 0; wrmsr(MDD_UART1_CONF, msr); - } else { - /* Reset and disable COM1 */ + /* Reset and disable COM1. */ + printk(BIOS_SPEW, "uarts_init: disable COM1\n"); msr = rdmsr(MDD_UART1_CONF); - msr.lo = 1; // reset + msr.lo = 1; /* Reset */ wrmsr(MDD_UART1_CONF, msr); - msr.lo = 0; // disabled + msr.lo = 0; /* Disabled */ wrmsr(MDD_UART1_CONF, msr); - /* Disable the IRQ */ + /* Disable the IRQ. */ msr = rdmsr(MDD_LEG_IO); msr.lo &= ~(0xF << 16); wrmsr(MDD_LEG_IO, msr); @@ -330,19 +340,17 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb) /* COM2 */ if (sb->com2_enable) { + printk(BIOS_SPEW, "uarts_init: enable COM2\n"); switch (sb->com2_address) { case 0x3F8: addr = 7; break; - case 0x3E8: addr = 6; break; - case 0x2F8: addr = 5; break; - case 0x2E8: addr = 4; break; @@ -350,49 +358,59 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb) msr = rdmsr(MDD_LEG_IO); msr.lo |= addr << 20; wrmsr(MDD_LEG_IO, msr); + printk(BIOS_SPEW, "uarts_init: wrote COM2 address 0x%x\n", sb->com2_address); - /* Set the IRQ */ + /* Set the IRQ. */ msr = rdmsr(MDD_IRQM_YHIGH); msr.lo |= sb->com2_irq << 28; wrmsr(MDD_IRQM_YHIGH, msr); + printk(BIOS_SPEW, "uarts_init: set COM2 irq\n"); - /* GPIO4 - UART2_RX */ - /* Set: Output Enable (0x4) */ - outl(GPIOL_4_SET, gpio_addr + GPIOL_OUTPUT_ENABLE); - /* Set: OUTAUX1 Select (0x10) */ - outl(GPIOL_4_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT); - - /* GPIO3 - UART2_TX */ + /* GPIO3 - UART2_RX */ /* Set: Input Enable (0x20) */ outl(GPIOL_3_SET, gpio_addr + GPIOL_INPUT_ENABLE); /* Set: INAUX1 Select (0x34) */ outl(GPIOL_3_SET, gpio_addr + GPIOL_IN_AUX1_SELECT); - /* Set: GPIO 3 and 4 Pull Up (0x18) */ + /* GPIO4 - UART2_TX */ + /* Set: Output Enable (0x4) */ + outl(GPIOL_4_SET, gpio_addr + GPIOL_OUTPUT_ENABLE); + printk(BIOS_SPEW, "uarts_init: set output enable\n"); + /* Set: OUTAUX1 Select (0x10) */ + outl(GPIOL_4_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT); + printk(BIOS_SPEW, "uarts_init: set OUTAUX1\n"); + + /* Set: GPIO 3 + 4 Pull Up (0x18) */ outl(GPIOL_3_SET | GPIOL_4_SET, gpio_addr + GPIOL_PULLUP_ENABLE); + printk(BIOS_SPEW, "uarts_init: set pullup COM2\n"); - /* enable COM2 */ - /* Bit 1 = device enable Bit 4 = allow access to the upper banks */ + /* Enable COM2. + * + * Bit 1 = device enable + * Bit 4 = allow access to the upper banks + */ msr.lo = (1 << 4) | (1 << 1); msr.hi = 0; wrmsr(MDD_UART2_CONF, msr); - + printk(BIOS_SPEW, "uarts_init: COM2 enabled\n"); } else { - /* Reset and disable COM2 */ + printk(BIOS_SPEW, "uarts_init: disable COM2\n"); + /* Reset and disable COM2. */ msr = rdmsr(MDD_UART2_CONF); - msr.lo = 1; // reset + msr.lo = 1; /* Reset */ wrmsr(MDD_UART2_CONF, msr); - msr.lo = 0; // disabled + msr.lo = 0; /* Disabled */ wrmsr(MDD_UART2_CONF, msr); - /* Disable the IRQ */ + /* Disable the IRQ. */ msr = rdmsr(MDD_LEG_IO); msr.lo &= ~(0xF << 20); wrmsr(MDD_LEG_IO, msr); } } + #define HCCPARAMS 0x08 #define IPREG04 0xA0 #define USB_HCCPW_SET (1 << 1) @@ -409,7 +427,7 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb) static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) { - uint32_t *bar; + u32 bar; msr_t msr; device_t dev; @@ -425,32 +443,33 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) /* write to clear diag register */ wrmsr(USB2_SB_GLD_MSR_DIAG, rdmsr(USB2_SB_GLD_MSR_DIAG)); - bar = (uint32_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0); + bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); /* Make HCCPARAMS writeable */ - *(bar + IPREG04) |= USB_HCCPW_SET; + write32(bar + IPREG04, read32(bar + IPREG04) | USB_HCCPW_SET); /* ; EECP=50h, IST=01h, ASPC=1 */ - *(bar + HCCPARAMS) = 0x00005012; + write32(bar + HCCPARAMS, 0x00005012); } dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OTG, 0); if (dev) { - bar = (uint32_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0); + bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); - *(bar + UOCMUX) &= PUEN_SET; + write32(bar + UOCMUX, read32(bar + UOCMUX) & PUEN_SET); /* Host or Device? */ if (sb->enable_USBP4_device) { - *(bar + UOCMUX) |= PMUX_DEVICE; + write32(bar + UOCMUX, read32(bar + UOCMUX) | PMUX_DEVICE); } else { - *(bar + UOCMUX) |= PMUX_HOST; + write32(bar + UOCMUX, read32(bar + UOCMUX) | PMUX_HOST); } /* Overcurrent configuration */ if (sb->enable_USBP4_overcurrent) { - *(bar + UOCCAP) |= sb->enable_USBP4_overcurrent; + write32(bar + UOCCAP, read32(bar + UOCCAP) + | sb->enable_USBP4_overcurrent); } } @@ -464,19 +483,18 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_UDC, 0); if (dev) { - bar = (uint32_t *) pci_read_config32(dev, - PCI_BASE_ADDRESS_0); - *(bar + UDCDEVCTL) |= UDC_SD_SET; + bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); + write32(bar + UDCDEVCTL, + read32(bar + UDCDEVCTL) | UDC_SD_SET); } dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OTG, 0); if (dev) { - bar = (uint32_t *) pci_read_config32(dev, - PCI_BASE_ADDRESS_0); - *(bar + UOCCTL) |= PADEN_SET; - *(bar + UOCCAP) |= APU_SET; + bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); + write32(bar + UOCCTL, read32(bar + UOCCTL) | PADEN_SET); + write32(bar + UOCCAP, read32(bar + UOCCAP) | APU_SET); } } @@ -504,14 +522,14 @@ void chipsetinit(void) { device_t dev; msr_t msr; - uint32_t msrnum; + u32 msrnum; struct southbridge_amd_cs5536_config *sb = (struct southbridge_amd_cs5536_config *)dev->chip_info; struct msrinit *csi; post_code(P80_CHIPSET_INIT); - /* we hope NEVER to be in linuxbios when S3 resumes + /* we hope NEVER to be in coreboot when S3 resumes if (! IsS3Resume()) */ { struct acpiinit *aci = acpi_init_table; @@ -548,7 +566,7 @@ void chipsetinit(void) } /* Flash BAR size Setup */ - printk_err("%sDoing ChipsetFlashSetup()\n", + printk(BIOS_ERR, "%sDoing ChipsetFlashSetup()\n", sb->enable_ide_nand_flash == 1 ? "" : "Not "); if (sb->enable_ide_nand_flash == 1) ChipsetFlashSetup(); @@ -576,7 +594,7 @@ static void southbridge_init(struct device *dev) * unsigned short gpiobase = MDD_GPIO; */ - printk_err("cs5536: %s\n", __FUNCTION__); + printk(BIOS_ERR, "cs5536: %s\n", __func__); setup_i8259(); lpc_init(sb); uarts_init(sb); @@ -588,7 +606,7 @@ static void southbridge_init(struct device *dev) (sb->enable_gpio_int_route >> 16)); } - printk_err("cs5536: %s: enable_ide_nand_flash is %d\n", __FUNCTION__, + printk(BIOS_ERR, "cs5536: %s: enable_ide_nand_flash is %d\n", __func__, sb->enable_ide_nand_flash); if (sb->enable_ide_nand_flash == 1) { enable_ide_nand_flash_header(); @@ -598,28 +616,47 @@ static void southbridge_init(struct device *dev) /* disable unwanted virtual PCI devices */ for (i = 0; (i < MAX_UNWANTED_VPCI) && (0 != sb->unwanted_vpci[i]); i++) { - printk_debug("Disabling VPCI device: 0x%08X\n", + printk(BIOS_DEBUG, "Disabling VPCI device: 0x%08X\n", sb->unwanted_vpci[i]); outl(sb->unwanted_vpci[i] + 0x7C, 0xCF8); outl(0xDEADBEEF, 0xCFC); } } +static void cs5536_read_resources(device_t dev) +{ + struct resource *res; + + pci_dev_read_resources(dev); + + res = new_resource(dev, 1); + res->base = 0x0UL; + res->size = 0x400UL; + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + static void southbridge_enable(struct device *dev) { - printk_err("cs5536: %s: dev is %p\n", __FUNCTION__, dev); + printk(BIOS_ERR, "cs5536: %s: dev is %p\n", __func__, dev); } static void cs5536_pci_dev_enable_resources(device_t dev) { - printk_err("cs5536: %s()\n", __FUNCTION__); + printk(BIOS_ERR, "cs5536: %s()\n", __func__); pci_dev_enable_resources(dev); enable_childrens_resources(dev); } static struct device_operations southbridge_ops = { - .read_resources = pci_dev_read_resources, + .read_resources = cs5536_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = cs5536_pci_dev_enable_resources, .init = southbridge_init,