X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fsouthbridge%2Famd%2Famd8111%2Famd8111_enable_rom.c;h=3e73112b4799195e2bd98de3a4d6a3f90a2743a9;hb=1f7d3c5672ec90f8d71907b1a07c8a87fa461047;hp=b8cc5b1a84ae30c3f4912575b0fb440732807c43;hpb=df323fcefd6020f8f418a13d65a075d282eed3de;p=coreboot.git

diff --git a/src/southbridge/amd/amd8111/amd8111_enable_rom.c b/src/southbridge/amd/amd8111/amd8111_enable_rom.c
index b8cc5b1a8..3e73112b4 100644
--- a/src/southbridge/amd/amd8111/amd8111_enable_rom.c
+++ b/src/southbridge/amd/amd8111/amd8111_enable_rom.c
@@ -1,15 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Linux Networx
+ * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
 
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_ids.h>
+
+/* Enable 5MB ROM access at 0xFFB00000 - 0xFFFFFFFF. */
 static void amd8111_enable_rom(void)
 {
-	unsigned char byte;
+	u8 byte;
 	device_t dev;
 
-	/* Enable 5MB rom access at 0xFFB00000 - 0xFFFFFFFF */
-	/* Locate the amd8111 */
-	dev = pci_io_locate_device(PCI_ID(0x1022, 0x7468), 0);
+	dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_AMD,
+					  PCI_DEVICE_ID_AMD_8111_ISA), 0);
+
+	/* Note: The 0xFFFF0000 - 0xFFFFFFFF range is always enabled. */
 
-	/* Set the 5MB enable bits */
+	/* Set the 5MB enable bits. */
 	byte = pci_io_read_config8(dev, 0x43);
-	byte |= 0xC0;
+	byte |= (1 << 7); /* Enable 0xFFC00000-0xFFFFFFFF (4MB). */
+	byte |= (1 << 6); /* Enable 0xFFB00000-0xFFBFFFFF (1MB). */
 	pci_io_write_config8(dev, 0x43, byte);
 }