X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fshadow.c;h=169decf7508184d0f796cb0c7d89fd11ffb5505e;hb=6e4583c4a4a72fcb5914e59c8f1c534aceafbd44;hp=887851d1b96c43fd377c803db7e9d5b432aecf01;hpb=276d4a916517fc8ebf05b05f0226e80787f90309;p=seabios.git diff --git a/src/shadow.c b/src/shadow.c index 887851d..169decf 100644 --- a/src/shadow.c +++ b/src/shadow.c @@ -1,85 +1,163 @@ // Support for enabling/disabling BIOS ram shadowing. // -// Copyright (C) 2008 Kevin O'Connor +// Copyright (C) 2008-2010 Kevin O'Connor // Copyright (C) 2006 Fabrice Bellard // -// This file may be distributed under the terms of the GNU GPLv3 license. +// This file may be distributed under the terms of the GNU LGPLv3 license. #include "util.h" // memcpy #include "pci.h" // pci_config_writeb +#include "config.h" // CONFIG_* +#include "pci_ids.h" // PCI_VENDOR_ID_INTEL +#include "xen.h" // usingXen -// Test if 'addr' is in the range from 'start'..'start+size' -#define IN_RANGE(addr, start, size) ({ \ - u32 __addr = (addr); \ - u32 __start = (start); \ - u32 __size = (size); \ - (__addr - __start < __size); \ - }) +// On the emulators, the bios at 0xf0000 is also at 0xffff0000 +#define BIOS_SRC_OFFSET 0xfff00000 + +#define I440FX_PAM0 0x59 // Enable shadowing and copy bios. static void -copy_bios(PCIDevice d) +__make_bios_writable_intel(u16 bdf, u32 pam0) +{ + // Make ram from 0xc0000-0xf0000 writable + int clear = 0; + int i; + for (i=0; i<6; i++) { + u32 pam = pam0 + 1 + i; + int reg = pci_config_readb(bdf, pam); + if (CONFIG_OPTIONROMS_DEPLOYED && (reg & 0x11) != 0x11) { + // Need to copy optionroms to work around qemu implementation + void *mem = (void*)(BUILD_ROM_START + i * 32*1024); + memcpy((void*)BUILD_BIOS_TMP_ADDR, mem, 32*1024); + pci_config_writeb(bdf, pam, 0x33); + memcpy(mem, (void*)BUILD_BIOS_TMP_ADDR, 32*1024); + clear = 1; + } else { + pci_config_writeb(bdf, pam, 0x33); + } + } + if (clear) + memset((void*)BUILD_BIOS_TMP_ADDR, 0, 32*1024); + + // Make ram from 0xf0000-0x100000 writable + int reg = pci_config_readb(bdf, pam0); + pci_config_writeb(bdf, pam0, 0x30); + if (reg & 0x10) + // Ram already present. + return; + + // Copy bios. + extern u8 code32flat_start[], code32flat_end[]; + memcpy(code32flat_start, code32flat_start + BIOS_SRC_OFFSET + , code32flat_end - code32flat_start); +} + +static void +make_bios_writable_intel(u16 bdf, u32 pam0) +{ + int reg = pci_config_readb(bdf, pam0); + if (!(reg & 0x10)) { + // QEMU doesn't fully implement the piix shadow capabilities - + // if ram isn't backing the bios segment when shadowing is + // disabled, the code itself wont be in memory. So, run the + // code from the high-memory flash location. + u32 pos = (u32)__make_bios_writable_intel + BIOS_SRC_OFFSET; + void (*func)(u16 bdf, u32 pam0) = (void*)pos; + func(bdf, pam0); + return; + } + // Ram already present - just enable writes + __make_bios_writable_intel(bdf, pam0); +} + +static void +make_bios_readonly_intel(u16 bdf, u32 pam0) +{ + // Flush any pending writes before locking memory. + wbinvd(); + + // Write protect roms from 0xc0000-0xf0000 + int i; + for (i=0; i<6; i++) { + u32 mem = BUILD_ROM_START + i * 32*1024; + u32 pam = pam0 + 1 + i; + if (RomEnd <= mem + 16*1024) { + if (RomEnd > mem) + pci_config_writeb(bdf, pam, 0x31); + break; + } + pci_config_writeb(bdf, pam, 0x11); + } + + // Write protect 0xf0000-0x100000 + pci_config_writeb(bdf, pam0, 0x10); +} + +static void i440fx_bios_make_writable(u16 bdf, void *arg) +{ + make_bios_writable_intel(bdf, I440FX_PAM0); +} + +static void i440fx_bios_make_readonly(u16 bdf, void *arg) { - int v = pci_config_readb(d, 0x59); - v |= 0x30; - pci_config_writeb(d, 0x59, v); - memcpy((void *)0x000f0000, (void *)BUILD_BIOS_TMP_ADDR, 0x10000); + make_bios_readonly_intel(bdf, I440FX_PAM0); } -// Make the BIOS code segment area (0xf0000) writable. +static const struct pci_device_id dram_controller_make_writable_tbl[] = { + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, + i440fx_bios_make_writable), + PCI_DEVICE_END +}; + +static const struct pci_device_id dram_controller_make_readonly_tbl[] = { + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, + i440fx_bios_make_readonly), + PCI_DEVICE_END +}; + +// Make the 0xc0000-0x100000 area read/writable. void -make_bios_writable() +make_bios_writable(void) { - if (CONFIG_COREBOOT) + if (CONFIG_COREBOOT || usingXen()) return; dprintf(3, "enabling shadow ram\n"); + // at this point, statically allocated variables can't be written. + // so stack should be used. + // Locate chip controlling ram shadowing. - PCIDevice d; - int ret = pci_find_device(0x8086, 0x1237, 0, &d); - if (ret) { + int bdf = pci_find_init_device(dram_controller_make_writable_tbl, NULL); + if (bdf < 0) { dprintf(1, "Unable to unlock ram - bridge not found\n"); - return; - } - - // Copy the bios to a temporary area. - memcpy((void *)BUILD_BIOS_TMP_ADDR, (void *)0x000f0000, 0x10000); - - // Enable shadowing and copy bios. - if (IN_RANGE((u32)copy_bios, 0xf0000, 0x10000)) { - // Jump to shadow enable function - use the copy in the - // temporary storage area so that memory does not change under - // the executing code. - u32 pos = (u32)copy_bios - 0xf0000 + BUILD_BIOS_TMP_ADDR; - void (*func)(PCIDevice) = (void*)pos; - func(d); - } else { - copy_bios(d); } - - // Clear the temporary area. - memset((void *)BUILD_BIOS_TMP_ADDR, 0, 0x10000); } // Make the BIOS code segment area (0xf0000) read-only. void -make_bios_readonly() +make_bios_readonly(void) { - if (CONFIG_COREBOOT) + if (CONFIG_COREBOOT || usingXen()) return; dprintf(3, "locking shadow ram\n"); - - PCIDevice d; - int ret = pci_find_device(0x8086, 0x1237, 0, &d); - if (ret) { + int bdf = pci_find_init_device(dram_controller_make_readonly_tbl, NULL); + if (bdf < 0) { dprintf(1, "Unable to lock ram - bridge not found\n"); - return; } +} - wbinvd(); - int v = pci_config_readb(d, 0x59); - v = (v & 0x0f) | (0x10); - pci_config_writeb(d, 0x59, v); +void +qemu_prep_reset(void) +{ + if (CONFIG_COREBOOT) + return; + // QEMU doesn't map 0xc0000-0xfffff back to the original rom on a + // reset, so do that manually before invoking a hard reset. + make_bios_writable(); + extern u8 code32flat_start[], code32flat_end[]; + memcpy(code32flat_start, code32flat_start + BIOS_SRC_OFFSET + , code32flat_end - code32flat_start); }