X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fpciinit.c;h=9314698b4515ec5bc9f4867640472a2015d485ec;hb=82b39b286e58b4066e75868dcd96620416954412;hp=6d35eeacb333facc31496ce1073c3216789eb353;hpb=e79163695a2518ad2e87cb75b80c9e7deb2972b1;p=seabios.git diff --git a/src/pciinit.c b/src/pciinit.c index 6d35eea..9314698 100644 --- a/src/pciinit.c +++ b/src/pciinit.c @@ -3,48 +3,194 @@ // Copyright (C) 2008 Kevin O'Connor // Copyright (C) 2006 Fabrice Bellard // -// This file may be distributed under the terms of the GNU GPLv3 license. +// This file may be distributed under the terms of the GNU LGPLv3 license. #include "util.h" // dprintf #include "pci.h" // pci_config_readl #include "biosvar.h" // GET_EBDA #include "pci_ids.h" // PCI_VENDOR_ID_INTEL #include "pci_regs.h" // PCI_COMMAND +#include "xen.h" // usingXen -#define PCI_ROM_SLOT 6 -#define PCI_NUM_REGIONS 7 +#define PCI_IO_INDEX_SHIFT 2 +#define PCI_MEM_INDEX_SHIFT 12 + +#define PCI_BRIDGE_IO_MIN 0x1000 +#define PCI_BRIDGE_MEM_MIN 0x100000 + +static struct pci_region pci_bios_io_region; +static struct pci_region pci_bios_mem_region; +static struct pci_region pci_bios_prefmem_region; + +enum pci_region_type { + PCI_REGION_TYPE_IO, + PCI_REGION_TYPE_MEM, + PCI_REGION_TYPE_PREFMEM, + PCI_REGION_TYPE_COUNT, +}; + +static const char *region_type_name[] = { + [ PCI_REGION_TYPE_IO ] = "io", + [ PCI_REGION_TYPE_MEM ] = "mem", + [ PCI_REGION_TYPE_PREFMEM ] = "prefmem", +}; + +static struct pci_bus { + struct { + /* pci region stats */ + u32 count[32 - PCI_MEM_INDEX_SHIFT]; + u32 sum, max; + /* seconday bus region sizes */ + u32 size; + /* pci region assignments */ + u32 bases[32 - PCI_MEM_INDEX_SHIFT]; + u32 base; + } r[PCI_REGION_TYPE_COUNT]; +} *busses; +static int busses_count; + +static void pci_bios_init_device_in_bus(int bus); +static void pci_bios_check_device_in_bus(int bus); +static void pci_bios_init_bus_bases(struct pci_bus *bus); +static void pci_bios_map_device_in_bus(int bus); + +static int pci_size_to_index(u32 size, enum pci_region_type type) +{ + int index = __fls(size); + int shift = (type == PCI_REGION_TYPE_IO) ? + PCI_IO_INDEX_SHIFT : PCI_MEM_INDEX_SHIFT; + + if (index < shift) + index = shift; + index -= shift; + return index; +} + +static u32 pci_index_to_size(int index, enum pci_region_type type) +{ + int shift = (type == PCI_REGION_TYPE_IO) ? + PCI_IO_INDEX_SHIFT : PCI_MEM_INDEX_SHIFT; + + return 0x1 << (index + shift); +} + +static enum pci_region_type pci_addr_to_type(u32 addr) +{ + if (addr & PCI_BASE_ADDRESS_SPACE_IO) + return PCI_REGION_TYPE_IO; + if (addr & PCI_BASE_ADDRESS_MEM_PREFETCH) + return PCI_REGION_TYPE_PREFMEM; + return PCI_REGION_TYPE_MEM; +} + +static u32 pci_size_roundup(u32 size) +{ + int index = __fls(size-1)+1; + return 0x1 << index; +} -static u32 pci_bios_io_addr; -static u32 pci_bios_mem_addr; -static u32 pci_bios_bigmem_addr; /* host irqs corresponding to PCI irqs A-D */ -static u8 pci_irqs[4] = { 11, 9, 11, 9 }; +const u8 pci_irqs[4] = { + 10, 10, 11, 11 +}; + +static u32 pci_bar(u16 bdf, int region_num) +{ + if (region_num != PCI_ROM_SLOT) { + return PCI_BASE_ADDRESS_0 + region_num * 4; + } + +#define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 + u8 type = pci_config_readb(bdf, PCI_HEADER_TYPE); + type &= ~PCI_HEADER_TYPE_MULTI_FUNCTION; + return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; +} static void pci_set_io_region_addr(u16 bdf, int region_num, u32 addr) { - u16 cmd; - u32 ofs, old_addr; + u32 ofs; + + ofs = pci_bar(bdf, region_num); + + pci_config_writel(bdf, ofs, addr); + dprintf(1, "region %d: 0x%08x\n", region_num, addr); +} + +/* + * return value + * 0: 32bit BAR + * non 0: 64bit BAR + */ +static int pci_bios_allocate_region(u16 bdf, int region_num) +{ + struct pci_region *r; + u32 ofs = pci_bar(bdf, region_num); + u32 old = pci_config_readl(bdf, ofs); + u32 mask; if (region_num == PCI_ROM_SLOT) { - ofs = PCI_ROM_ADDRESS; + mask = PCI_ROM_ADDRESS_MASK; + pci_config_writel(bdf, ofs, mask); } else { - ofs = PCI_BASE_ADDRESS_0 + region_num * 4; + if (old & PCI_BASE_ADDRESS_SPACE_IO) + mask = PCI_BASE_ADDRESS_IO_MASK; + else + mask = PCI_BASE_ADDRESS_MEM_MASK; + pci_config_writel(bdf, ofs, ~0); } + u32 val = pci_config_readl(bdf, ofs); + pci_config_writel(bdf, ofs, old); - old_addr = pci_config_readl(bdf, ofs); + u32 size = (~(val & mask)) + 1; + if (val != 0) { + const char *type; + const char *msg; + if (val & PCI_BASE_ADDRESS_SPACE_IO) { + r = &pci_bios_io_region; + type = "io"; + msg = ""; + } else if ((val & PCI_BASE_ADDRESS_MEM_PREFETCH) && + /* keep behaviour on bus = 0 */ + pci_bdf_to_bus(bdf) != 0 && + /* If pci_bios_prefmem_addr == 0, keep old behaviour */ + pci_region_addr(&pci_bios_prefmem_region) != 0) { + r = &pci_bios_prefmem_region; + type = "prefmem"; + msg = "decrease BUILD_PCIMEM_SIZE and recompile. size %x"; + } else { + r = &pci_bios_mem_region; + type = "mem"; + msg = "increase BUILD_PCIMEM_SIZE and recompile."; + } + u32 addr = pci_region_alloc(r, size); + if (addr > 0) { + pci_set_io_region_addr(bdf, region_num, addr); + } else { + size = 0; + dprintf(1, + "%s region of (bdf 0x%x bar %d) can't be mapped. " + "%s size %x\n", + type, bdf, region_num, msg, pci_region_size(r)); + } + } - pci_config_writel(bdf, ofs, addr); - dprintf(1, "region %d: 0x%08x\n", region_num, addr); + int is_64bit = !(val & PCI_BASE_ADDRESS_SPACE_IO) && + (val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64; + if (is_64bit && size > 0) { + pci_config_writel(bdf, ofs + 4, 0); + } + return is_64bit; +} - /* enable memory mappings */ - cmd = pci_config_readw(bdf, PCI_COMMAND); - if (region_num == PCI_ROM_SLOT) - cmd |= PCI_COMMAND_MEMORY; - else if (old_addr & PCI_BASE_ADDRESS_SPACE_IO) - cmd |= PCI_COMMAND_IO; - else - cmd |= PCI_COMMAND_MEMORY; - pci_config_writew(bdf, PCI_COMMAND, cmd); +static void pci_bios_allocate_regions(struct pci_device *pci, void *arg) +{ + int i; + for (i = 0; i < PCI_NUM_REGIONS; i++) { + int is_64bit = pci_bios_allocate_region(pci->bdf, i); + if (is_64bit){ + i++; + } + } } /* return the global irq number corresponding to a given device irq @@ -56,114 +202,221 @@ static int pci_slot_get_pirq(u16 bdf, int irq_num) return (irq_num + slot_addend) & 3; } -static void pci_bios_init_bridges(u16 bdf) +/* PIIX3/PIIX4 PCI to ISA bridge */ +static void piix_isa_bridge_init(struct pci_device *pci, void *arg) { - u16 vendor_id = pci_config_readw(bdf, PCI_VENDOR_ID); - u16 device_id = pci_config_readw(bdf, PCI_DEVICE_ID); + int i, irq; + u8 elcr[2]; - if (vendor_id == PCI_VENDOR_ID_INTEL - && (device_id == PCI_DEVICE_ID_INTEL_82371SB_0 - || device_id == PCI_DEVICE_ID_INTEL_82371AB_0)) { - int i, irq; - u8 elcr[2]; + elcr[0] = 0x00; + elcr[1] = 0x00; + for (i = 0; i < 4; i++) { + irq = pci_irqs[i]; + /* set to trigger level */ + elcr[irq >> 3] |= (1 << (irq & 7)); + /* activate irq remapping in PIIX */ + pci_config_writeb(pci->bdf, 0x60 + i, irq); + } + outb(elcr[0], 0x4d0); + outb(elcr[1], 0x4d1); + dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", elcr[0], elcr[1]); +} - /* PIIX3/PIIX4 PCI to ISA bridge */ +static const struct pci_device_id pci_isa_bridge_tbl[] = { + /* PIIX3/PIIX4 PCI to ISA bridge */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, + piix_isa_bridge_init), + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, + piix_isa_bridge_init), - elcr[0] = 0x00; - elcr[1] = 0x00; - for(i = 0; i < 4; i++) { - irq = pci_irqs[i]; - /* set to trigger level */ - elcr[irq >> 3] |= (1 << (irq & 7)); - /* activate irq remapping in PIIX */ - pci_config_writeb(bdf, 0x60 + i, irq); - } - outb(elcr[0], 0x4d0); - outb(elcr[1], 0x4d1); - dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", - elcr[0], elcr[1]); + PCI_DEVICE_END +}; + +#define PCI_IO_ALIGN 4096 +#define PCI_IO_SHIFT 8 +#define PCI_MEMORY_ALIGN (1UL << 20) +#define PCI_MEMORY_SHIFT 16 +#define PCI_PREF_MEMORY_ALIGN (1UL << 20) +#define PCI_PREF_MEMORY_SHIFT 16 + +static void pci_bios_init_device_bridge(struct pci_device *pci, void *arg) +{ + u16 bdf = pci->bdf; + pci_bios_allocate_region(bdf, 0); + pci_bios_allocate_region(bdf, 1); + pci_bios_allocate_region(bdf, PCI_ROM_SLOT); + + u32 io_old = pci_region_addr(&pci_bios_io_region); + u32 mem_old = pci_region_addr(&pci_bios_mem_region); + u32 prefmem_old = pci_region_addr(&pci_bios_prefmem_region); + + /* IO BASE is assumed to be 16 bit */ + if (pci_region_align(&pci_bios_io_region, PCI_IO_ALIGN) == 0) { + pci_region_disable(&pci_bios_io_region); + } + if (pci_region_align(&pci_bios_mem_region, PCI_MEMORY_ALIGN) == 0) { + pci_region_disable(&pci_bios_mem_region); + } + if (pci_region_align(&pci_bios_prefmem_region, + PCI_PREF_MEMORY_ALIGN) == 0) { + pci_region_disable(&pci_bios_prefmem_region); + } + + u32 io_base = pci_region_addr(&pci_bios_io_region); + u32 mem_base = pci_region_addr(&pci_bios_mem_region); + u32 prefmem_base = pci_region_addr(&pci_bios_prefmem_region); + + u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS); + if (secbus > 0) { + pci_bios_init_device_in_bus(secbus); + } + + u32 io_end = pci_region_align(&pci_bios_io_region, PCI_IO_ALIGN); + if (io_end == 0) { + pci_region_revert(&pci_bios_io_region, io_old); + io_base = 0xffff; + io_end = 1; + } + pci_config_writeb(bdf, PCI_IO_BASE, io_base >> PCI_IO_SHIFT); + pci_config_writew(bdf, PCI_IO_BASE_UPPER16, 0); + pci_config_writeb(bdf, PCI_IO_LIMIT, (io_end - 1) >> PCI_IO_SHIFT); + pci_config_writew(bdf, PCI_IO_LIMIT_UPPER16, 0); + + u32 mem_end = pci_region_align(&pci_bios_mem_region, PCI_MEMORY_ALIGN); + if (mem_end == 0) { + pci_region_revert(&pci_bios_mem_region, mem_old); + mem_base = 0xffffffff; + mem_end = 1; + } + pci_config_writew(bdf, PCI_MEMORY_BASE, mem_base >> PCI_MEMORY_SHIFT); + pci_config_writew(bdf, PCI_MEMORY_LIMIT, (mem_end -1) >> PCI_MEMORY_SHIFT); + + u32 prefmem_end = pci_region_align(&pci_bios_prefmem_region, + PCI_PREF_MEMORY_ALIGN); + if (prefmem_end == 0) { + pci_region_revert(&pci_bios_prefmem_region, prefmem_old); + prefmem_base = 0xffffffff; + prefmem_end = 1; + } + pci_config_writew(bdf, PCI_PREF_MEMORY_BASE, + prefmem_base >> PCI_PREF_MEMORY_SHIFT); + pci_config_writew(bdf, PCI_PREF_MEMORY_LIMIT, + (prefmem_end - 1) >> PCI_PREF_MEMORY_SHIFT); + pci_config_writel(bdf, PCI_PREF_BASE_UPPER32, 0); + pci_config_writel(bdf, PCI_PREF_LIMIT_UPPER32, 0); + + dprintf(1, "PCI: br io = [0x%x, 0x%x)\n", io_base, io_end); + dprintf(1, "PCI: br mem = [0x%x, 0x%x)\n", mem_base, mem_end); + dprintf(1, "PCI: br pref = [0x%x, 0x%x)\n", prefmem_base, prefmem_end); + + u16 cmd = pci_config_readw(bdf, PCI_COMMAND); + cmd &= ~PCI_COMMAND_IO; + if (io_end > io_base) { + cmd |= PCI_COMMAND_IO; } + cmd &= ~PCI_COMMAND_MEMORY; + if (mem_end > mem_base || prefmem_end > prefmem_base) { + cmd |= PCI_COMMAND_MEMORY; + } + cmd |= PCI_COMMAND_MASTER; + pci_config_writew(bdf, PCI_COMMAND, cmd); + + pci_config_maskw(bdf, PCI_BRIDGE_CONTROL, 0, PCI_BRIDGE_CTL_SERR); +} + +static void storage_ide_init(struct pci_device *pci, void *arg) +{ + u16 bdf = pci->bdf; + /* IDE: we map it as in ISA mode */ + pci_set_io_region_addr(bdf, 0, PORT_ATA1_CMD_BASE); + pci_set_io_region_addr(bdf, 1, PORT_ATA1_CTRL_BASE); + pci_set_io_region_addr(bdf, 2, PORT_ATA2_CMD_BASE); + pci_set_io_region_addr(bdf, 3, PORT_ATA2_CTRL_BASE); +} + +/* PIIX3/PIIX4 IDE */ +static void piix_ide_init(struct pci_device *pci, void *arg) +{ + u16 bdf = pci->bdf; + pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0 + pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1 + pci_bios_allocate_regions(pci, NULL); +} + +static void pic_ibm_init(struct pci_device *pci, void *arg) +{ + /* PIC, IBM, MPIC & MPIC2 */ + pci_set_io_region_addr(pci->bdf, 0, 0x80800000 + 0x00040000); +} + +static void apple_macio_init(struct pci_device *pci, void *arg) +{ + /* macio bridge */ + pci_set_io_region_addr(pci->bdf, 0, 0x80800000); +} + +static const struct pci_device_id pci_class_tbl[] = { + /* STORAGE IDE */ + PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1, + PCI_CLASS_STORAGE_IDE, piix_ide_init), + PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB, + PCI_CLASS_STORAGE_IDE, piix_ide_init), + PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, + storage_ide_init), + + /* PIC, IBM, MIPC & MPIC2 */ + PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0x0046, PCI_CLASS_SYSTEM_PIC, + pic_ibm_init), + PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0xFFFF, PCI_CLASS_SYSTEM_PIC, + pic_ibm_init), + + /* 0xff00 */ + PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0017, 0xff00, apple_macio_init), + PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0022, 0xff00, apple_macio_init), + + /* PCI bridge */ + PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI, + pci_bios_init_device_bridge), + + /* default */ + PCI_DEVICE(PCI_ANY_ID, PCI_ANY_ID, pci_bios_allocate_regions), + + PCI_DEVICE_END, +}; + +/* PIIX4 Power Management device (for ACPI) */ +static void piix4_pm_init(struct pci_device *pci, void *arg) +{ + u16 bdf = pci->bdf; + // acpi sci is hardwired to 9 + pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9); + + pci_config_writel(bdf, 0x40, PORT_ACPI_PM_BASE | 1); + pci_config_writeb(bdf, 0x80, 0x01); /* enable PM io space */ + pci_config_writel(bdf, 0x90, PORT_SMB_BASE | 1); + pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */ } -static void pci_bios_init_device(u16 bdf) +static const struct pci_device_id pci_device_tbl[] = { + /* PIIX4 Power Management device (for ACPI) */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, + piix4_pm_init), + + PCI_DEVICE_END, +}; + +static void pci_bios_init_device(struct pci_device *pci) { - int class; - u32 *paddr; - int i, pin, pic_irq, vendor_id, device_id; + u16 bdf = pci->bdf; + int pin, pic_irq; - class = pci_config_readw(bdf, PCI_CLASS_DEVICE); - vendor_id = pci_config_readw(bdf, PCI_VENDOR_ID); - device_id = pci_config_readw(bdf, PCI_DEVICE_ID); dprintf(1, "PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n" - , pci_bdf_to_bus(bdf), pci_bdf_to_devfn(bdf), vendor_id, device_id); - switch(class) { - case PCI_CLASS_STORAGE_IDE: - if (vendor_id == PCI_VENDOR_ID_INTEL - && (device_id == PCI_DEVICE_ID_INTEL_82371SB_1 - || device_id == PCI_DEVICE_ID_INTEL_82371AB)) { - /* PIIX3/PIIX4 IDE */ - pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0 - pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1 - goto default_map; - } else { - /* IDE: we map it as in ISA mode */ - pci_set_io_region_addr(bdf, 0, 0x1f0); - pci_set_io_region_addr(bdf, 1, 0x3f4); - pci_set_io_region_addr(bdf, 2, 0x170); - pci_set_io_region_addr(bdf, 3, 0x374); - } - break; - case PCI_CLASS_DISPLAY_VGA: - if (vendor_id != 0x1234) - goto default_map; - /* VGA: map frame buffer to default Bochs VBE address */ - pci_set_io_region_addr(bdf, 0, 0xE0000000); - break; - case PCI_CLASS_SYSTEM_PIC: - /* PIC */ - if (vendor_id == PCI_VENDOR_ID_IBM) { - /* IBM */ - if (device_id == 0x0046 || device_id == 0xFFFF) { - /* MPIC & MPIC2 */ - pci_set_io_region_addr(bdf, 0, 0x80800000 + 0x00040000); - } - } - break; - case 0xff00: - if (vendor_id == PCI_VENDOR_ID_APPLE && - (device_id == 0x0017 || device_id == 0x0022)) { - /* macio bridge */ - pci_set_io_region_addr(bdf, 0, 0x80800000); - } - break; - default: - default_map: - /* default memory mappings */ - for (i = 0; i < PCI_NUM_REGIONS; i++) { - int ofs; - u32 val, size; - - if (i == PCI_ROM_SLOT) - ofs = PCI_ROM_ADDRESS; - else - ofs = PCI_BASE_ADDRESS_0 + i * 4; - pci_config_writel(bdf, ofs, 0xffffffff); - val = pci_config_readl(bdf, ofs); - if (val != 0) { - size = (~(val & ~0xf)) + 1; - if (val & PCI_BASE_ADDRESS_SPACE_IO) - paddr = &pci_bios_io_addr; - else if (size >= 0x04000000) - paddr = &pci_bios_bigmem_addr; - else - paddr = &pci_bios_mem_addr; - *paddr = ALIGN(*paddr, size); - pci_set_io_region_addr(bdf, i, *paddr); - *paddr += size; - } - } - break; - } + , pci_bdf_to_bus(bdf), pci_bdf_to_devfn(bdf) + , pci->vendor, pci->device); + pci_init_device(pci_class_tbl, pci, NULL); + + /* enable memory mappings */ + pci_config_maskw(bdf, PCI_COMMAND, 0, PCI_COMMAND_IO | PCI_COMMAND_MEMORY); /* map the interrupt */ pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN); @@ -173,34 +426,354 @@ static void pci_bios_init_device(u16 bdf) pci_config_writeb(bdf, PCI_INTERRUPT_LINE, pic_irq); } - if (vendor_id == PCI_VENDOR_ID_INTEL - && device_id == PCI_DEVICE_ID_INTEL_82371AB_3) { - /* PIIX4 Power Management device (for ACPI) */ - pci_config_writel(bdf, 0x40, PORT_ACPI_PM_BASE | 1); - pci_config_writeb(bdf, 0x80, 0x01); /* enable PM io space */ - pci_config_writel(bdf, 0x90, PORT_SMB_BASE | 1); - pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */ + pci_init_device(pci_device_tbl, pci, NULL); +} + +static void pci_bios_init_device_in_bus(int bus) +{ + struct pci_device *pci; + foreachpci(pci) { + u8 pci_bus = pci_bdf_to_bus(pci->bdf); + if (pci_bus < bus) + continue; + if (pci_bus > bus) + break; + pci_bios_init_device(pci); + } +} + +static void +pci_bios_init_bus_rec(int bus, u8 *pci_bus) +{ + int bdf; + u16 class; + + dprintf(1, "PCI: %s bus = 0x%x\n", __func__, bus); + + /* prevent accidental access to unintended devices */ + foreachbdf(bdf, bus) { + class = pci_config_readw(bdf, PCI_CLASS_DEVICE); + if (class == PCI_CLASS_BRIDGE_PCI) { + pci_config_writeb(bdf, PCI_SECONDARY_BUS, 255); + pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 0); + } + } + + foreachbdf(bdf, bus) { + class = pci_config_readw(bdf, PCI_CLASS_DEVICE); + if (class != PCI_CLASS_BRIDGE_PCI) { + continue; + } + dprintf(1, "PCI: %s bdf = 0x%x\n", __func__, bdf); + + u8 pribus = pci_config_readb(bdf, PCI_PRIMARY_BUS); + if (pribus != bus) { + dprintf(1, "PCI: primary bus = 0x%x -> 0x%x\n", pribus, bus); + pci_config_writeb(bdf, PCI_PRIMARY_BUS, bus); + } else { + dprintf(1, "PCI: primary bus = 0x%x\n", pribus); + } + + u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS); + (*pci_bus)++; + if (*pci_bus != secbus) { + dprintf(1, "PCI: secondary bus = 0x%x -> 0x%x\n", + secbus, *pci_bus); + secbus = *pci_bus; + pci_config_writeb(bdf, PCI_SECONDARY_BUS, secbus); + } else { + dprintf(1, "PCI: secondary bus = 0x%x\n", secbus); + } + + /* set to max for access to all subordinate buses. + later set it to accurate value */ + u8 subbus = pci_config_readb(bdf, PCI_SUBORDINATE_BUS); + pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 255); + + pci_bios_init_bus_rec(secbus, pci_bus); + + if (subbus != *pci_bus) { + dprintf(1, "PCI: subordinate bus = 0x%x -> 0x%x\n", + subbus, *pci_bus); + subbus = *pci_bus; + } else { + dprintf(1, "PCI: subordinate bus = 0x%x\n", subbus); + } + pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, subbus); + } +} + +static void +pci_bios_init_bus(void) +{ + u8 pci_bus = 0; + pci_bios_init_bus_rec(0 /* host bus */, &pci_bus); + busses_count = pci_bus + 1; +} + +static void pci_bios_bus_get_bar(struct pci_bus *bus, int bdf, int bar, + u32 *val, u32 *size) +{ + u32 ofs = pci_bar(bdf, bar); + u32 old = pci_config_readl(bdf, ofs); + u32 mask; + + if (bar == PCI_ROM_SLOT) { + mask = PCI_ROM_ADDRESS_MASK; + pci_config_writel(bdf, ofs, mask); + } else { + if (old & PCI_BASE_ADDRESS_SPACE_IO) + mask = PCI_BASE_ADDRESS_IO_MASK; + else + mask = PCI_BASE_ADDRESS_MEM_MASK; + pci_config_writel(bdf, ofs, ~0); + } + *val = pci_config_readl(bdf, ofs); + pci_config_writel(bdf, ofs, old); + *size = (~(*val & mask)) + 1; +} + +static void pci_bios_bus_reserve(struct pci_bus *bus, int type, u32 size) +{ + u32 index; + + index = pci_size_to_index(size, type); + size = pci_index_to_size(index, type); + bus->r[type].count[index]++; + bus->r[type].sum += size; + if (bus->r[type].max < size) + bus->r[type].max = size; +} + +static u32 pci_bios_bus_get_addr(struct pci_bus *bus, int type, u32 size) +{ + u32 index, addr; + + index = pci_size_to_index(size, type); + addr = bus->r[type].bases[index]; + bus->r[type].bases[index] += pci_index_to_size(index, type); + return addr; +} + +static void pci_bios_check_device(struct pci_bus *bus, struct pci_device *dev) +{ + u16 bdf = dev->bdf; + u32 limit; + int i,type; + + if (dev->class == PCI_CLASS_BRIDGE_PCI) { + if (dev->secondary_bus >= busses_count) { + /* should never trigger */ + dprintf(1, "PCI: bus count too small (%d), skipping bus #%d\n", + busses_count, dev->secondary_bus); + return; + } + struct pci_bus *s = busses + dev->secondary_bus; + pci_bios_check_device_in_bus(dev->secondary_bus); + for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) { + limit = (type == PCI_REGION_TYPE_IO) ? + PCI_BRIDGE_IO_MIN : PCI_BRIDGE_MEM_MIN; + s->r[type].size = s->r[type].sum; + if (s->r[type].size < limit) + s->r[type].size = limit; + s->r[type].size = pci_size_roundup(s->r[type].size); + pci_bios_bus_reserve(bus, type, s->r[type].size); + } + dprintf(1, "PCI: secondary bus %d sizes: io %x, mem %x, prefmem %x\n", + dev->secondary_bus, + s->r[PCI_REGION_TYPE_IO].size, + s->r[PCI_REGION_TYPE_MEM].size, + s->r[PCI_REGION_TYPE_PREFMEM].size); + return; + } + + for (i = 0; i < PCI_NUM_REGIONS; i++) { + u32 val, size; + pci_bios_bus_get_bar(bus, bdf, i, &val, &size); + if (val == 0) { + continue; + } + pci_bios_bus_reserve(bus, pci_addr_to_type(val), size); + dev->bars[i].addr = val; + dev->bars[i].size = size; + dev->bars[i].is64 = (!(val & PCI_BASE_ADDRESS_SPACE_IO) && + (val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64); + + if (dev->bars[i].is64) { + i++; + } + } +} + +static void pci_bios_map_device(struct pci_bus *bus, struct pci_device *dev) +{ + int type, i; + + if (dev->class == PCI_CLASS_BRIDGE_PCI) { + if (dev->secondary_bus >= busses_count) { + return; + } + struct pci_bus *s = busses + dev->secondary_bus; + + for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) { + s->r[type].base = pci_bios_bus_get_addr(bus, type, s->r[type].size); + } + dprintf(1, "PCI: init bases bus %d (secondary)\n", dev->secondary_bus); + pci_bios_init_bus_bases(s); + /* TODO: commit assignments */ + + pci_bios_map_device_in_bus(dev->secondary_bus); + return; + } + + for (i = 0; i < PCI_NUM_REGIONS; i++) { + u32 addr; + if (dev->bars[i].addr == 0) { + continue; + } + + addr = pci_bios_bus_get_addr(bus, pci_addr_to_type(dev->bars[i].addr), + dev->bars[i].size); + dprintf(1, " bar %d, addr %x, size %x [%s]\n", + i, addr, dev->bars[i].size, + dev->bars[i].addr & PCI_BASE_ADDRESS_SPACE_IO ? "io" : "mem"); + /* TODO: commit assignments */ + + if (dev->bars[i].is64) { + i++; + } + } +} + +static void pci_bios_check_device_in_bus(int bus) +{ + struct pci_device *pci; + + dprintf(1, "PCI: check devices bus %d\n", bus); + foreachpci(pci) { + if (pci_bdf_to_bus(pci->bdf) != bus) + continue; + pci_bios_check_device(&busses[bus], pci); + } +} + +static void pci_bios_map_device_in_bus(int bus) +{ + struct pci_device *pci; + + foreachpci(pci) { + if (pci_bdf_to_bus(pci->bdf) != bus) + continue; + dprintf(1, "PCI: map device bus %d, bfd 0x%x\n", bus, pci->bdf); + pci_bios_map_device(&busses[bus], pci); + } +} + +static void pci_bios_init_bus_bases(struct pci_bus *bus) +{ + u32 base, newbase, size; + int type, i; + + for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) { + dprintf(1, " type %s max %x sum %x base %x\n", region_type_name[type], + bus->r[type].max, bus->r[type].sum, bus->r[type].base); + base = bus->r[type].base; + for (i = ARRAY_SIZE(bus->r[type].count)-1; i >= 0; i--) { + size = pci_index_to_size(i, type); + if (!bus->r[type].count[i]) + continue; + newbase = base + size * bus->r[type].count[i]; + dprintf(1, " size %8x: %d bar(s), %8x -> %8x\n", + size, bus->r[type].count[i], base, newbase - 1); + bus->r[type].bases[i] = base; + base = newbase; + } + } +} + +#define ROOT_BASE(top, sum, align) ALIGN_DOWN((top)-(sum),(align)) + +static int pci_bios_init_root_regions(u32 start, u32 end) +{ + struct pci_bus *bus = &busses[0]; + + bus->r[PCI_REGION_TYPE_IO].base = 0xc000; + + if (bus->r[PCI_REGION_TYPE_MEM].sum < bus->r[PCI_REGION_TYPE_PREFMEM].sum) { + bus->r[PCI_REGION_TYPE_MEM].base = + ROOT_BASE(end, + bus->r[PCI_REGION_TYPE_MEM].sum, + bus->r[PCI_REGION_TYPE_MEM].max); + bus->r[PCI_REGION_TYPE_PREFMEM].base = + ROOT_BASE(bus->r[PCI_REGION_TYPE_MEM].base, + bus->r[PCI_REGION_TYPE_PREFMEM].sum, + bus->r[PCI_REGION_TYPE_PREFMEM].max); + if (bus->r[PCI_REGION_TYPE_PREFMEM].base >= start) { + return 0; + } + } else { + bus->r[PCI_REGION_TYPE_PREFMEM].base = + ROOT_BASE(end, + bus->r[PCI_REGION_TYPE_PREFMEM].sum, + bus->r[PCI_REGION_TYPE_PREFMEM].max); + bus->r[PCI_REGION_TYPE_MEM].base = + ROOT_BASE(bus->r[PCI_REGION_TYPE_PREFMEM].base, + bus->r[PCI_REGION_TYPE_MEM].sum, + bus->r[PCI_REGION_TYPE_MEM].max); + if (bus->r[PCI_REGION_TYPE_MEM].base >= start) { + return 0; + } } + return -1; } void -pci_bios_setup(void) +pci_setup(void) { - if (CONFIG_COREBOOT) - // Already done by coreboot. + if (CONFIG_COREBOOT || usingXen()) { + // PCI setup already done by coreboot or Xen - just do probe. + pci_probe(); return; + } + + dprintf(3, "pci setup\n"); - pci_bios_io_addr = 0xc000; - pci_bios_mem_addr = 0xf0000000; - pci_bios_bigmem_addr = RamSize; - if (pci_bios_bigmem_addr < 0x90000000) - pci_bios_bigmem_addr = 0x90000000; + u32 start = BUILD_PCIMEM_START; + u32 end = BUILD_IOAPIC_ADDR; - int bdf, max; - foreachpci(bdf, max) { - pci_bios_init_bridges(bdf); + pci_region_init(&pci_bios_io_region, 0xc000, 64 * 1024 - 1); + pci_region_init(&pci_bios_mem_region, + BUILD_PCIMEM_START, BUILD_PCIMEM_END - 1); + pci_region_init(&pci_bios_prefmem_region, + BUILD_PCIPREFMEM_START, BUILD_PCIPREFMEM_END - 1); + + dprintf(1, "=== PCI bus & bridge init ===\n"); + pci_bios_init_bus(); + + dprintf(1, "=== PCI device probing ===\n"); + pci_probe(); + + dprintf(1, "=== PCI new allocation pass #1 ===\n"); + busses = malloc_tmp(sizeof(*busses) * busses_count); + memset(busses, 0, sizeof(*busses) * busses_count); + pci_bios_check_device_in_bus(0 /* host bus */); + if (pci_bios_init_root_regions(start, end) != 0) { + dprintf(1, "PCI: out of address space\n"); + /* Hmm, what do now? */ } - foreachpci(bdf, max) { - pci_bios_init_device(bdf); + + dprintf(1, "=== PCI new allocation pass #2 ===\n"); + dprintf(1, "PCI: init bases bus 0 (primary)\n"); + pci_bios_init_bus_bases(&busses[0]); + pci_bios_map_device_in_bus(0 /* host bus */); + + dprintf(1, "=== PCI old allocation pass ===\n"); + struct pci_device *pci; + foreachpci(pci) { + pci_init_device(pci_isa_bridge_tbl, pci, NULL); } + pci_bios_init_device_in_bus(0 /* host bus */); + + free(busses); + busses_count = 0; }