X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fpcibios.c;h=31ca37e5caa64a802989371a3f6f7516ffe995c7;hb=5044053c84df0d423cdb61fcf29fe2cba2326f31;hp=2425a65c7f4898ccc1499d0062c157ca341bb911;hpb=871e0a0c142f7b2fcaa93600c5958d4ae4fa1394;p=seabios.git

diff --git a/src/pcibios.c b/src/pcibios.c
index 2425a65..31ca37e 100644
--- a/src/pcibios.c
+++ b/src/pcibios.c
@@ -13,8 +13,8 @@
 #include "pci_regs.h" // PCI_VENDOR_ID
 
 // romlayout.S
-extern void bios32_entry();
-extern void pcibios32_entry();
+extern void bios32_entry(void);
+extern void pcibios32_entry(void);
 
 #define RET_FUNC_NOT_SUPPORTED 0x81
 #define RET_BAD_VENDOR_ID      0x83
@@ -25,14 +25,9 @@ extern void pcibios32_entry();
 static void
 handle_1ab101(struct bregs *regs)
 {
-    // Find max bus.
-    int bdf, max;
-    foreachpci(bdf, max) {
-    }
-
     regs->al = 0x01; // Flags - "Config Mechanism #1" supported.
     regs->bx = 0x0210; // PCI version 2.10
-    regs->cl = pci_bdf_to_bus(max - 1);
+    regs->cl = GET_GLOBAL(MaxPCIBus);
     regs->edx = 0x20494350; // "PCI "
     regs->edi = (u32)pcibios32_entry + BUILD_BIOS_ADDR;
     set_code_success(regs);
@@ -44,16 +39,20 @@ handle_1ab102(struct bregs *regs)
 {
     u32 id = (regs->cx << 16) | regs->dx;
     int count = regs->si;
-    int bdf, max;
-    foreachpci(bdf, max) {
-        u32 v = pci_config_readl(bdf, PCI_VENDOR_ID);
-        if (v != id)
-            continue;
-        if (count--)
-            continue;
-        regs->bx = bdf;
-        set_code_success(regs);
-        return;
+    int bus = -1;
+    while (bus < GET_GLOBAL(MaxPCIBus)) {
+        bus++;
+        int bdf;
+        foreachbdf(bdf, bus) {
+            u32 v = pci_config_readl(bdf, PCI_VENDOR_ID);
+            if (v != id)
+                continue;
+            if (count--)
+                continue;
+            regs->bx = bdf;
+            set_code_success(regs);
+            return;
+        }
     }
     set_code_invalid(regs, RET_DEVICE_NOT_FOUND);
 }
@@ -64,16 +63,20 @@ handle_1ab103(struct bregs *regs)
 {
     int count = regs->si;
     u32 classprog = regs->ecx;
-    int bdf, max;
-    foreachpci(bdf, max) {
-        u32 v = pci_config_readl(bdf, PCI_CLASS_REVISION);
-        if ((v>>8) != classprog)
-            continue;
-        if (count--)
-            continue;
-        regs->bx = bdf;
-        set_code_success(regs);
-        return;
+    int bus = -1;
+    while (bus < GET_GLOBAL(MaxPCIBus)) {
+        bus++;
+        int bdf;
+        foreachbdf(bdf, bus) {
+            u32 v = pci_config_readl(bdf, PCI_CLASS_REVISION);
+            if ((v>>8) != classprog)
+                continue;
+            if (count--)
+                continue;
+            regs->bx = bdf;
+            set_code_success(regs);
+            return;
+        }
     }
     set_code_invalid(regs, RET_DEVICE_NOT_FOUND);
 }
@@ -202,7 +205,6 @@ handle_1ab1(struct bregs *regs)
  * 32bit interface
  ****************************************************************/
 
-#if MODE16 == 0 && MODESEGMENT == 1
 // Entry point for 32bit pci bios functions.
 void VISIBLE32SEG
 handle_pcibios32(struct bregs *regs)
@@ -210,7 +212,6 @@ handle_pcibios32(struct bregs *regs)
     debug_enter(regs, DEBUG_HDL_pcibios32);
     handle_1ab1(regs);
 }
-#endif
 
 struct bios32_s {
     u32 signature;