X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fpc_communication.vhd;h=ca885dd5da144295b812c08b926f015af20323c0;hb=c8121750fe9ee3825f64957884849b0e52866606;hp=89dff252be4bc9cd13891311d76123ad7465a19a;hpb=030287b141ae40fd8c7e9e8060ee7a96ba109499;p=hwmod.git

diff --git a/src/pc_communication.vhd b/src/pc_communication.vhd
index 89dff25..ca885dd 100644
--- a/src/pc_communication.vhd
+++ b/src/pc_communication.vhd
@@ -24,26 +24,22 @@ entity pc_communication is
 		pc_zeile : out hzeile;
 		pc_spalte : out hspalte;
 		pc_get :  out std_logic;
-		pc_busy : in std_logic; --signals if the history module actually grants our request.
 		pc_done : in std_logic;
 		pc_char : in hbyte
 	);
 end entity pc_communication;
 
 architecture beh of pc_communication is
-	signal spalte, spalte_next : integer range 1 to hspalte_max + 1;
-	signal zeile , zeile_next : integer range 1 to hzeile_max + 1;
+	signal spalte, spalte_next : integer range 1 to HSPALTE_MAX + 2;
+	signal zeile , zeile_next : integer range 0 to HZEILE_MAX + 1;
 	signal get, get_next : std_logic;
 	signal new_i, new_i_next : std_logic;
 	signal tx_done_i, tx_done_i_next : std_logic;
 	signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0);
 
-	type STATE_PC is (IDLE, WAIT_HIST, FETCH, FORWARD, WAIT_UART, UART_DONE);
+	type STATE_PC is (IDLE, FETCH, FORWARD, WAIT_UART, UART_DONE, CR, CR_WAIT, NL, NL_WAIT);
 	signal state, state_next : STATE_PC ;
-
 begin
-
-
 	pc_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
 	pc_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
 	pc_get <= get;
@@ -56,10 +52,10 @@ begin
 		if sys_res_n = '0' then
 			state <= IDLE;
 			spalte <= 1;
-			zeile <= 1;
+			zeile <= 0;
 			get <= '0';
 			new_i <= '0';
-			tx_data_i <= "00000000";
+			tx_data_i <= x"00";
 			tx_done_i <= '0';
 		elsif rising_edge(sys_clk) then
 			spalte <= spalte_next;
@@ -72,72 +68,72 @@ begin
 		end if;
 	end process sync;
 
-	output_pc : process (state, zeile, spalte, tx_data_i, tx_done_i, pc_char)
+	process (state, zeile, spalte, tx_data_i, tx_done_i, pc_char, rx_new, btn_a,
+		pc_done)
 	begin
 		get_next <= '0';
 		new_i_next <= '0';
-
 		spalte_next <= spalte;
 		zeile_next <= zeile;
 		tx_data_i_next <= tx_data_i;
 
-		case state is
-			when IDLE =>
-				null;
-			when FETCH =>
-				get_next <= '1';
-			when WAIT_HIST =>
-			tx_data_i_next <= pc_char;
-			when FORWARD =>
-				new_i_next <= '1';
-			when WAIT_UART =>
-				null;
-			when UART_DONE =>
-				if tx_data_i = x"00" or spalte = hspalte_max then
-					zeile_next <= zeile + 1;
-					spalte_next <= 1;
-					if zeile = hzeile_max then
-						zeile_next <= 1;
-					end if;
-				else
-					spalte_next <= spalte + 1;
-				end if;
-		end case;
-	end process output_pc;
-
-	next_state_pc : process (btn_a, pc_busy, pc_done, rx_new, rx_data, spalte, 
-		state, tx_data_i ,tx_done_i, zeile)
-	begin
 		state_next <= state;
 		case state is
 			when IDLE =>
-				if (rx_new = '1' and rx_data = x"0a" ) or btn_a = '0' then
+--				if (rx_new = '1' and rx_data = x"0a") or btn_a = '0' then
+				if (rx_new = '1') or btn_a = '0' then
 					state_next <= FETCH;
 				end if;
 			when FETCH =>
-				if pc_busy = '1' then
-					state_next <= WAIT_HIST;
-				else
-					state_next <= FETCH;
-				end if;
-			when WAIT_HIST =>
-				if (pc_done = '1') then
-					state_next <= FORWARD;
+				get_next <= '1';
+				if pc_done = '1' and tx_done_i = '0' then
+					if pc_char = x"00" then
+						state_next <= UART_DONE;
+					else
+						state_next <= FORWARD;
+					end if;
 				end if;
 			when FORWARD =>
+				tx_data_i_next <= pc_char;
+				new_i_next <= '1';
+				-- halte pc_get weiterhin high sodass pc_char garantiert gleich bleibt
+				get_next <= '1';
 				state_next <= WAIT_UART;
 			when WAIT_UART =>
-				if (tx_done_i = '1') then
+				new_i_next <= '1';
+				get_next <= '1';
+				if tx_done_i = '1' then
 					state_next <= UART_DONE;
 				end if;
-			when UART_DONE =>
-				if (tx_data_i = x"00" or spalte = hspalte_max) and
-					zeile = hzeile_max then
+			when UART_DONE => null;
+				state_next <= FETCH;
+				spalte_next <= spalte + 1;
+				if spalte = HSPALTE_MAX + 1 then
+					state_next <= NL;
+					spalte_next <= 1;
+					zeile_next <= zeile + 1;
+				end if;
+			when NL =>
+				tx_data_i_next <= x"0a";
+				new_i_next <= '1';
+				if tx_done_i = '1' then
+					state_next <= NL_WAIT;
+				end if;
+			when NL_WAIT =>
+				state_next <= CR;
+			when CR =>
+				tx_data_i_next <= x"0d";
+				new_i_next <= '1';
+				if tx_done_i = '1' then
+					state_next <= CR_WAIT;
+				end if;
+			when CR_WAIT =>
+				state_next <= FETCH;
+				if zeile = HZEILE_MAX then
 					state_next <= IDLE;
-				else
-					state_next <= FETCH;
+					zeile_next <= 0;
+					spalte_next <= 1;
 				end if;
 		end case;
-	end process next_state_pc;
-
+	end process;
 end architecture beh;