X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fpc_communication.vhd;h=c422ed7ade9d9dfb9cecf4992c4c674ab90ec9b1;hb=5198223f6d43e915eed4be1d0bbbbc7f908ef6b1;hp=3681c6907efcbb495e46fb2502c73269bb044482;hpb=021eb0653bb6229cc9275cd8198ce03301f54a39;p=hwmod.git

diff --git a/src/pc_communication.vhd b/src/pc_communication.vhd
index 3681c69..c422ed7 100644
--- a/src/pc_communication.vhd
+++ b/src/pc_communication.vhd
@@ -3,7 +3,6 @@ use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 use work.gen_pkg.all;
 
-
 entity pc_communication is
 	port (
 		sys_clk : in std_logic;
@@ -18,51 +17,129 @@ entity pc_communication is
 		tx_done : in std_logic;
 
 		--uart_rx
-		rx_data : in std_logic_vector(7 downt 0); --not really required
-		rx_new : in std_logic_vector;
+		rx_data : in std_logic_vector(7 downto 0);
+		rx_new : in std_logic;
 
 		-- History
-		d_zeile : out hzeile;
-		d_spalte : out hspalte;
-		d_get :  out std_logic;
-		d_done : in std_logic;
-		d_char : in hbyte --;
+		pc_zeile : out hzeile;
+		pc_spalte : out hspalte;
+		pc_get :  out std_logic;
+		pc_done : in std_logic;
+		pc_char : in hbyte
 	);
 end entity pc_communication;
 
+architecture beh of pc_communication is
+	signal spalte, spalte_next : integer range 1 to HSPALTE_MAX + 2;
+	signal zeile , zeile_next : integer range 0 to HZEILE_MAX + 1;
+	signal get, get_next : std_logic;
+	signal new_i, new_i_next : std_logic;
+	signal tx_done_i, tx_done_i_next : std_logic;
+	signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0);
 
-
-architecture beh of display is
-	signal push_history, push_history_next : std_logic;
+	type STATE_PC is (IDLE, FETCH, FORWARD, WAIT_UART, UART_DONE, CALC_VAL);
+	signal state, state_next : STATE_PC ;
 begin
+	pc_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
+	pc_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
+	pc_get <= get;
+	tx_new <= new_i;
+	tx_done_i_next <= tx_done;
+	tx_data <= tx_data_i;
 
-	sync_push_history : process (sys_clk, sys_res_n)
+	sync: process (sys_clk, sys_res_n)
 	begin
 		if sys_res_n = '0' then
-			push_history <= '0';
+			state <= IDLE;
+			spalte <= 1;
+			zeile <= 0;
+			get <= '0';
+			new_i <= '0';
+			tx_data_i <= x"00";
+			tx_done_i <= '0';
 		elsif rising_edge(sys_clk) then
-			push_history <= push_history_next;
+			spalte <= spalte_next;
+			zeile <= zeile_next;
+			state <= state_next;
+			get <= get_next;
+			new_i <= new_i_next;
+			tx_done_i <= tx_done_i_next;
+			tx_data_i <= tx_data_i_next;
 		end if;
-	end process sync_push_history;
+	end process sync;
 
-	push_history : process(rx_new, rx_data, btn_a)
+	output_pc : process (state, zeile, spalte, tx_data_i, tx_done_i, pc_char)
 	begin
-		if ( (rx_new = '1' and rx_data = X"41") or btn_a '1') then
-			push_history_next <= '1';
-		else
-			push_history_next <= '0';
-		end if;
-	end process push_history;
+		get_next <= '0';
+		new_i_next <= '0';
+
+		spalte_next <= spalte;
+		zeile_next <= zeile;
+		tx_data_i_next <= tx_data_i;
 
---	sync_pc : process ()
---	begin
---	end process sync_pc;
---
---	next_state_pc : process ()
---	begin
---	end process next_state_pc;
---
---	output_pc : process ()
---	begin
---	end process output_pc;
+		case state is
+			when IDLE =>
+				null;
+			when FETCH =>
+				get_next <= '1';
+			when FORWARD =>
+				tx_data_i_next <= pc_char;
+				new_i_next <= '1';
+				-- halte pc_get weiterhin high sodass pc_char garantiert gleich bleibt
+				get_next <= '1';
+			when WAIT_UART =>
+				new_i_next <= '1';
+				get_next <= '1';
+			when UART_DONE => null;
+				-- get_next <= '0';
+				-- new_i_next <= '0';
+			when CALC_VAL =>
+				spalte_next <= spalte + 1;
+				if spalte = HSPALTE_MAX + 1 then
+					tx_data_i_next <= x"0a";
+					new_i_next <= '1';
+
+					spalte_next <= 1;
+					zeile_next <= zeile + 1;
+					if zeile = HZEILE_MAX-1 then
+						zeile_next <= 0;
+					end if;
+				end if;
+		end case;
+	end process output_pc;
+
+	next_state_pc : process (btn_a, pc_done, rx_new, rx_data, spalte, state,
+		tx_data_i ,tx_done_i, zeile, pc_char)
+	begin
+		state_next <= state;
+		case state is
+			when IDLE =>
+--				if (rx_new = '1' and rx_data = x"0a") or btn_a = '0' then
+				if (rx_new = '1') or btn_a = '0' then
+					state_next <= FETCH;
+				end if;
+			when FETCH =>
+				if pc_done = '1' and tx_done_i = '0' then
+					if pc_char = x"00" then
+						state_next <= UART_DONE;
+					else
+						state_next <= FORWARD;
+					end if;
+				end if;
+			when FORWARD =>
+				state_next <= WAIT_UART;
+			when WAIT_UART =>
+				if (tx_done_i = '1') then
+					state_next <= UART_DONE;
+				end if;
+			when UART_DONE =>
+				state_next <= CALC_VAL;
+			when CALC_VAL =>
+				if spalte = HSPALTE_MAX + 1 and zeile = HZEILE_MAX - 1 then
+					state_next <= IDLE;
+				else
+					state_next <= FETCH;
+				end if;
+		end case;
+	end process next_state_pc;
 end architecture beh;