X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fpc_communication.vhd;h=b593b33a1a01f318a953bc33863fe0bc29c4f51b;hb=b42b2b9d669e1d12db43c70704b4657901d1ab02;hp=b40444682580dddb605740bbba66703fa8517077;hpb=4daed56adb94596e6e991086a40f52e4a0b34efe;p=hwmod.git

diff --git a/src/pc_communication.vhd b/src/pc_communication.vhd
index b404446..b593b33 100644
--- a/src/pc_communication.vhd
+++ b/src/pc_communication.vhd
@@ -24,14 +24,15 @@ entity pc_communication is
 		pc_zeile : out hzeile;
 		pc_spalte : out hspalte;
 		pc_get :  out std_logic;
+		pc_busy : in std_logic; --signals if the history module actually grants our request.
 		pc_done : in std_logic;
 		pc_char : in hbyte
 	);
 end entity pc_communication;
 
 architecture beh of pc_communication is
-	signal spalte, spalte_next : integer range 1 to hspalte_max + 1;
-	signal zeile , zeile_next : integer range 1 to hzeile_max + 1;
+	signal spalte, spalte_next : integer range 1 to HSPALTE_MAX + 1;
+	signal zeile , zeile_next : integer range 1 to HZEILE_MAX + 1;
 	signal get, get_next : std_logic;
 	signal new_i, new_i_next : std_logic;
 	signal tx_done_i, tx_done_i_next : std_logic;
@@ -86,16 +87,17 @@ begin
 			when FETCH =>
 				get_next <= '1';
 			when WAIT_HIST =>
-			tx_data_i_next <= pc_char;
+				tx_data_i_next <= pc_char;
 			when FORWARD =>
 				new_i_next <= '1';
 			when WAIT_UART =>
-				null;
+				new_i_next <= '1';
 			when UART_DONE =>
-				if tx_data_i = x"00" or spalte = hspalte_max then
+				if tx_data_i = x"00" or spalte = HSPALTE_MAX then
+					tx_data_i_next <= x"0a";
 					zeile_next <= zeile + 1;
 					spalte_next <= 1;
-					if zeile = hzeile_max then
+					if zeile = HZEILE_MAX then
 						zeile_next <= 1;
 					end if;
 				else
@@ -104,17 +106,22 @@ begin
 		end case;
 	end process output_pc;
 
-	next_state_pc : process (btn_a, pc_done, rx_new, rx_data, spalte, state,
-		tx_data_i ,tx_done_i, zeile)
+	next_state_pc : process (btn_a, pc_busy, pc_done, rx_new, rx_data, spalte,
+		state, tx_data_i ,tx_done_i, zeile)
 	begin
 		state_next <= state;
 		case state is
 			when IDLE =>
-				if (rx_new = '1' and rx_data = x"0a" ) or btn_a = '1' then
+--				if (rx_new = '1' and rx_data = x"0a") or btn_a = '0' then
+				if (rx_new = '1') or btn_a = '0' then
 					state_next <= FETCH;
 				end if;
 			when FETCH =>
-				state_next <= WAIT_HIST;
+				if pc_busy = '1' then
+					state_next <= WAIT_HIST;
+				else
+					state_next <= FETCH;
+				end if;
 			when WAIT_HIST =>
 				if (pc_done = '1') then
 					state_next <= FORWARD;
@@ -126,8 +133,8 @@ begin
 					state_next <= UART_DONE;
 				end if;
 			when UART_DONE =>
-				if (tx_data_i = x"00" or spalte = hspalte_max) and
-					zeile = hzeile_max then
+				if (tx_data_i = x"00" or spalte = HSPALTE_MAX) and
+					zeile = HZEILE_MAX then
 					state_next <= IDLE;
 				else
 					state_next <= FETCH;