X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fpc_communication.vhd;h=89dff252be4bc9cd13891311d76123ad7465a19a;hb=030287b141ae40fd8c7e9e8060ee7a96ba109499;hp=321d0a36feb4627e4a41f50216909c8a6614341b;hpb=6001db94b7d15e097001a3e4e8b4ea1eaee75bad;p=hwmod.git

diff --git a/src/pc_communication.vhd b/src/pc_communication.vhd
index 321d0a3..89dff25 100644
--- a/src/pc_communication.vhd
+++ b/src/pc_communication.vhd
@@ -21,11 +21,12 @@ entity pc_communication is
 		rx_new : in std_logic;
 
 		-- History
-		d_zeile : out hzeile;
-		d_spalte : out hspalte;
-		d_get :  out std_logic;
-		d_done : in std_logic;
-		d_char : in hbyte
+		pc_zeile : out hzeile;
+		pc_spalte : out hspalte;
+		pc_get :  out std_logic;
+		pc_busy : in std_logic; --signals if the history module actually grants our request.
+		pc_done : in std_logic;
+		pc_char : in hbyte
 	);
 end entity pc_communication;
 
@@ -36,17 +37,16 @@ architecture beh of pc_communication is
 	signal new_i, new_i_next : std_logic;
 	signal tx_done_i, tx_done_i_next : std_logic;
 	signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0);
-	signal s_done, s_done_next : std_logic;
 
-	type STATE_PC is (IDLE, FETCH, FORWARD, DONE);
+	type STATE_PC is (IDLE, WAIT_HIST, FETCH, FORWARD, WAIT_UART, UART_DONE);
 	signal state, state_next : STATE_PC ;
 
 begin
 
 
-	d_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
-	d_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
-	d_get <= get;
+	pc_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
+	pc_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
+	pc_get <= get;
 	tx_new <= new_i;
 	tx_done_i_next <= tx_done;
 	tx_data <= tx_data_i;
@@ -61,7 +61,6 @@ begin
 			new_i <= '0';
 			tx_data_i <= "00000000";
 			tx_done_i <= '0';
-			s_done <= '0';
 		elsif rising_edge(sys_clk) then
 			spalte <= spalte_next;
 			zeile <= zeile_next;
@@ -70,76 +69,74 @@ begin
 			new_i <= new_i_next;
 			tx_done_i <= tx_done_i_next;
 			tx_data_i <= tx_data_i_next;
-			s_done <= s_done_next;
 		end if;
 	end process sync;
 
-	output_pc : process (state, zeile, spalte, tx_data_i, tx_done_i)
-	variable spalte_up : std_logic;
+	output_pc : process (state, zeile, spalte, tx_data_i, tx_done_i, pc_char)
 	begin
 		get_next <= '0';
 		new_i_next <= '0';
 
-		s_done_next <= '0';
 		spalte_next <= spalte;
 		zeile_next <= zeile;
 		tx_data_i_next <= tx_data_i;
-		spalte_up := '0';
 
 		case state is
 			when IDLE =>
 				null;
 			when FETCH =>
 				get_next <= '1';
-				tx_data_i_next <= d_char;
+			when WAIT_HIST =>
+			tx_data_i_next <= pc_char;
 			when FORWARD =>
 				new_i_next <= '1';
-				if (tx_done_i = '1') then
-					spalte_up := '1';
-				end if;
-
-			when DONE =>
+			when WAIT_UART =>
 				null;
-		end case;
-
-		if spalte_up = '1' then
-			if spalte = hspalte_max  then
-				if zeile = hzeile_max then
+			when UART_DONE =>
+				if tx_data_i = x"00" or spalte = hspalte_max then
+					zeile_next <= zeile + 1;
 					spalte_next <= 1;
-					zeile_next <= 1;
-					s_done_next <= '1';
+					if zeile = hzeile_max then
+						zeile_next <= 1;
+					end if;
 				else
-					spalte_next <= 1;
-					zeile_next <= zeile + 1;
+					spalte_next <= spalte + 1;
 				end if;
-			else
-				spalte_next <= spalte + 1; --overflow here!
-				zeile_next <= zeile;
-			end if;
-		end if;
-
+		end case;
 	end process output_pc;
 
-	next_state_pc : process (state, rx_new, rx_data, btn_a, d_done, tx_done_i, s_done)
+	next_state_pc : process (btn_a, pc_busy, pc_done, rx_new, rx_data, spalte, 
+		state, tx_data_i ,tx_done_i, zeile)
 	begin
 		state_next <= state;
 		case state is
 			when IDLE =>
-				if (rx_new = '1' and rx_data = x"0a" ) or btn_a = '1' then
+				if (rx_new = '1' and rx_data = x"0a" ) or btn_a = '0' then
 					state_next <= FETCH;
 				end if;
 			when FETCH =>
-				if (d_done = '1') then
+				if pc_busy = '1' then
+					state_next <= WAIT_HIST;
+				else
+					state_next <= FETCH;
+				end if;
+			when WAIT_HIST =>
+				if (pc_done = '1') then
 					state_next <= FORWARD;
-				elsif (s_done = '1') then
-					state_next <= IDLE;
 				end if;
 			when FORWARD =>
+				state_next <= WAIT_UART;
+			when WAIT_UART =>
 				if (tx_done_i = '1') then
+					state_next <= UART_DONE;
+				end if;
+			when UART_DONE =>
+				if (tx_data_i = x"00" or spalte = hspalte_max) and
+					zeile = hzeile_max then
+					state_next <= IDLE;
+				else
 					state_next <= FETCH;
 				end if;
-			when DONE =>
-				state_next <= IDLE;
 		end case;
 	end process next_state_pc;