X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fpc_communication.vhd;h=410bc4fbb05aa0674f9e0eab1aa024bfa3da3b4d;hb=a1b9896ecd59e16ef6c28bc6990eadd6e0c515c8;hp=4bc09d4c9bd319f745f6a40bd5e9df4071099a93;hpb=7c42d302d04814bced7207f42a16a0876121c368;p=hwmod.git

diff --git a/src/pc_communication.vhd b/src/pc_communication.vhd
index 4bc09d4..410bc4f 100644
--- a/src/pc_communication.vhd
+++ b/src/pc_communication.vhd
@@ -17,143 +17,195 @@ entity pc_communication is
 		tx_done : in std_logic;
 
 		--uart_rx
-		rx_data : in std_logic_vector(7 downto 0); --not really required
+		rx_data : in std_logic_vector(7 downto 0);
 		rx_new : in std_logic;
 
 		-- History
-		d_zeile : out hzeile;
-		d_spalte : out hspalte;
-		d_get :  out std_logic;
-		d_done : in std_logic;
-		d_char : in hbyte
+		pc_zeile : out hzeile;
+		pc_spalte : out hspalte;
+		pc_get :  out std_logic;
+		pc_done : in std_logic;
+		pc_char : in hbyte
 	);
 end entity pc_communication;
 
 architecture beh of pc_communication is
-	signal push_history, push_history_next : std_logic;
-
-	signal spalte, spalte_next : integer range 0 to 71;
-	signal zeile , zeile_next : integer range 0 to 71;
-	signal spalte_up, spalte_up_next : std_logic;
+	signal spalte, spalte_next : integer range 1 to HSPALTE_MAX + 2;
+	signal zeile , zeile_next : integer range 0 to HZEILE_MAX + 1;
 	signal get, get_next : std_logic;
 	signal new_i, new_i_next : std_logic;
 	signal tx_done_i, tx_done_i_next : std_logic;
-	signal d_done_i, d_done_i_next : std_logic;
+	signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0);
 
-	signal char, char_next : hbyte;
-	signal char_en : std_logic;
-	type STATE_PC is (IDLE, FETCH, FORWARD, DONE);
+	type STATE_PC is (IDLE, FETCH, FORWARD, WAIT_UART, UART_DONE, CR, CR_WAIT,
+		NL, NL_WAIT, PRINT_NO1, PRINT_NO1_WAIT, PRINT_NO2, PRINT_NO2_WAIT,
+		PRINT_NO3, PRINT_NO3_WAIT, PRINT_NO4, PRINT_NO4_WAIT, PRINT_NO5,
+		PRINT_NO5_WAIT, PRINT_NO6, PRINT_NO0_WAIT);
 	signal state, state_next : STATE_PC ;
-
 begin
-
-
-	d_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
-	d_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
-	d_get <= get;
-	char_next <= d_char;
+	pc_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
+	pc_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
+	pc_get <= get;
 	tx_new <= new_i;
-	d_done_i <= d_done;
-	tx_done_i <= tx_done;
+	tx_done_i_next <= tx_done;
+	tx_data <= tx_data_i;
 
 	sync: process (sys_clk, sys_res_n)
 	begin
 		if sys_res_n = '0' then
 			state <= IDLE;
-			push_history <= '0';
-			spalte <= 0;
+			spalte <= 1;
 			zeile <= 0;
 			get <= '0';
 			new_i <= '0';
-			tx_data <= "00000000";
-			spalte_up <= '0';
+			tx_data_i <= x"00";
+			tx_done_i <= '0';
 		elsif rising_edge(sys_clk) then
-			push_history <= push_history_next;
 			spalte <= spalte_next;
 			zeile <= zeile_next;
 			state <= state_next;
 			get <= get_next;
 			new_i <= new_i_next;
-			spalte_up <= spalte_up_next;
-			if (char_en = '1') then
-				char <= char_next;
-			end if;
+			tx_done_i <= tx_done_i_next;
+			tx_data_i <= tx_data_i_next;
 		end if;
 	end process sync;
 
-	process (spalte_up, spalte, zeile)
-	begin
-		if (spalte_up = '1') then
-			if (spalte > 71) then
-				spalte_next <= 0;
-				zeile_next <= zeile + 1;
-			else
-				spalte_next <= spalte + 1;
-				zeile_next <= zeile;
-			end if;
-		else
-			spalte_next <= spalte;
-			zeile_next <= zeile;
-		end if;
-	end process;
-
-	async_push_history : process (rx_new, rx_data, btn_a)
-	begin
-		if rx_new = '1' then
-			if rx_data = X"41" then
-				push_history_next <= '1';
-			else
-				push_history_next <= '0';
-			end if;
-		elsif btn_a = '1' then
-				push_history_next <= '1';
-		else
-			push_history_next <= '0';
-		end if;
-	end process async_push_history;
-
-	output_pc : process (state, zeile, spalte, char)
+	process (state, zeile, spalte, tx_data_i, tx_done_i, pc_char, rx_new, btn_a,
+			pc_done)
+		variable tmp : std_logic_vector(6 downto 0);
 	begin
 		get_next <= '0';
 		new_i_next <= '0';
-		spalte_up_next <= '0';
+		spalte_next <= spalte;
+		zeile_next <= zeile;
+		tx_data_i_next <= tx_data_i;
+
+		state_next <= state;
 		case state is
 			when IDLE =>
-				null;
-			when FETCH =>
-				get_next <= '1';
-				char_en <= '1';
-			when FORWARD =>
-				char_en <= '0';
-				tx_data <= char;
-				new_i_next <= '1';
-				if (tx_done = '1') then
-					spalte_up_next <= '1';
+--				if (rx_new = '1' and rx_data = x"0a") or btn_a = '0' then
+				if (rx_new = '1') or btn_a = '0' then
+					state_next <= PRINT_NO0_WAIT;
 				end if;
-			when DONE =>
-				null;
-		end case;
-	end process output_pc;
 
-	next_state_pc : process (rx_new, btn_a, d_done, tx_done)
-	begin
-		case state is
-			when IDLE =>
-				if rx_new = '1' or btn_a = '1' then
+			when PRINT_NO0_WAIT =>
+				if tx_done_i = '0' then
+					state_next <= PRINT_NO1;
+				end if;
+			when PRINT_NO1 =>
+				tx_data_i_next <= x"28"; -- '('
+				new_i_next <= '1';
+				if tx_done_i = '1' then
+					state_next <= PRINT_NO1_WAIT;
+				end if;
+			when PRINT_NO1_WAIT =>
+				if tx_done_i = '0' then
+					state_next <= PRINT_NO2;
+				end if;
+			when PRINT_NO2 =>
+				tx_data_i_next <= zeile2char(std_logic_vector(to_unsigned(zeile,7)), 1);
+				new_i_next <= '1';
+				if tx_done_i = '1' then
+					state_next <= PRINT_NO2_WAIT;
+				end if;
+			when PRINT_NO2_WAIT =>
+				if tx_done_i = '0' then
+					state_next <= PRINT_NO3;
+				end if;
+			when PRINT_NO3 =>
+				tx_data_i_next <= zeile2char(std_logic_vector(to_unsigned(zeile,7)), 2);
+				new_i_next <= '1';
+				if tx_done_i = '1' then
+					state_next <= PRINT_NO3_WAIT;
+				end if;
+			when PRINT_NO3_WAIT =>
+				if tx_done_i = '0' then
+					state_next <= PRINT_NO4;
+				end if;
+			when PRINT_NO4 =>
+				tx_data_i_next <= x"29"; -- ')'
+				new_i_next <= '1';
+				if tx_done_i = '1' then
+					state_next <= PRINT_NO4_WAIT;
+				end if;
+			when PRINT_NO4_WAIT =>
+				if tx_done_i = '0' then
+					state_next <= PRINT_NO5;
+				end if;
+			when PRINT_NO5 =>
+				tx_data_i_next <= x"24"; -- '$'
+				new_i_next <= '1';
+				if tx_done_i = '1' then
+					state_next <= PRINT_NO5_WAIT;
+				end if;
+			when PRINT_NO5_WAIT =>
+				if tx_done_i = '0' then
+					state_next <= PRINT_NO6;
+				end if;
+			when PRINT_NO6 =>
+				tx_data_i_next <= x"20"; -- ' '
+				new_i_next <= '1';
+				if tx_done_i = '1' then
 					state_next <= FETCH;
-					
 				end if;
+
 			when FETCH =>
-				if (d_done = '1') then
+				get_next <= '1';
+				if pc_done = '1' and tx_done_i = '0' then
 					state_next <= FORWARD;
+					if pc_char = x"00" then
+						state_next <= UART_DONE;
+					end if;
 				end if;
 			when FORWARD =>
-				if (tx_done = '1') then
+				tx_data_i_next <= pc_char;
+				new_i_next <= '1';
+				-- halte pc_get weiterhin high sodass pc_char garantiert gleich bleibt
+				get_next <= '1';
+				state_next <= WAIT_UART;
+			when WAIT_UART =>
+				new_i_next <= '1';
+				get_next <= '1';
+				if tx_done_i = '1' then
+					state_next <= UART_DONE;
+				end if;
+			when UART_DONE =>
+				state_next <= FETCH;
+				spalte_next <= spalte + 1;
+				if spalte = HSPALTE_MAX + 1 then
+					state_next <= NL;
+					spalte_next <= 1;
+					zeile_next <= zeile + 1;
+				end if;
+			when NL =>
+				tx_data_i_next <= x"0a";
+				new_i_next <= '1';
+				if tx_done_i = '1' then
+					state_next <= NL_WAIT;
+				end if;
+			when NL_WAIT =>
+				state_next <= CR;
+			when CR =>
+				tx_data_i_next <= x"0d";
+				new_i_next <= '1';
+				if tx_done_i = '1' then
+					state_next <= CR_WAIT;
+				end if;
+			when CR_WAIT =>
+				tmp := std_logic_vector(to_unsigned(zeile,7));
+				if tmp(0) = '0' then
+					-- es handelt sich um eingabe
+					-- => print zeilennummer
+					state_next <= PRINT_NO0_WAIT;
+				else
 					state_next <= FETCH;
 				end if;
-			when DONE =>
-				state_next <= IDLE;
+				if zeile = HZEILE_MAX then
+					state_next <= IDLE;
+					zeile_next <= 0;
+					spalte_next <= 1;
+				end if;
 		end case;
-	end process next_state_pc;
-
+	end process;
 end architecture beh;