X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fpc_communication.vhd;h=321d0a36feb4627e4a41f50216909c8a6614341b;hb=6001db94b7d15e097001a3e4e8b4ea1eaee75bad;hp=4c3a8b9af7ee1025a15595dc083bea5a6eb0a74b;hpb=59c46d104154c881734b5dcdae684661dd56e6bd;p=hwmod.git

diff --git a/src/pc_communication.vhd b/src/pc_communication.vhd
index 4c3a8b9..321d0a3 100644
--- a/src/pc_communication.vhd
+++ b/src/pc_communication.vhd
@@ -17,7 +17,7 @@ entity pc_communication is
 		tx_done : in std_logic;
 
 		--uart_rx
-		rx_data : in std_logic_vector(7 downto 0); --not really required
+		rx_data : in std_logic_vector(7 downto 0);
 		rx_new : in std_logic;
 
 		-- History
@@ -30,123 +30,115 @@ entity pc_communication is
 end entity pc_communication;
 
 architecture beh of pc_communication is
-	signal push_history, push_history_next : std_logic;
+	signal spalte, spalte_next : integer range 1 to hspalte_max + 1;
+	signal zeile , zeile_next : integer range 1 to hzeile_max + 1;
+	signal get, get_next : std_logic;
+	signal new_i, new_i_next : std_logic;
+	signal tx_done_i, tx_done_i_next : std_logic;
+	signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0);
+	signal s_done, s_done_next : std_logic;
 
-	signal spalte, spalte_next : hspalte;
-	signal zeile , zeile_next : hzeile;
-	signal spalte_up, spalte_up_next : std_logic;
-
-	signal char, char_next : hbyte;
-	signal char_en : std_logic;
 	type STATE_PC is (IDLE, FETCH, FORWARD, DONE);
 	signal state, state_next : STATE_PC ;
 
 begin
 
+
+	d_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
+	d_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
+	d_get <= get;
+	tx_new <= new_i;
+	tx_done_i_next <= tx_done;
+	tx_data <= tx_data_i;
+
 	sync: process (sys_clk, sys_res_n)
 	begin
 		if sys_res_n = '0' then
 			state <= IDLE;
-			push_history <= '0';
-			spalte <= "0000000";
-			spalte_next <= "0000000";
-			zeile <= "0000000";
-			zeile_next <= "0000000";
-			d_get <= '0';
-			tx_new <= '0';
-			tx_data <= "00000000";
+			spalte <= 1;
+			zeile <= 1;
+			get <= '0';
+			new_i <= '0';
+			tx_data_i <= "00000000";
+			tx_done_i <= '0';
+			s_done <= '0';
 		elsif rising_edge(sys_clk) then
-			push_history <= push_history_next;
 			spalte <= spalte_next;
 			zeile <= zeile_next;
 			state <= state_next;
-			if (char_en = '1') then
-				state <= state_next;
-			end if;
+			get <= get_next;
+			new_i <= new_i_next;
+			tx_done_i <= tx_done_i_next;
+			tx_data_i <= tx_data_i_next;
+			s_done <= s_done_next;
 		end if;
 	end process sync;
 
-	process (spalte_up)
-	variable spalte_tmp, zeile_tmp : integer;
-	variable spalte2_tmp, zeile2_tmp : std_logic_vector(7 downto 0);
+	output_pc : process (state, zeile, spalte, tx_data_i, tx_done_i)
+	variable spalte_up : std_logic;
 	begin
-		if (spalte_up = '1') then
-			if (spalte > X"45") then
-				spalte_next <= "0000000";
-				zeile_tmp := to_integer(unsigned(zeile)) + 1;
-				zeile2_tmp := std_logic_vector(to_unsigned(zeile_tmp,8));
-				zeile_next <= hzeile(zeile2_tmp(6 downto 0));
-			else
-				spalte_tmp := to_integer(unsigned(spalte)) + 1;
-				spalte2_tmp := std_logic_vector(to_unsigned(spalte_tmp,8));
-				spalte_next <= hspalte(spalte2_tmp(6 downto 0));
-
-				zeile_next <= zeile;
-			end if;
-			spalte_up <= '0';
-		end if;
-	end process;
+		get_next <= '0';
+		new_i_next <= '0';
 
-	async_push_history : process (rx_new, rx_data, btn_a)
-	begin
-		if rx_new = '1' then
-			if rx_data = X"41" then
-				push_history_next <= '1';
-			else
-				push_history_next <= '0';
-			end if;
-		elsif btn_a = '1' then
-				push_history_next <= '1';
-		else
-			push_history_next <= '0';
-		end if;
-	end process async_push_history;
+		s_done_next <= '0';
+		spalte_next <= spalte;
+		zeile_next <= zeile;
+		tx_data_i_next <= tx_data_i;
+		spalte_up := '0';
 
-	output_pc : process (state, zeile, spalte, char)
-	begin
-		d_get <= '0';
-		spalte_next <= "0000000";
-		zeile_next <= "0000000";
-		case state is 
+		case state is
 			when IDLE =>
 				null;
 			when FETCH =>
-				d_zeile <= zeile_next;
-				d_spalte <= spalte_next;
-				d_get <= '1';
-				char_en <= '1';
-				-- wait for timer overflow
-				-- increment counter
+				get_next <= '1';
+				tx_data_i_next <= d_char;
 			when FORWARD =>
-				char_en <= '0';
-				tx_data <= char;
-				tx_new <= '1';
+				new_i_next <= '1';
+				if (tx_done_i = '1') then
+					spalte_up := '1';
+				end if;
+
 			when DONE =>
 				null;
-				-- be there for a single cycle and then 
 		end case;
+
+		if spalte_up = '1' then
+			if spalte = hspalte_max  then
+				if zeile = hzeile_max then
+					spalte_next <= 1;
+					zeile_next <= 1;
+					s_done_next <= '1';
+				else
+					spalte_next <= 1;
+					zeile_next <= zeile + 1;
+				end if;
+			else
+				spalte_next <= spalte + 1; --overflow here!
+				zeile_next <= zeile;
+			end if;
+		end if;
+
 	end process output_pc;
 
-	next_state_pc : process (rx_new, btn_a, d_done, tx_done)
+	next_state_pc : process (state, rx_new, rx_data, btn_a, d_done, tx_done_i, s_done)
 	begin
-		spalte_up <= '0';
+		state_next <= state;
 		case state is
 			when IDLE =>
-				if rx_new = '1' or btn_a = '1' then
+				if (rx_new = '1' and rx_data = x"0a" ) or btn_a = '1' then
 					state_next <= FETCH;
-					char <= d_char; --latch
 				end if;
 			when FETCH =>
 				if (d_done = '1') then
 					state_next <= FORWARD;
+				elsif (s_done = '1') then
+					state_next <= IDLE;
 				end if;
 			when FORWARD =>
-				if (tx_done = '1') then
+				if (tx_done_i = '1') then
 					state_next <= FETCH;
-					spalte_up <= '1';
 				end if;
 			when DONE =>
-				-- be there for a single cycle and then 
 				state_next <= IDLE;
 		end case;
 	end process next_state_pc;