X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fnorthbridge%2Fvia%2Fvx800%2Fexamples%2Fromstage.c;h=6fbc4ebad4c2560488b2974652434d4af7ddd794;hb=7b997053eb2fcde464f5f6a1e5c85d1ffb6b4e32;hp=80ee22c22a86900c9133cdcc0145785aec1b5867;hpb=5a1f5970857a5ad1fda0cf9d5945192408bf537b;p=coreboot.git diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c index 80ee22c22..6fbc4ebad 100644 --- a/src/northbridge/via/vx800/examples/romstage.c +++ b/src/northbridge/via/vx800/examples/romstage.c @@ -20,8 +20,6 @@ #define ASSEMBLY 1 #define __PRE_RAM__ -#define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 #include #include @@ -40,25 +38,22 @@ #include "lib/delay.c" #include "lib/memcpy.c" #include "cpu/x86/lapic/boot_cpu.c" - #include "driving_clk_phase_data.c" - #include "northbridge/via/vx800/raminit.h" #include "northbridge/via/vx800/raminit.c" -#include "cpu/x86/car/copy_and_run.c" -int acpi_is_wakeup_early_via_vx800(void) +static int acpi_is_wakeup_early_via_vx800(void) { device_t dev; u16 tmp, result; - print_debug("In acpi_is_wakeup_early_via_vx800\r\n"); + print_debug("In acpi_is_wakeup_early_via_vx800\n"); /* Power management controller */ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_LPC), 0); if (dev == PCI_DEV_INVALID) - die("Power management controller not found\r\n"); + die("Power management controller not found\n"); /* Set ACPI base address to I/O VX800_ACPI_IO_BASE. */ pci_write_config16(dev, 0x88, VX800_ACPI_IO_BASE | 0x1); @@ -70,7 +65,7 @@ int acpi_is_wakeup_early_via_vx800(void) result = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0; print_debug(" boot_mode="); print_debug_hex16(result); - print_debug("\r\n"); + print_debug("\n"); return result; } @@ -79,17 +74,14 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } - static void enable_mainboard_devices(void) { device_t dev; uint16_t values; - print_debug("In enable_mainboard_devices \r\n"); + print_debug("In enable_mainboard_devices \n"); - /* - Enable P2P Bridge Header for External PCI BUS. - */ + /* Enable P2P bridge Header for external PCI bus. */ dev = pci_locate_device(PCI_ID(0x1106, 0xa353), 0); pci_write_config8(dev, 0x4f, 0x41); } @@ -97,6 +89,7 @@ static void enable_mainboard_devices(void) static void enable_shadow_ram(void) { uint8_t shadowreg; + pci_write_config8(PCI_DEV(0, 0, 3), 0x80, 0xff); /* 0xf0000-0xfffff - ACPI tables */ shadowreg = pci_read_config8(PCI_DEV(0, 0, 3), 0x83); @@ -105,10 +98,8 @@ static void enable_shadow_ram(void) /* 0xe0000-0xeffff - elfload? */ pci_write_config8(PCI_DEV(0, 0, 3), 0x82, 0xff); - } - /* this table contains the value needed to be set before begin to init dram. Note: REV_Bx should be cared when porting a new board!!!!! */ @@ -184,7 +175,8 @@ static const struct VIA_PCI_REG_INIT_TABLE mNbStage1InitTbl[] = { #define gCom1Base 0x3f8 #define gCom2Base 0x2f8 -void EmbedComInit() + +void EmbedComInit(void) { u8 ByteVal; u16 ComBase; @@ -235,8 +227,6 @@ void EmbedComInit() ByteVal = (ByteVal & 0x3F) | 0xC0; pci_write_config8(PCI_DEV(0, 17, 0), 0x46, ByteVal); - - //enable embeded com1 and com2 D17F0RxB0[5,4] ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0xB0); ByteVal = ByteVal & 0xcf; @@ -298,9 +288,7 @@ void EmbedComInit() //while(1); } -/* cache_as_ram.inc jump to here -*/ -void amd64_main(unsigned long bist) +void main(unsigned long bist) { unsigned cpu_reset = 0; u16 boot_mode; @@ -313,7 +301,6 @@ void amd64_main(unsigned long bist) //enable_vx800_serial(); //uart_init(); - /* 1. D15F0 a) RxBAh = 71h @@ -362,7 +349,7 @@ g) Rx73h = 32h /* decide if this is a s3 wakeup or a normal boot */ boot_mode = acpi_is_wakeup_early_via_vx800(); /*add this, to transfer "cpu restart" to "cold boot" - When this boot is not a S3 resume, and PCI registers had been written, + When this boot is not a S3 resume, and PCI registers had been written, then this must be a cpu restart(result of os reboot cmd). so we need a real "cold boot". */ if ((boot_mode != 3) && (pci_read_config8(PCI_DEV(0, 0, 3), 0x80) != 0)) { @@ -371,18 +358,18 @@ g) Rx73h = 32h /*x86 cold boot I/O cmd */ enable_smbus(); - //smbus_fixup(&ctrl);// this fix does help vx800!, but vx855 no need this + //smbus_fixup(&ctrl);// this fix does help vx800!, but vx855 no need this if (bist == 0) { // CAR need mtrr untill mem is ok, so i disable this early_mtrr_init(); - //print_debug("doing early_mtrr\r\n"); + //print_debug("doing early_mtrr\n"); //early_mtrr_init(); } /* Halt if there was a built-in self test failure. */ report_bist_failure(bist); - print_debug("Enabling mainboard devices\r\n"); + print_debug("Enabling mainboard devices\n"); enable_mainboard_devices(); u8 Data; @@ -392,7 +379,7 @@ g) Rx73h = 32h Data = pci_read_config8(device, 0xf6); print_debug("NB chip revision ="); print_debug_hex8(Data); - print_debug("\r\n"); + print_debug("\n"); /* make NB ready before draminit */ via_pci_inittable(Data, mNbStage1InitTbl); @@ -405,7 +392,7 @@ g) Rx73h = 32h u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 }; DRAM_SYS_ATTR DramAttr; - print_debug("This is a S3 wakeup\r\n"); + print_debug("This is a S3 wakeup\n"); memset(&DramAttr, 0, sizeof(DRAM_SYS_ATTR)); /*Step1 DRAM Detection; DDR1 or DDR2; Get SPD Data; Rank Presence;64 or 128bit; Unbuffered or registered; 1T or 2T */ @@ -429,7 +416,7 @@ g) Rx73h = 32h DRAMRegFinalValue(&DramAttr); // I just copy this function from draminit to here! SetUMARam(); // I just copy this function from draminit to here! - print_debug("Resume from S3, RAM init was ignored\r\n"); + print_debug("Resume from S3, RAM init was ignored\n"); } else { ddr2_ram_setup(); ram_check(0, 640 * 1024); @@ -441,7 +428,7 @@ g) Rx73h = 32h /* For coreboot most time of S3 resume is the same as normal boot, so some memory area under 1M become dirty, - so before this happen, I need to backup the content of mem to top-mem. + so before this happen, I need to backup the content of mem to top-mem. I will reserve the 1M top-men in LBIO table in coreboot_table.c and recovery the content of 1M-mem in wakeup.c */ #if PAYLOAD_IS_SEABIOS==1 // @@ -449,7 +436,7 @@ g) Rx73h = 32h /* some idea of Libo.Feng at amd.com in http://www.coreboot.org/pipermail/coreboot/2008-December/043111.html I want move the 1M data, I have to set some MTRRs myself. */ /* seting mtrr before back memoy save s3 resume time about 0.14 seconds */ - /*because CAR stack use cache, and here to use cache , must be careful, + /*because CAR stack use cache, and here to use cache , must be careful, 1 during these mtrr code, must no function call, (after this mtrr, I think it should be ok to use function) 2 before stack switch, no use variable that have value set before this 3 due to 2, take care of "cpu_reset", I directlly set it to ZERO. @@ -462,7 +449,7 @@ g) Rx73h = 32h u32 memtop4 = *(u32 *) WAKE_MEM_INFO - 64 * 1024 - 0x100000 + 0xe0000; - /* __asm__ volatile ( + /* __asm__ volatile ( "movl $0x204, %%ecx\n\t" "xorl %%edx, %%edx\n\t" "movl %0,%%eax\n\t" @@ -478,7 +465,7 @@ g) Rx73h = 32h "wrmsr\n\t" ::"g"(memtop2) ); - __asm__ volatile ( + __asm__ volatile ( "movl $0x206, %%ecx\n\t" "xorl %%edx, %%edx\n\t" "movl %0,%%eax\n\t" @@ -494,7 +481,7 @@ g) Rx73h = 32h "wrmsr\n\t" ::"g"(memtop1) ); - __asm__ volatile ( + __asm__ volatile ( "movl $0x208, %ecx\n\t" "xorl %edx, %edx\n\t" "movl $0,%eax\n\t" @@ -512,23 +499,23 @@ g) Rx73h = 32h */ // WAKE_MEM_INFO is inited in get_set_top_available_mem in tables.c // these two memcpy not not be enabled if set the MTRR around this two lines. - /*__asm__ volatile ( + /*__asm__ volatile ( "movl $0, %%esi\n\t" "movl %0, %%edi\n\t" "movl $0xa0000, %%ecx\n\t" "shrl $2, %%ecx\n\t" - "rep movsd\n\t" - ::"g"(memtop3) + "rep movsd\n\t" + ::"g"(memtop3) ); - __asm__ volatile ( + __asm__ volatile ( "movl $0xe0000, %%esi\n\t" "movl %0, %%edi\n\t" "movl $0x20000, %%ecx\n\t" "shrl $2, %%ecx\n\t" - "rep movsd\n\t" - ::"g"(memtop4) + "rep movsd\n\t" + ::"g"(memtop4) );*/ - print_debug("copy memory to high memory to protect s3 wakeup vector code \r\n"); //this can have function call, because no variable used before this + print_debug("copy memory to high memory to protect s3 wakeup vector code \n"); //this can have function call, because no variable used before this memcpy((unsigned char *) ((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - 0x100000), (unsigned char *) 0, 0xa0000); @@ -537,122 +524,23 @@ g) Rx73h = 32h (unsigned char *) 0xe0000, 0x20000); /* restore the MTRR previously modified. */ -/* __asm__ volatile ( - "wbinvd\n\t" +/* __asm__ volatile ( + "wbinvd\n\t" "xorl %edx, %edx\n\t" "xorl %eax, %eax\n\t" "movl $0x204, %ecx\n\t" "wrmsr\n\t" - "movl $0x205, %ecx\n\t" - "wrmsr\n\t" + "movl $0x205, %ecx\n\t" + "wrmsr\n\t" "movl $0x206, %ecx\n\t" "wrmsr\n\t" - "movl $0x207, %ecx\n\t" - "wrmsr\n\t" - "movl $0x208, %ecx\n\t" - "wrmsr\n\t" - "movl $0x209, %ecx\n\t" - "wrmsr\n\t" + "movl $0x207, %ecx\n\t" + "wrmsr\n\t" + "movl $0x208, %ecx\n\t" + "wrmsr\n\t" + "movl $0x209, %ecx\n\t" + "wrmsr\n\t" );*/ } #endif -/* -the following code is copied from src/mainboard/tyan/s2735/romstage.c -Only the code around CLEAR_FIRST_1M_RAM is changed. -I remove all the code around CLEAR_FIRST_1M_RAM and #include "cpu/x86/car/cache_as_ram_post.c" -the CLEAR_FIRST_1M_RAM seems to make cpu/x86/car/cache_as_ram_post.c stop at somewhere, -and cpu/x86/car/cache_as_ram_post.c do not cache my $CONFIG_XIP_ROM_BASE+SIZE area. - -So, I use: #include "cpu/via/car/cache_as_ram_post.c". my via-version post.c have some diff with x86-version -*/ -#if 1 - { - /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */ - unsigned v_esp; - __asm__ volatile ("movl %%esp, %0\n\t":"=a" (v_esp) - ); -#if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "v_esp=%08x\r\n", v_esp); -#else - print_debug("v_esp="); - print_debug_hex32(v_esp); - print_debug("\r\n"); -#endif - } - -#endif -#if 1 - - cpu_reset_x: -// it seems that cpu_reset is not used before this, so I just reset it, (this is because the s3 resume, setting in mtrr and copy data may destroy -//stack - cpu_reset = 0; -#if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "cpu_reset = %08x\r\n", cpu_reset); -#else - print_debug("cpu_reset = "); - print_debug_hex32(cpu_reset); - print_debug("\r\n"); -#endif - - if (cpu_reset == 0) { - print_debug("Clearing initial memory region: "); - } - print_debug("No cache as ram now - "); - - /* store cpu_reset to ebx */ - __asm__ volatile ("movl %0, %%ebx\n\t"::"a" (cpu_reset) - ); - - -/* cancel these lines, CLEAR_FIRST_1M_RAM cause the cpu/x86/car/cache_as_ram_post.c stop at somewhere - - if(cpu_reset==0) { -#define CLEAR_FIRST_1M_RAM 1 -#include "cpu/via/car/cache_as_ram_post.c" - } - else { -#undef CLEAR_FIRST_1M_RAM -#include "cpu/via/car/cache_as_ram_post.c" - } -*/ -#include "cpu/via/car/cache_as_ram_post.c" -//#include "cpu/x86/car/cache_as_ram_post.c" - __asm__ volatile ( - /* set new esp *//* before CONFIG_RAMBASE */ - "subl %0, %%ebp\n\t" - "subl %0, %%esp\n\t":: - "a" ((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) - - CONFIG_RAMBASE) - ); - - { - unsigned new_cpu_reset; - - /* get back cpu_reset from ebx */ - __asm__ volatile ("movl %%ebx, %0\n\t":"=a" (new_cpu_reset) - ); - - /* We can not go back any more, we lost old stack data in cache as ram */ - if (new_cpu_reset == 0) { - print_debug("Use Ram as Stack now - done\r\n"); - } else { - print_debug("Use Ram as Stack now - \r\n"); - } -#if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "new_cpu_reset = %08x\r\n", new_cpu_reset); -#else - print_debug("new_cpu_reset = "); - print_debug_hex32(new_cpu_reset); - print_debug("\r\n"); -#endif - /*copy and execute coreboot_ram */ - copy_and_run(new_cpu_reset); - /* We will not return */ - } -#endif - - - print_debug("should not be here -\r\n"); - }