X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fnorthbridge%2Fvia%2Fvt8601%2Fnorthbridge.c;h=d2731c7074b677e58448da120a6e82a21aa67837;hb=4b42a62966527f18f3894af953b0757080424b00;hp=76d93f0ddbafbda37768185a4969ea43b328a9c3;hpb=f8ee1806ac524bc782c93eccc59ee3c929abddb9;p=coreboot.git diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c index 76d93f0dd..d2731c707 100644 --- a/src/northbridge/via/vt8601/northbridge.c +++ b/src/northbridge/via/vt8601/northbridge.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -17,9 +18,9 @@ * slower than normal, ethernet drops packets). * Apparently these registers govern some sort of bus master behavior. */ -static void northbridge_init(device_t dev) +static void northbridge_init(device_t dev) { - printk_spew("VT8601 random fixup ...\n"); + printk(BIOS_SPEW, "VT8601 random fixup ...\n"); pci_write_config8(dev, 0x70, 0xc0); pci_write_config8(dev, 0x71, 0x88); pci_write_config8(dev, 0x72, 0xec); @@ -44,61 +45,11 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x0601, /* 0x8601 is the AGP bridge? */ }; -#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM) - -static void pci_domain_read_resources(device_t dev) -{ - struct resource *resource; - - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0)); - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0)); - resource->limit = 0xffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -} - -static void ram_resource(device_t dev, unsigned long index, - unsigned long basek, unsigned long sizek) -{ - struct resource *resource; - - if (!sizek) { - return; - } - resource = new_resource(dev, index); - resource->base = ((resource_t)basek) << 10; - resource->size = ((resource_t)sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - -static void tolm_test(void *gp, struct device *dev, struct resource *new) -{ - struct resource **best_p = gp; - struct resource *best; - best = *best_p; - if (!best || (best->base > new->base)) { - best = new; - } - *best_p = best; -} - -static uint32_t find_pci_tolm(struct bus *bus) -{ - struct resource *min; - uint32_t tolm; - min = 0; - search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); - tolm = 0xffffffffUL; - if (min && tolm > min->base) { - tolm = min->base; - } - return tolm; -} +#if CONFIG_WRITE_HIGH_TABLES==1 +/* maximum size of high tables in KB */ +#define HIGH_TABLES_SIZE 64 +extern uint64_t high_tables_base, high_tables_size; +#endif static void pci_domain_set_resources(device_t dev) { @@ -108,29 +59,29 @@ static void pci_domain_set_resources(device_t dev) device_t mc_dev; uint32_t pci_tolm; - pci_tolm = find_pci_tolm(&dev->link[0]); - mc_dev = dev->link[0].children; + pci_tolm = find_pci_tolm(dev->link_list); + mc_dev = dev->link_list->children; if (mc_dev) { unsigned long tomk, tolmk; unsigned char rambits; int i, idx; - for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) { + for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) { unsigned char reg; reg = pci_read_config8(mc_dev, ramregs[i]); - /* these are ENDING addresses, not sizes. + /* these are ENDING addresses, not sizes. * if there is memory in this slot, then reg will be > rambits. - * So we just take the max, that gives us total. + * So we just take the max, that gives us total. * We take the highest one to cover for once and future coreboot * bugs. We warn about bugs. */ if (reg > rambits) rambits = reg; if (reg < rambits) - printk_err("ERROR! register 0x%x is not set!\n", + printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n", ramregs[i]); } - printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024); + printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024); tomk = rambits*8*1024; /* Compute the top of Low memory */ tolmk = pci_tolm >> 10; @@ -139,30 +90,31 @@ static void pci_domain_set_resources(device_t dev) */ tolmk = tomk; } + +#if CONFIG_WRITE_HIGH_TABLES == 1 + high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE* 1024; + printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); +#endif + /* Report the memory regions */ idx = 10; ram_resource(dev, idx++, 0, tolmk); } - assign_resources(&dev->link[0]); -} - -static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) -{ - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); - return max; + assign_resources(dev->link_list); } static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, - .enable_resources = enable_childrens_resources, - .init = 0, + .enable_resources = NULL, + .init = NULL, .scan_bus = pci_domain_scan_bus, -}; +}; static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) @@ -191,5 +143,5 @@ static void enable_dev(struct device *dev) struct chip_operations northbridge_via_vt8601_ops = { CHIP_NAME("VIA VT8601 Northbridge") - .enable_dev = enable_dev, + .enable_dev = enable_dev, };