X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fnorthbridge%2Fintel%2Fi945%2Framinit.c;h=77b9ade6c47f30f543f741b71efa792f002e492f;hb=d773fd370a92a6da2f7dbf91c085eb0df1f6f30d;hp=f65ccfaf42765eb74691e43a9720741d02b26b07;hpb=f98ad3ace0852159c6e716a5563a9c3df8cf76f3;p=coreboot.git

diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index f65ccfaf4..77b9ade6c 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -17,16 +17,19 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include <cpu/x86/mem.h>
+#include <console/console.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
+#include <pc80/mc146818rtc.h>
 #include <spd.h>
+#include <string.h>
+#include <arch/romcc_io.h>
 #include "raminit.h"
 #include "i945.h"
 
 /* Debugging macros. */
 #if CONFIG_DEBUG_RAM_SETUP
-#define PRINTK_DEBUG(x...)	printk_debug(x)
+#define PRINTK_DEBUG(x...)	printk(BIOS_DEBUG, x)
 #else
 #define PRINTK_DEBUG(x...)
 #endif
@@ -45,7 +48,12 @@
 #define RAM_EMRS_2			(0x1 << 21)
 #define RAM_EMRS_3			(0x2 << 21)
 
-static void do_ram_command(u32 command)
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+	return smbus_read_byte(device, address);
+}
+
+static __attribute__((noinline)) void do_ram_command(u32 command)
 {
 	u32 reg32;
 
@@ -62,6 +70,8 @@ static void do_ram_command(u32 command)
 	MCHBAR32(DCC) = reg32;  /* This is the actual magic */
 
 	PRINTK_DEBUG("...done\n");
+
+	udelay(1);
 }
 
 static void ram_read32(u32 offset)
@@ -75,12 +85,12 @@ static void ram_read32(u32 offset)
 static void sdram_dump_mchbar_registers(void)
 {
 	int i;
-	printk_debug("Dumping MCHBAR Registers\n");
+	printk(BIOS_DEBUG, "Dumping MCHBAR Registers\n");
 
 	for (i=0; i<0xfff; i+=4) {
 		if (MCHBAR32(i) == 0)
 			continue;
-		printk_debug("0x%04x: 0x%08x\n", i, MCHBAR32(i));
+		printk(BIOS_DEBUG, "0x%04x: 0x%08x\n", i, MCHBAR32(i));
 	}
 }
 #endif
@@ -88,40 +98,39 @@ static void sdram_dump_mchbar_registers(void)
 static int memclk(void)
 {
 	int offset = 0;
-#ifdef CHIPSET_I945GM
+#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
 	offset++;
 #endif
 	switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) {
 	case 1: return 400;
 	case 2: return 533;
 	case 3: return 667;
-	default: printk_debug("memclk: unknown register value %x\n", ((MCHBAR32(CLKCFG) >> 4) & 7) - offset);
+	default: printk(BIOS_DEBUG, "memclk: unknown register value %x\n", ((MCHBAR32(CLKCFG) >> 4) & 7) - offset);
 	}
 	return -1;
 }
 
-#ifdef CHIPSET_I945GM
-static int fsbclk(void)
+#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
+static u16 fsbclk(void)
 {
 	switch (MCHBAR32(CLKCFG) & 7) {
 	case 0: return 400;
 	case 1: return 533;
 	case 3: return 667;
-	default: printk_debug("fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
+	default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
 	}
-	return -1;
+	return 0xffff;
 }
-#endif
-#ifdef CHIPSET_I945GC
-static int fsbclk(void)
+#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
+static u16 fsbclk(void)
 {
 	switch (MCHBAR32(CLKCFG) & 7) {
 	case 0: return 1066;
 	case 1: return 533;
 	case 2: return 800;
-	default: printk_debug("fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
+	default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
 	}
-	return -1;
+	return 0xffff;
 }
 #endif
 
@@ -129,11 +138,11 @@ static int sdram_capabilities_max_supported_memory_frequency(void)
 {
 	u32 reg32;
 
-#ifdef MAXIMUM_SUPPORTED_FREQUENCY
-	return MAXIMUM_SUPPORTED_FREQUENCY;
+#if CONFIG_MAXIMUM_SUPPORTED_FREQUENCY
+	return CONFIG_MAXIMUM_SUPPORTED_FREQUENCY;
 #endif
 
-	reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4);
+	reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4); /* CAPID0 + 4 */
 	reg32 &= (7 << 0);
 
 	switch (reg32) {
@@ -157,7 +166,7 @@ static int sdram_capabilities_interleave(void)
 {
 	u32 reg32;
 
-	reg32 = pci_read_config8(PCI_DEV(0, 0x00,0), 0xe4);
+	reg32 = pci_read_config32(PCI_DEV(0, 0x00,0), 0xe4); /* CAPID0 + 4 */
 	reg32 >>= 25;
 	reg32 &= 1;
 
@@ -173,7 +182,7 @@ static int sdram_capabilities_dual_channel(void)
 {
 	u32 reg32;
 
-	reg32 = pci_read_config8(PCI_DEV(0, 0x00,0), 0xe4);
+	reg32 = pci_read_config32(PCI_DEV(0, 0x00,0), 0xe4); /* CAPID0 + 4 */
 	reg32 >>= 24;
 	reg32 &= 1;
 
@@ -200,15 +209,18 @@ static int sdram_capabilities_two_dimms_per_channel(void)
 	return (reg8 != 0);
 }
 
+// TODO check if we ever need this function
+#if 0
 static int sdram_capabilities_MEM4G_disable(void)
 {
 	u8 reg8;
 
-	reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5);
+	reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */
 	reg8 &= (1 << 0);
 
 	return (reg8 != 0);
 }
+#endif
 
 #define GFX_FREQUENCY_CAP_166MHZ	0x04
 #define GFX_FREQUENCY_CAP_200MHZ	0x03
@@ -226,7 +238,7 @@ static int sdram_capabilities_core_frequencies(void)
 	return (reg8);
 }
 
-static void sdram_detect_errors(void)
+static void sdram_detect_errors(struct sys_info *sysinfo)
 {
 	u8 reg8;
 	u8 do_reset = 0;
@@ -235,7 +247,7 @@ static void sdram_detect_errors(void)
 
 	if (reg8 & ((1<<7)|(1<<2))) {
 		if (reg8 & (1<<2)) {
-			printk_debug("SLP S4# Assertion Width Violation.\n");
+			printk(BIOS_DEBUG, "SLP S4# Assertion Width Violation.\n");
 			/* Write back clears bit 2 */
 			pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 			do_reset = 1;
@@ -243,7 +255,7 @@ static void sdram_detect_errors(void)
 		}
 
 		if (reg8 & (1<<7)) {
-			printk_debug("DRAM initialization was interrupted.\n");
+			printk(BIOS_DEBUG, "DRAM initialization was interrupted.\n");
 			reg8 &= ~(1<<7);
 			pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 			do_reset = 1;
@@ -255,7 +267,7 @@ static void sdram_detect_errors(void)
 		pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
 
 		if (do_reset) {
-			printk_debug("Reset required.\n");
+			printk(BIOS_DEBUG, "Reset required.\n");
 			outb(0x00, 0xcf9);
 			outb(0x0e, 0xcf9);
 			for (;;) asm("hlt"); /* Wait for reset! */
@@ -267,6 +279,29 @@ static void sdram_detect_errors(void)
 	reg8 |= (1<<7);
 	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 
+	/* clear self refresh if not wake-up from suspend */
+	if (sysinfo->boot_path != 2) {
+		MCHBAR8(0xf14) |= 3;
+	} else {
+		/* Validate self refresh config */
+		if (((sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED) ||
+		     (sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)) &&
+		    !(MCHBAR8(0xf14) & (1<<0))) {
+			do_reset = 1;
+		}
+		if (((sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED) ||
+		     (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)) &&
+		    !(MCHBAR8(0xf14) & (1<<1))) {
+			do_reset = 1;
+		}
+	}
+
+	if (do_reset) {
+		printk(BIOS_DEBUG, "Reset required.\n");
+		outb(0x00, 0xcf9);
+		outb(0x0e, 0xcf9);
+		for (;;) asm("hlt"); /* Wait for reset! */
+	}
 }
 
 /**
@@ -288,23 +323,22 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo)
 	/**
 	 * i945 supports two DIMMs, in two configurations:
 	 *
-	 * - single channel with two dimms
-	 * - dual channel with one dimm per channel
+	 * - single channel with two DIMMs
+	 * - dual channel with one DIMM per channel
 	 *
-	 * In practice dual channel mainboards have their spd at 0x50, 0x52
-	 * whereas single channel configurations have their spd at 0x50/x51
+	 * In practice dual channel mainboards have their SPD at 0x50/0x52
+	 * whereas single channel configurations have their SPD at 0x50/0x51.
 	 *
 	 * The capability register knows a lot about the channel configuration
-	 * but for now we stick with the information we gather from the SPD
-	 * ROMs
+	 * but for now we stick with the information we gather via SPD.
 	 */
 
 	if (sdram_capabilities_dual_channel()) {
 		sysinfo->dual_channel = 1;
-		printk_debug("This mainboard supports Dual Channel Operation.\n");
+		printk(BIOS_DEBUG, "This mainboard supports Dual Channel Operation.\n");
 	} else {
 		sysinfo->dual_channel = 0;
-		printk_debug("This mainboard supports only Single Channel Operation.\n");
+		printk(BIOS_DEBUG, "This mainboard supports only Single Channel Operation.\n");
 	}
 
 	/**
@@ -327,7 +361,7 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo)
 	 */
 
 	for (i=0; i<(2 * DIMM_SOCKETS); i++) {
-		u8 reg8, device = DIMM_SPD_BASE + i;
+		u8 reg8, device = DIMM0 + i;
 
 		/* Initialize the socket information with a sane value */
 		sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED;
@@ -340,10 +374,10 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo)
 		if (!sdram_capabilities_two_dimms_per_channel() && (i& 1))
 			continue;
 
-		printk_debug("DDR II Channel %d Socket %d: ", (i >> 1), (i & 1));
+		printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: ", (i >> 1), (i & 1));
 
 		if (spd_read_byte(device, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR2) {
-			printk_debug("N/A\n");
+			printk(BIOS_DEBUG, "N/A\n");
 			continue;
 		}
 
@@ -361,29 +395,29 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo)
 		case 0x08:
 			switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) {
 			case 1:
-				printk_debug("x8DDS\n");
+				printk(BIOS_DEBUG, "x8DDS\n");
 				sysinfo->dimm[i] = SYSINFO_DIMM_X8DDS;
 				break;
 			case 0:
-				printk_debug("x8DS\n");
+				printk(BIOS_DEBUG, "x8DS\n");
 				sysinfo->dimm[i] = SYSINFO_DIMM_X8DS;
 				break;
 			default:
-				printk_debug ("Unsupported.\n");
+				printk(BIOS_DEBUG, "Unsupported.\n");
 			}
 			break;
 		case 0x10:
 			switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) {
 			case 1:
-				printk_debug("x16DS\n");
+				printk(BIOS_DEBUG, "x16DS\n");
 				sysinfo->dimm[i] = SYSINFO_DIMM_X16DS;
 				break;
 			case 0:
-				printk_debug("x16SS\n");
+				printk(BIOS_DEBUG, "x16SS\n");
 				sysinfo->dimm[i] = SYSINFO_DIMM_X16SS;
 				break;
 			default:
-				printk_debug ("Unsupported.\n");
+				printk(BIOS_DEBUG, "Unsupported.\n");
 			}
 			break;
 		default:
@@ -398,7 +432,7 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo)
 	}
 
 	if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
-		printk_info("Channel 0 has no memory populated.\n");
+		printk(BIOS_INFO, "Channel 0 has no memory populated.\n");
 	}
 }
 
@@ -418,7 +452,7 @@ static void sdram_verify_package_type(struct sys_info * sysinfo)
 			continue;
 
 		/* Is the current DIMM a stacked DIMM? */
-		if (spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_DIMM_BANKS) & (1 << 4))
+		if (spd_read_byte(DIMM0 + i, SPD_NUM_DIMM_BANKS) & (1 << 4))
 			sysinfo->package = 1;
 	}
 }
@@ -435,7 +469,7 @@ static u8 sdram_possible_cas_latencies(struct sys_info * sysinfo)
 
 	for (i=0; i<2*DIMM_SOCKETS; i++) {
 		if (sysinfo->dimm[i] != SYSINFO_DIMM_NOT_POPULATED)
-			cas_mask &= spd_read_byte(DIMM_SPD_BASE + i, SPD_ACCEPTABLE_CAS_LATENCIES);
+			cas_mask &= spd_read_byte(DIMM0 + i, SPD_ACCEPTABLE_CAS_LATENCIES);
 	}
 
 	if(!cas_mask) {
@@ -496,7 +530,7 @@ static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8
 				continue;
 			}
 
-			current_cas_mask = spd_read_byte(DIMM_SPD_BASE + i, SPD_ACCEPTABLE_CAS_LATENCIES);
+			current_cas_mask = spd_read_byte(DIMM0 + i, SPD_ACCEPTABLE_CAS_LATENCIES);
 
 			while (current_cas_mask) {
 				int highest_supported_cas = 0, current_cas = 0;
@@ -518,11 +552,11 @@ static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8
 
 				idx = highest_supported_cas - current_cas;
 				PRINTK_DEBUG("idx=%d, ", idx);
-				PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[2*idx]));
-				PRINTK_DEBUG("tAC=%x", spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[(2*idx)+1]));
+				PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(DIMM0 + i, spd_lookup_table[2*idx]));
+				PRINTK_DEBUG("tAC=%x", spd_read_byte(DIMM0 + i, spd_lookup_table[(2*idx)+1]));
 
-				if (spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] &&
-						spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) {
+				if (spd_read_byte(DIMM0 + i, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] &&
+						spd_read_byte(DIMM0 + i, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) {
 					PRINTK_DEBUG(":    OK\n");
 					break;
 				}
@@ -557,7 +591,7 @@ static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8
 	}
 
 	if (sysinfo->memory_frequency && sysinfo->cas) {
-		printk_debug("Memory will be driven at %dMHz with CAS=%d clocks\n",
+		printk(BIOS_DEBUG, "Memory will be driven at %dMHz with CAS=%d clocks\n",
 				sysinfo->memory_frequency, sysinfo->cas);
 	} else {
 		die("Could not find common memory frequency and CAS\n");
@@ -586,7 +620,7 @@ static void sdram_detect_smallest_tRAS(struct sys_info * sysinfo)
 		if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 			continue;
 
-		reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
+		reg8 = spd_read_byte(DIMM0 + i, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
 		if (!reg8) {
 			die("Invalid tRAS value.\n");
 		}
@@ -600,7 +634,7 @@ static void sdram_detect_smallest_tRAS(struct sys_info * sysinfo)
 		die("DDR-II Module does not support this frequency (tRAS error)\n");
 	}
 
-	printk_debug("tRAS = %d cycles\n", tRAS_cycles);
+	printk(BIOS_DEBUG, "tRAS = %d cycles\n", tRAS_cycles);
 	sysinfo->tras = tRAS_cycles;
 }
 
@@ -626,7 +660,7 @@ static void sdram_detect_smallest_tRP(struct sys_info * sysinfo)
 		if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 			continue;
 
-		reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_ROW_PRECHARGE_TIME);
+		reg8 = spd_read_byte(DIMM0 + i, SPD_MIN_ROW_PRECHARGE_TIME);
 		if (!reg8) {
 			die("Invalid tRP value.\n");
 		}
@@ -641,7 +675,7 @@ static void sdram_detect_smallest_tRP(struct sys_info * sysinfo)
 		die("DDR-II Module does not support this frequency (tRP error)\n");
 	}
 
-	printk_debug("tRP = %d cycles\n", tRP_cycles);
+	printk(BIOS_DEBUG, "tRP = %d cycles\n", tRP_cycles);
 	sysinfo->trp = tRP_cycles;
 }
 
@@ -667,7 +701,7 @@ static void sdram_detect_smallest_tRCD(struct sys_info * sysinfo)
 		if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 			continue;
 
-		reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_RAS_TO_CAS_DELAY);
+		reg8 = spd_read_byte(DIMM0 + i, SPD_MIN_RAS_TO_CAS_DELAY);
 		if (!reg8) {
 			die("Invalid tRCD value.\n");
 		}
@@ -681,7 +715,7 @@ static void sdram_detect_smallest_tRCD(struct sys_info * sysinfo)
 		die("DDR-II Module does not support this frequency (tRCD error)\n");
 	}
 
-	printk_debug("tRCD = %d cycles\n", tRCD_cycles);
+	printk(BIOS_DEBUG, "tRCD = %d cycles\n", tRCD_cycles);
 	sysinfo->trcd = tRCD_cycles;
 }
 
@@ -707,7 +741,7 @@ static void sdram_detect_smallest_tWR(struct sys_info * sysinfo)
 		if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 			continue;
 
-		reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_WRITE_RECOVERY_TIME);
+		reg8 = spd_read_byte(DIMM0 + i, SPD_WRITE_RECOVERY_TIME);
 		if (!reg8) {
 			die("Invalid tWR value.\n");
 		}
@@ -721,7 +755,7 @@ static void sdram_detect_smallest_tWR(struct sys_info * sysinfo)
 		die("DDR-II Module does not support this frequency (tWR error)\n");
 	}
 
-	printk_debug("tWR = %d cycles\n", tWR_cycles);
+	printk(BIOS_DEBUG, "tWR = %d cycles\n", tWR_cycles);
 	sysinfo->twr = tWR_cycles;
 }
 
@@ -757,7 +791,7 @@ static void sdram_detect_smallest_tRFC(struct sys_info * sysinfo)
 			/* Can this happen? Go back to 127.5ns just to be sure
 			 * we don't run out of the array. This may be wrong
 			 */
-			printk_debug("DIMM %d is 1Gb x16.. Please report.\n", i);
+			printk(BIOS_DEBUG, "DIMM %d is 1Gb x16.. Please report.\n", i);
 			reg8 = 3;
 		}
 
@@ -773,7 +807,7 @@ static void sdram_detect_smallest_tRFC(struct sys_info * sysinfo)
 	}
 
 	sysinfo->trfc = tRFC_cycles[index];
-	printk_debug("tRFC = %d cycles\n", tRFC_cycles[index]);
+	printk(BIOS_DEBUG, "tRFC = %d cycles\n", tRFC_cycles[index]);
 }
 
 static void sdram_detect_smallest_refresh(struct sys_info * sysinfo)
@@ -788,7 +822,7 @@ static void sdram_detect_smallest_refresh(struct sys_info * sysinfo)
 		if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 			continue;
 
-		refresh = spd_read_byte(DIMM_SPD_BASE + i, SPD_REFRESH) & ~(1 << 7);
+		refresh = spd_read_byte(DIMM0 + i, SPD_REFRESH) & ~(1 << 7);
 
 		/* 15.6us */
 		if (!refresh)
@@ -805,7 +839,7 @@ static void sdram_detect_smallest_refresh(struct sys_info * sysinfo)
 
 		die("DDR-II module has unsupported refresh value\n");
 	}
-	printk_debug("Refresh: %s\n", sysinfo->refresh?"7.8us":"15.6us");
+	printk(BIOS_DEBUG, "Refresh: %s\n", sysinfo->refresh?"7.8us":"15.6us");
 }
 
 static void sdram_verify_burst_length(struct sys_info * sysinfo)
@@ -816,7 +850,7 @@ static void sdram_verify_burst_length(struct sys_info * sysinfo)
 		if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 			continue;
 
-		if (!(spd_read_byte(DIMM_SPD_BASE + i, SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8))
+		if (!(spd_read_byte(DIMM0 + i, SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8))
 			die("Only DDR-II RAM with burst length 8 is supported by this chipset.\n");
 	}
 }
@@ -1017,7 +1051,7 @@ static const u32 *slew_group_lookup(int dual_channel, int index)
 	return nc;
 }
 
-#ifdef CHIPSET_I945GM
+#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
 /* Strength multiplier tables */
 static const u8 dual_channel_strength_multiplier[] = {
 	0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
@@ -1072,8 +1106,7 @@ static const u8 single_channel_strength_multiplier[] = {
 	0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
 	0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11
 };
-#endif
-#ifdef CHIPSET_I945GC
+#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
 static const u8 dual_channel_strength_multiplier[] = {
 	0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
 	0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
@@ -1138,18 +1171,18 @@ static void sdram_rcomp_buffer_strength_and_slew(struct sys_info *sysinfo)
 
 	/* Dual Channel needs different tables. */
 	if (sdram_capabilities_dual_channel()) {
-		printk_debug("Programming Dual Channel RCOMP\n");
+		printk(BIOS_DEBUG, "Programming Dual Channel RCOMP\n");
 		strength_multiplier = dual_channel_strength_multiplier;
 		dual_channel = 1;
 		idx = 5 * sysinfo->dimm[0] +  sysinfo->dimm[2];
 	} else {
-		printk_debug("Programming Single Channel RCOMP\n");
+		printk(BIOS_DEBUG, "Programming Single Channel RCOMP\n");
 		strength_multiplier = single_channel_strength_multiplier;
 		dual_channel = 0;
 		idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[1];
 	}
 
-	printk_debug("Table Index: %d\n", idx);
+	printk(BIOS_DEBUG, "Table Index: %d\n", idx);
 
 	MCHBAR8(G1SC) = strength_multiplier[idx * 8 + 0];
 	MCHBAR8(G2SC) = strength_multiplier[idx * 8 + 1];
@@ -1198,7 +1231,7 @@ static void sdram_program_dll_timings(struct sys_info *sysinfo)
 	u32 chan0dll = 0, chan1dll = 0;
 	int i;
 
-	printk_debug ("Programming DLL Timings... \n");
+	printk(BIOS_DEBUG, "Programming DLL Timings... \n");
 
 	MCHBAR16(DQSMT) &= ~( (3 << 12) | (1 << 10) | ( 0xf << 0) );
 	MCHBAR16(DQSMT) |= (1 << 13) | (0xc << 0);
@@ -1250,7 +1283,7 @@ static void sdram_initialize_system_memory_io(struct sys_info *sysinfo)
 	u8 reg8;
 	u32 reg32;
 
-	printk_debug ("Initializing System Memory IO... \n");
+	printk(BIOS_DEBUG, "Initializing System Memory IO... \n");
 	/* Enable Data Half Clock Pushout */
 	reg8 = MCHBAR8(C0HCTC);
 	reg8 &= ~0x1f;
@@ -1292,7 +1325,7 @@ static void sdram_enable_system_memory_io(struct sys_info *sysinfo)
 {
 	u32 reg32;
 
-	printk_debug ("Enabling System Memory IO... \n");
+	printk(BIOS_DEBUG, "Enabling System Memory IO... \n");
 
 	reg32 = MCHBAR32(RCVENMT);
 	reg32 &= ~(0x3f << 6);
@@ -1309,7 +1342,7 @@ static void sdram_enable_system_memory_io(struct sys_info *sysinfo)
 	reg32 |= (1 << 6) | (1 << 4);
 	MCHBAR32(DRTST) = reg32;
 
-	asm volatile ("nop; nop;");
+	asm volatile ("nop; nop;" ::: "memory");
 
 	reg32 = MCHBAR32(DRTST);
 
@@ -1402,7 +1435,7 @@ static struct dimm_size sdram_get_dimm_size(u16 device)
 	/* Don't die here, I have not come across any of these to test what
 	 * actually happens.
 	 */
-	printk_err("Assymetric DIMMs are not supported by this chipset\n");
+	printk(BIOS_ERR, "Assymetric DIMMs are not supported by this chipset\n");
 
 	sz.side2 -= (rows & 0x0f);		/* Subtract out rows on side 1 */
 	sz.side2 += ((rows >> 4) & 0x0f);	/* Add in rows on side 2 */
@@ -1437,16 +1470,16 @@ static void sdram_detect_dimm_size(struct sys_info * sysinfo)
 		if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 			continue;
 
-		sz = sdram_get_dimm_size(DIMM_SPD_BASE + i);
+		sz = sdram_get_dimm_size(DIMM0 + i);
 
-		sysinfo->banks[i] = spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_BANKS_PER_SDRAM);	/* banks */
+		sysinfo->banks[i] = spd_read_byte(DIMM0 + i, SPD_NUM_BANKS_PER_SDRAM);	/* banks */
 
 		if (sz.side1 < 30)
 			die("DDR-II rank size smaller than 128MB is not supported.\n");
 
 		sysinfo->banksize[i * 2] = 1 << (sz.side1 - 28);
 
-		printk_debug("DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32 );
+		printk(BIOS_DEBUG, "DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32 );
 
 		if (!sz.side2)
 			continue;
@@ -1457,7 +1490,7 @@ static void sdram_detect_dimm_size(struct sys_info * sysinfo)
 
 		sysinfo->banksize[(i * 2) + 1] = 1 << (sz.side2 - 28);
 
-		printk_debug("DIMM %d side 1 = %d MB\n", i, sysinfo->banksize[(i * 2) + 1] * 32);
+		printk(BIOS_DEBUG, "DIMM %d side 1 = %d MB\n", i, sysinfo->banksize[(i * 2) + 1] * 32);
 	}
 }
 
@@ -1466,7 +1499,7 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo)
 	int i;
 	int cum0, cum1, tolud, tom;
 
-	printk_debug ("Setting RAM size... \n");
+	printk(BIOS_DEBUG, "Setting RAM size... \n");
 
 	cum0 = 0;
 	for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
@@ -1508,9 +1541,9 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo)
 
 	pci_write_config8(PCI_DEV(0,0,0), TOLUD, tolud);
 
-	printk_debug("C0DRB = 0x%08x\n", MCHBAR32(C0DRB0));
-	printk_debug("C1DRB = 0x%08x\n", MCHBAR32(C1DRB0));
-	printk_debug("TOLUD = 0x%04x\n", pci_read_config8(PCI_DEV(0,0,0), TOLUD));
+	printk(BIOS_DEBUG, "C0DRB = 0x%08x\n", MCHBAR32(C0DRB0));
+	printk(BIOS_DEBUG, "C1DRB = 0x%08x\n", MCHBAR32(C1DRB0));
+	printk(BIOS_DEBUG, "TOLUD = 0x%04x\n", pci_read_config8(PCI_DEV(0,0,0), TOLUD));
 
 	pci_write_config16(PCI_DEV(0,0,0), TOM, tom);
 
@@ -1522,7 +1555,7 @@ static int sdram_set_row_attributes(struct sys_info *sysinfo)
 	int i, value;
 	u16 dra0=0, dra1=0, dra = 0;
 
-	printk_debug ("Setting row attributes... \n");
+	printk(BIOS_DEBUG, "Setting row attributes... \n");
 	for(i=0; i < 2 * DIMM_SOCKETS; i++) {
 		u16 device;
 		u8 columnsrows;
@@ -1531,7 +1564,7 @@ static int sdram_set_row_attributes(struct sys_info *sysinfo)
 			continue;
 		}
 
-		device = DIMM_SPD_BASE + i;
+		device = DIMM0 + i;
 
 		value = spd_read_byte(device, SPD_NUM_ROWS);	/* rows */
 		columnsrows = (value & 0x0f);
@@ -1562,8 +1595,8 @@ static int sdram_set_row_attributes(struct sys_info *sysinfo)
 	MCHBAR16(C0DRA0) = dra0;
 	MCHBAR16(C1DRA0) = dra1;
 
-	printk_debug("C0DRA = 0x%04x\n", dra0);
-	printk_debug("C1DRA = 0x%04x\n", dra1);
+	printk(BIOS_DEBUG, "C0DRA = 0x%04x\n", dra0);
+	printk(BIOS_DEBUG, "C1DRA = 0x%04x\n", dra1);
 
 	return 0;
 }
@@ -1588,7 +1621,7 @@ static void sdram_set_bank_architecture(struct sys_info *sysinfo)
 		if (sysinfo->banks[i] != 8)
 			continue;
 
-		printk_spew("DIMM%d has 8 banks.\n", i);
+		printk(BIOS_SPEW, "DIMM%d has 8 banks.\n", i);
 
 		if (i & 1)
 			MCHBAR16(off32) |= 0x50;
@@ -1853,7 +1886,7 @@ static void sdram_set_channel_mode(struct sys_info *sysinfo)
 {
 	u32 reg32;
 
-	printk_debug("Setting mode of operation for memory channels...");
+	printk(BIOS_DEBUG, "Setting mode of operation for memory channels...");
 
 	if (sdram_capabilities_interleave() &&
 		    ( ( sysinfo->banksize[0] + sysinfo->banksize[1] +
@@ -1871,23 +1904,24 @@ static void sdram_set_channel_mode(struct sys_info *sysinfo)
 
 	if(sysinfo->interleaved) {
 		/* Dual Channel Interleaved */
-		printk_debug("Dual Channel Interleaved.\n");
+		printk(BIOS_DEBUG, "Dual Channel Interleaved.\n");
 		reg32 |= (1 << 1);
 	} else if (sysinfo->dimm[0] == SYSINFO_DIMM_NOT_POPULATED &&
 			sysinfo->dimm[1] == SYSINFO_DIMM_NOT_POPULATED) {
 		/* Channel 1 only */
-		printk_debug("Single Channel 1 only.\n");
+		printk(BIOS_DEBUG, "Single Channel 1 only.\n");
 		reg32 |= (1 << 2);
 	} else if (sdram_capabilities_dual_channel() && sysinfo->dimm[2] !=
 			SYSINFO_DIMM_NOT_POPULATED) {
 		/* Dual Channel Assymetric */
-		printk_debug("Dual Channel Assymetric.\n");
+		printk(BIOS_DEBUG, "Dual Channel Assymetric.\n");
 		reg32 |= (1 << 0);
 	} else {
 		/* All bits 0 means Single Channel 0 operation */
-		printk_debug("Single Channel 0 only.\n");
+		printk(BIOS_DEBUG, "Single Channel 0 only.\n");
 	}
 
+	/* Now disable channel XORing */
 	reg32 |= (1 << 10);
 
 	MCHBAR32(DCC) = reg32;
@@ -1902,7 +1936,7 @@ static void sdram_program_pll_settings(struct sys_info *sysinfo)
 	MCHBAR32(PLLMON) = 0x80800000;
 
 	sysinfo->fsb_frequency = fsbclk();
-	if (sysinfo->fsb_frequency == -1)
+	if (sysinfo->fsb_frequency == 0xffff)
 		die("Unsupported FSB speed");
 
 	/* Program CPCTL according to FSB speed */
@@ -1935,14 +1969,14 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
 #define VOLTAGE_1_05	0x00
 #define VOLTAGE_1_50	0x01
 
-	printk_debug ("Setting Graphics Frequency... \n");
+	printk(BIOS_DEBUG, "Setting Graphics Frequency... \n");
 
-	printk_debug("FSB: %d MHz ", sysinfo->fsb_frequency);
+	printk(BIOS_DEBUG, "FSB: %d MHz ", sysinfo->fsb_frequency);
 
 	voltage = VOLTAGE_1_05;
 	if (MCHBAR32(DFT_STRAP1) & (1 << 20))
 		voltage = VOLTAGE_1_50;
-	printk_debug("Voltage: %s ", (voltage==VOLTAGE_1_05)?"1.05V":"1.5V");
+	printk(BIOS_DEBUG, "Voltage: %s ", (voltage==VOLTAGE_1_05)?"1.05V":"1.5V");
 
 	/* Gate graphics hardware for frequency change */
 	reg8 = pci_read_config16(PCI_DEV(0,2,0), GCFC + 1);
@@ -1958,7 +1992,7 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
 		if (voltage == VOLTAGE_1_05)
 			freq = CRCLK_250MHz;
 		else
-			freq = CRCLK_400MHz;
+			freq = CRCLK_400MHz; /* 1.5V requires 400MHz */
 		break;
 	case GFX_FREQUENCY_CAP_250MHZ: freq = CRCLK_250MHz; break;
 	case GFX_FREQUENCY_CAP_200MHZ: freq = CRCLK_200MHz; break;
@@ -1972,12 +2006,12 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
 			freq = CRCLK_166MHz;
 	}
 
-	printk_debug("Render: ");
+	printk(BIOS_DEBUG, "Render: ");
 	switch (freq) {
-	case CRCLK_166MHz: printk_debug("166Mhz"); break;
-	case CRCLK_200MHz: printk_debug("200Mhz"); break;
-	case CRCLK_250MHz: printk_debug("250Mhz"); break;
-	case CRCLK_400MHz: printk_debug("400Mhz"); break;
+	case CRCLK_166MHz: printk(BIOS_DEBUG, "166Mhz"); break;
+	case CRCLK_200MHz: printk(BIOS_DEBUG, "200Mhz"); break;
+	case CRCLK_250MHz: printk(BIOS_DEBUG, "250Mhz"); break;
+	case CRCLK_400MHz: printk(BIOS_DEBUG, "400Mhz"); break;
 	}
 
 	if (i945_silicon_revision() == 0) {
@@ -2022,10 +2056,10 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
 
 	if (voltage == VOLTAGE_1_05) {
 		reg8 |= CDCLK_200MHz;
-		printk_debug(" Display: 200MHz\n");
+		printk(BIOS_DEBUG, " Display: 200MHz\n");
 	} else {
 		reg8 |= CDCLK_320MHz;
-		printk_debug(" Display: 320MHz\n");
+		printk(BIOS_DEBUG, " Display: 320MHz\n");
 	}
 	pci_write_config8(PCI_DEV(0,2,0), GCFC, reg8);
 
@@ -2046,39 +2080,35 @@ static void sdram_program_memory_frequency(struct sys_info *sysinfo)
 {
 	u32 clkcfg;
 	u8 reg8;
-	u8 offset = 0;
-#ifdef CHIPSET_I945GM
-	offset++;
-#endif
 
-	printk_debug ("Setting Memory Frequency... ");
+	printk(BIOS_DEBUG, "Setting Memory Frequency... ");
 
 	clkcfg = MCHBAR32(CLKCFG);
 
-	printk_debug("CLKCFG=0x%08x, ", clkcfg);
+	printk(BIOS_DEBUG, "CLKCFG=0x%08x, ", clkcfg);
 
 	clkcfg &= ~( (1 << 12) | (1 << 7) | ( 7 << 4) );
 
 	if (sysinfo->mvco4x) {
-		printk_debug("MVCO 4x, ");
+		printk(BIOS_DEBUG, "MVCO 4x, ");
 		clkcfg &= ~(1 << 12);
 	}
 
 	if (sysinfo->clkcfg_bit7) {
-		printk_debug("second VCO, ");
+		printk(BIOS_DEBUG, "second VCO, ");
 
 		clkcfg |= (1 << 7);
 	}
 
 	switch (sysinfo->memory_frequency) {
-	case 400: clkcfg |= ((1+offset) << 4); break;
-	case 533: clkcfg |= ((2+offset) << 4); break;
-	case 667: clkcfg |= ((3+offset) << 4); break;
+	case 400: clkcfg |= (2 << 4); break;
+	case 533: clkcfg |= (3 << 4); break;
+	case 667: clkcfg |= (4 << 4); break;
 	default: die("Target Memory Frequency Error");
 	}
 
 	if (MCHBAR32(CLKCFG) == clkcfg) {
-		printk_debug ("ok (unchanged)\n");
+		printk(BIOS_DEBUG, "ok (unchanged)\n");
 		return;
 	}
 
@@ -2098,7 +2128,7 @@ vco_update:
 	clkcfg |= (1 << 10);
 	MCHBAR32(CLKCFG) = clkcfg;
 
-	__asm__ __volatile__ (
+	asm volatile (
 		"	movl $0x100, %%ecx\n"
 		"delay_update:\n"
 		"	nop\n"
@@ -2108,7 +2138,7 @@ vco_update:
 		"	loop delay_update\n"
 		: /* No outputs */
 		: /* No inputs */
-		: "%ecx"
+		: "%ecx", "memory"
 		);
 
 	clkcfg &= ~(1 << 10);
@@ -2119,8 +2149,8 @@ cache_code:
 	goto vco_update;
 out:
 
-	printk_debug("CLKCFG=0x%08x, ", MCHBAR32(CLKCFG));
-	printk_debug ("ok\n");
+	printk(BIOS_DEBUG, "CLKCFG=0x%08x, ", MCHBAR32(CLKCFG));
+	printk(BIOS_DEBUG, "ok\n");
 }
 
 static void sdram_program_clock_crossing(void)
@@ -2130,7 +2160,7 @@ static void sdram_program_clock_crossing(void)
 	/**
 	 * We add the indices according to our clocks from CLKCFG.
 	 */
-#ifdef CHIPSET_I945GM
+#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
 	static const u32 data_clock_crossing[] = {
 		0x00100401, 0x00000000, /* DDR400 FSB400 */
 		0xffffffff, 0xffffffff, /*  nonexistant  */
@@ -2138,7 +2168,7 @@ static void sdram_program_clock_crossing(void)
 
 		0x08040120, 0x00000000,	/* DDR400 FSB533 */
 		0x00100401, 0x00000000, /* DDR533 FSB533 */
-		0xffffffff, 0xffffffff, /*  nonexistant  */
+		0x00010402, 0x00000000, /* DDR667 FSB533 - fake values */
 
 		0x04020120, 0x00000010,	/* DDR400 FSB667 */
 		0x10040280, 0x00000040, /* DDR533 FSB667 */
@@ -2175,8 +2205,7 @@ static void sdram_program_clock_crossing(void)
 		0xffffffff, 0xffffffff, /*  nonexistant  */
 	};
 
-#endif
-#ifdef CHIPSET_I945GC
+#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
 	/* i945 G/P */
 	static const u32 data_clock_crossing[] = {
 		0xffffffff, 0xffffffff, /*  nonexistant  */
@@ -2185,7 +2214,7 @@ static void sdram_program_clock_crossing(void)
 
 		0x10080201, 0x00000000,	/* DDR400 FSB533 */
 		0x00100401, 0x00000000, /* DDR533 FSB533 */
-		0xffffffff, 0xffffffff, /*  nonexistant  */
+		0x00010402, 0x00000000, /* DDR667 FSB533 - fake values */
 
 		0xffffffff, 0xffffffff, /*  nonexistant  */
 		0xffffffff, 0xffffffff, /*  nonexistant  */
@@ -2207,7 +2236,7 @@ static void sdram_program_clock_crossing(void)
 
 		0x00010800, 0x00000402,	/* DDR400 FSB533 */
 		0x01000400, 0x00000200, /* DDR533 FSB533 */
-		0xffffffff, 0xffffffff, /*  nonexistant  */
+		0x00020904, 0x00000000, /* DDR667 FSB533 - fake values */
 
 		0xffffffff, 0xffffffff, /*  nonexistant  */
 		0xffffffff, 0xffffffff, /*  nonexistant  */
@@ -2223,28 +2252,28 @@ static void sdram_program_clock_crossing(void)
 	};
 #endif
 
-	printk_debug("Programming Clock Crossing...");
+	printk(BIOS_DEBUG, "Programming Clock Crossing...");
 
-	printk_debug("MEM=");
+	printk(BIOS_DEBUG, "MEM=");
 	switch (memclk()) {
-	case 400:	printk_debug("400"); idx += 0; break;
-	case 533:	printk_debug("533"); idx += 2; break;
-	case 667:	printk_debug("667"); idx += 4; break;
-	default: printk_debug("RSVD %x", memclk()); return;
+	case 400:	printk(BIOS_DEBUG, "400"); idx += 0; break;
+	case 533:	printk(BIOS_DEBUG, "533"); idx += 2; break;
+	case 667:	printk(BIOS_DEBUG, "667"); idx += 4; break;
+	default: printk(BIOS_DEBUG, "RSVD %x", memclk()); return;
 	}
 
-	printk_debug(" FSB=");
+	printk(BIOS_DEBUG, " FSB=");
 	switch (fsbclk()) {
-	case 400:	printk_debug("400"); idx += 0; break;
-	case 533:	printk_debug("533"); idx += 6; break;
-	case 667:	printk_debug("667"); idx += 12; break;
-	case 800:	printk_debug("800"); idx += 18; break;
-	case 1066:	printk_debug("1066"); idx += 24; break;
-	default: printk_debug("RSVD %x\n", fsbclk()); return;
+	case 400:	printk(BIOS_DEBUG, "400"); idx += 0; break;
+	case 533:	printk(BIOS_DEBUG, "533"); idx += 6; break;
+	case 667:	printk(BIOS_DEBUG, "667"); idx += 12; break;
+	case 800:	printk(BIOS_DEBUG, "800"); idx += 18; break;
+	case 1066:	printk(BIOS_DEBUG, "1066"); idx += 24; break;
+	default: printk(BIOS_DEBUG, "RSVD %x\n", fsbclk()); return;
 	}
 
 	if (command_clock_crossing[idx]==0xffffffff) {
-		printk_debug("Invalid MEM/FSB combination!\n");
+		printk(BIOS_DEBUG, "Invalid MEM/FSB combination!\n");
 	}
 
 	MCHBAR32(CCCFT + 0) = command_clock_crossing[idx];
@@ -2255,7 +2284,7 @@ static void sdram_program_clock_crossing(void)
 	MCHBAR32(C1DCCFT + 0) = data_clock_crossing[idx];
 	MCHBAR32(C1DCCFT + 4) = data_clock_crossing[idx + 1];
 
-	printk_debug("... ok\n");
+	printk(BIOS_DEBUG, "... ok\n");
 }
 
 static void sdram_disable_fast_dispatch(void)
@@ -2395,7 +2424,7 @@ static void sdram_post_jedec_initialization(struct sys_info *sysinfo)
 	if (sysinfo->interleaved) {
 
 		reg32 = MCHBAR32(DCC);
-#if CHANNEL_XOR_RANDOMIZATION
+#if CONFIG_CHANNEL_XOR_RANDOMIZATION
 		reg32 &= ~(1 << 10);
 		reg32 |= (1 << 9);
 #else
@@ -2570,7 +2599,7 @@ static void sdram_power_management(struct sys_info *sysinfo)
 #ifdef C2_SELF_REFRESH_DISABLE
 
 	if (integrated_graphics) {
-		printk_debug("C2 self-refresh with IGD\n");
+		printk(BIOS_DEBUG, "C2 self-refresh with IGD\n");
 		MCHBAR16(MIPMC4) = 0x0468;
 		MCHBAR16(MIPMC5) = 0x046c;
 		MCHBAR16(MIPMC6) = 0x046c;
@@ -2617,6 +2646,7 @@ static void sdram_thermal_management(void)
 	 * 0x30/0x32.
 	 */
 
+	/* TODO This is not implemented yet. Volunteers? */
 }
 
 static void sdram_save_receive_enable(void)
@@ -2648,7 +2678,7 @@ static void sdram_save_receive_enable(void)
 	values[3] |= (reg32 >> (24 - 4)) & 0xf0;
 
 	/* coreboot only uses bytes 0 - 127 for its CMOS values so far
-	 * so we grad bytes 128 - 131 to save the receive enable values
+	 * so we grab bytes 128 - 131 to save the receive enable values
 	 */
 
 	for (i=0; i<4; i++)
@@ -2729,7 +2759,7 @@ static void sdram_on_die_termination(struct sys_info *sysinfo)
 
 	if ( !(sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED &&
 			sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) ) {
-		printk_debug("one dimm per channel config.. \n");
+		printk(BIOS_DEBUG, "one dimm per channel config.. \n");
 
 		reg32 = MCHBAR32(C0ODT);
 		reg32 &= ~(7 << 28);
@@ -2766,10 +2796,9 @@ static void sdram_enable_memory_clocks(struct sys_info *sysinfo)
 {
 	u8 clocks[2] = { 0, 0 };
 
-#ifdef CHIPSET_I945GM
+#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
 #define CLOCKS_WIDTH 2
-#endif
-#ifdef CHIPSET_I945GC
+#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
 #define CLOCKS_WIDTH 3
 #endif
 	if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED)
@@ -2784,15 +2813,11 @@ static void sdram_enable_memory_clocks(struct sys_info *sysinfo)
 	if (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)
 		clocks[1] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH;
 
-#ifdef OVERRIDE_CLOCK_DISABLE
+#if CONFIG_OVERRIDE_CLOCK_DISABLE
 	/* Usually system firmware turns off system memory clock signals
 	 * to unused SO-DIMM slots to reduce EMI and power consumption.
 	 * However, the Kontron 986LCD-M does not like unused clock
 	 * signals to be disabled.
-	 * If other similar mainboard occur, it would make sense to make
-	 * this an entry in the sysinfo structure, and pre-initialize that
-	 * structure in the mainboard's romstage.c main() function.
-	 * For now an #ifdef will do.
 	 */
 
 	clocks[0] = 0xf; /* force all clock gate pairs to enable */
@@ -2833,7 +2858,7 @@ static void sdram_jedec_enable(struct sys_info *sysinfo)
 			continue;
 		}
 
-		printk_debug("jedec enable sequence: bank %d\n", i);
+		printk(BIOS_DEBUG, "jedec enable sequence: bank %d\n", i);
 		switch (i) {
 		case 0:
 			/* Start at address 0 */
@@ -2846,7 +2871,7 @@ static void sdram_jedec_enable(struct sys_info *sysinfo)
 			}
 		default:
 			if (nonzero != -1) {
-				printk_debug("bankaddr from bank size of rank %d\n", nonzero);
+				printk(BIOS_DEBUG, "bankaddr from bank size of rank %d\n", nonzero);
 				bankaddr += sysinfo->banksize[nonzero] <<
 					(sysinfo->interleaved ? 26 : 25);
 				break;
@@ -3009,9 +3034,7 @@ void sdram_initialize(int boot_path)
 	struct sys_info sysinfo;
 	u8 reg8, cas_mask;
 
-	sdram_detect_errors();
-
-	printk_debug ("Setting up RAM controller.\n");
+	printk(BIOS_DEBUG, "Setting up RAM controller.\n");
 
 	memset(&sysinfo, 0, sizeof(sysinfo));
 
@@ -3020,6 +3043,9 @@ void sdram_initialize(int boot_path)
 	/* Look at the type of DIMMs and verify all DIMMs are x8 or x16 width */
 	sdram_get_dram_configuration(&sysinfo);
 
+	/* If error, do cold boot */
+	sdram_detect_errors(&sysinfo);
+
 	/* Check whether we have stacked DIMMs */
 	sdram_verify_package_type(&sysinfo);
 
@@ -3132,7 +3158,7 @@ void sdram_initialize(int boot_path)
 	reg8 &= ~(1 << 7);
 	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 
-	printk_debug("RAM initialization finished.\n");
+	printk(BIOS_DEBUG, "RAM initialization finished.\n");
 
 	sdram_setup_processor_side();
 }