X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=blobdiff_plain;f=src%2Fnorthbridge%2Fintel%2Fi855%2Framinit.h;h=2ac0fde62dc8812371dba2c703133723869c440b;hb=d773fd370a92a6da2f7dbf91c085eb0df1f6f30d;hp=dbd0be6927751a967a48969a80c827421b3a95ac;hpb=c264ad930a2579dc235de0c95842374e89ff5d6a;p=coreboot.git

diff --git a/src/northbridge/intel/i855/raminit.h b/src/northbridge/intel/i855/raminit.h
index dbd0be692..2ac0fde62 100644
--- a/src/northbridge/intel/i855/raminit.h
+++ b/src/northbridge/intel/i855/raminit.h
@@ -18,9 +18,14 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#ifndef RAMINIT_H
-#define RAMINIT_H
+#ifndef NORTHBRIDGE_INTEL_I855_RAMINIT_H
+#define NORTHBRIDGE_INTEL_I855_RAMINIT_H
 
+/* i855 Northbridge PCI device */
+#define NORTHBRIDGE         PCI_DEV(0, 0, 0)
+#define NORTHBRIDGE_MMC     PCI_DEV(0, 0, 1)
+
+/* The i855 supports max. 2 dual-sided SO-DIMMs. */
 #define DIMM_SOCKETS 2
 
 struct mem_controller {
@@ -30,5 +35,4 @@ struct mem_controller {
 
 void sdram_initialize(int controllers, const struct mem_controller *ctrl);
 
-
-#endif /* RAMINIT_H */
+#endif /* NORTHBRIDGE_INTEL_I855_RAMINIT_H */